JPH1092182A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive high access speed which is determined by a precharge period at the time of random access of an S-RAM device. SOLUTION: Data I/O ports (68 and 69) and (70 and 71) of system-(a) and system-(b) are provided on a memory cell 15, and bit lines (40 and 41) and (42 and 43) of the respective systems are made to be independently prechargeable. If the system-(b) is precharged while the system-(a) is selected by a word line and data are read/written out of/into the system-(a), a precharge period is outwardly eliminated, so that a high access speed can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a static semiconductor memory device that can be accessed randomly.

[0002]

2. Description of the Related Art SRAM as an example of a semiconductor memory device
(Static random access memory) includes a memory cell array in which a plurality of static memory cells are arranged in a matrix. The selection terminal of the memory cell is coupled to a word line for each row direction, and the data input / output terminal of the memory cell is coupled to a complementary bit line (also referred to as a complementary data line) for each column direction. Each complementary bit line includes a plurality of column selection switches one-to-one coupled to the complementary bit lines, and is commonly connected to a complementary common bit line via a column selection switch (column switch circuit).

An address signal input from the outside is transmitted to a row address decoder and a column address decoder via an address buffer arranged correspondingly. When a word line corresponding to an input address signal is driven to a selected level based on a decode output of a row address decoder, a memory cell coupled to the word line is selected.

Further, a column selection switch is turned on based on the decode output of the column address decoder, and the selected memory cell conducts to the complementary common bit line. At this time, the potential of the complementary common bit line is amplified by a sense amplifier included in the data input / output circuit, and further output to the outside via an output buffer or the like.

When write data is externally supplied to an input buffer included in a data input / output circuit, a complementary common bit line is driven in accordance with the write data, and thereby, via a complementary bit line selected by an address signal. Thus, charge information corresponding to the data is stored in a predetermined memory cell.

Immediately before accessing a memory cell, a pair of complementary bit lines are precharged to a "1" level for a predetermined time (protection against erroneous writing), and a precharge MO
After turning off the S transistor, the memory cell is accessed. For this, a signal synchronized with the access of the memory cell is required as a signal for controlling on / off of the precharge MOS transistor. Therefore, when reading and writing are performed continuously, the precharge operation and the read / write operation are performed alternately.

Further, as disclosed in, for example, Japanese Patent Application Laid-Open No. 7-211076, in a semiconductor memory device in which static memory cells are integrated, data read from the static memory cells to bit lines is held. And a column switch for selectively transmitting data held in the latch circuit to the sense amplifier, the semiconductor memory device has the same row address and sequentially changes the column address. During this period, the target data can be output by inhibiting the precharge of the bit line and sequentially outputting the data in the latch circuit.

As a result, the time required for row address decoding, word line driving, and bit line precharge in the period can be omitted, and the speed of the semiconductor memory device can be increased.

Further, during a period in which the row address is the same and the column address is sequentially changed, data from the outside is sequentially latched by the latch circuit, and the data for one row is simultaneously transferred to the memory cells, thereby achieving row address decoding. , The time required for word line drive and bit line precharge can be omitted,
A high speed semiconductor memory device is achieved.

[0010]

However, according to the above-described conventional technique, when an access requiring a change in row address is performed, such as when a cell is accessed at random or when a change in column address is not sufficient, for example. Since the precharge operation must be performed again and the cells must be accessed after the precharge period has elapsed, there is a problem that the access operation speed is reduced by the length of the precharge period.

Accordingly, an object of the present invention is to provide a semiconductor memory device in which the access speed at the time of random access does not decrease.

[0012]

A semiconductor memory device according to the present invention is provided in correspondence with a memory cell each having a plurality of data input / output ports and a corresponding one of the data input / output ports of the memory cell. A plurality of data input / output bit lines respectively connected to the data input / output ports of the corresponding system, and a plurality of selection word lines provided corresponding to the data input / output bit lines of the respective systems, A precharge means for independently performing precharge control on each system of the data input / output bit lines; and a plurality of system word lines and a plurality of systems when inputting / outputting data to / from the memory cell. Selecting means for selecting a corresponding set of data input / output bit lines, a set of word lines and data input / output bit lines selected by the selecting means. Period, characterized in that it comprises a means for controlling so as to form a pre-charge of the data input bit line of other strains of non-selective in that performing input and output of data using.

Another semiconductor memory device according to the present invention is provided so as to correspond to a memory cell each having first and second data input / output ports and to each data input / output port of the memory cell. First and second data input / output bit lines respectively connected to the corresponding system data input / output ports, and second data input / output bit lines provided corresponding to the first and second data input / output bit lines, respectively. A precharge means for performing precharge control independently on each of the first and second selection word lines and the first and second data input / output bit lines; and During a precharge period for the first system data input / output bit line, a set of the second system selection word line and the corresponding second system data input / output bit line is selected and data is selected. Characterized in that it comprises a control means for controlling so as to form the input and output.

The operation of the present invention is described as follows. Each memory cell is configured to have a plurality of data input / output ports, and a data input / output bit line and a selected word line are provided for each of these ports. The precharge period of each system is performed during the data input / output period of another system.

[0015]

Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an SRAM according to an embodiment of the present invention.
FIG. 3 is a block diagram of the configuration of FIG. In FIG. 1, reference numeral 100 denotes a memory cell array in which a plurality of static memory cells MC15 (hereinafter, referred to as “memory cells MC15”) are arranged in a matrix.

As a peripheral circuit, a control circuit (T-CTRL) 4 and a data output multiplexer (MU)
X) 22, row address buffer (X-buf) 1, column address buffer (Y-buf) 12, control signal buffer (C-buf) 11, data input buffer (I-bu).
f) 24, data output buffer (O-buf) 23, a
System row address latch (Xa-LCH) 2, system b row address latch (Xb-LCH) 5, system a column address latch (Ya-LCH) 7, system b column address latch (Y
b-LCH) 10, a system row address decoder (Xa-
DEC) 3, b-system row address decoder (xb-DE)
C) 6, a system column address decoder (Ya-DEC)
8, a b-system column address decoder (Yb-DEC) 9 is provided.

Further, as peripheral circuits, a-system precharge circuit (LOADa) 13, b-system precharge circuit (LOADb) 14, a-system column selection switch (Ya-S)
W) 16, b-system row selection switch (Yb-SW) 17,
a-system sense amplifier (SAMP-a) 18, b-system sense amplifier (SAMP-b) 19, a-system write amplifier (WAMP-a) 20, b-system write amplifier (WAMP)
-B) 21, a system word line 44, b system word line 4
5, a-system complementary bit lines 40 and 41, b-system complementary bit lines 42 and 43, a-system complementary bit lines 48 and 49,
The b system complementary common bit lines 50 and 51, the a system column selection line 46, and the b system column selection line 47 are provided.

As signal lines, a system precharge control signal 33, b system precharge control signal 34, a system row address latch control signal 25, b system row address latch control signal 27, a system column address latch control signal 2
9, b-system column address latch control signal 31, a-system row address decoder control signal 26, b-system row address decoder control signal 28, a-system column address decoder control signal 3
0, b system column address decoder control signal 32, a system sense amplifier control signal 35, b system sense amplifier control signal 37, a system write amplifier control signal 36, b system write amplifier control signal 38, data output multiplexer control signal 39, Common row address bus 52, a system row address line 53, b system row address line 54, common column address bus 5
8, a system column address line 55, b system column address line 5
6, an external control signal 57 is provided. Control signal 25
To 39 are called internal control signals.

In the present invention, data is read from one data input / output terminal to each memory cell MC15,
It has two equivalent paths for writing and two such selection mechanisms. One is referred to as a system and the other is referred to as b system.

FIG. 2 shows a circuit example of the memory cell MC15. The memory cell is of a latch type of inverters 72 and 73 whose inputs and outputs are cross-connected to each other. For this one memory cell, a pair of bit lines 4 of system a
In addition to 0 and 41, b-system bit lines 42 and 43, a-system word line 44, and b-system word line 45 are provided.

The a-system bit lines 40 and 41 are connected to the a-system input / output ports 68 and 69 of the memory cell.
The b-system bit lines 42 and 43 are connected to the b-system input / output ports 70 and 71, respectively. The input / output ports 68 and 69 are connected to input / output connection points of the inverters 72 and 73 via transfer gates 74 and 75, respectively.
6, 77 are also connected to the input / output connection points of the inverters 72, 73, respectively.

The gate terminals 64 and 65 of the transfer gates 74 and 75 of the system a are connected to the word line 44 of the system a, and the gate terminals 66 and 67 of the transfer gates 76 and 77 of the system b are connected to the word line 44 of the system b. 45.

Of the (k + 1) -bit address signals A0 to Ak input from the outside, the upper (ku) bit A
u + 1 to Ak are input as row addresses to a row address buffer X-buf1 arranged corresponding thereto, and the output of the row address buffer X-buf1 is connected to a common row address bus 52.

The lower (u + 1) bits A0-Au of the address signals A0-Ak are used as column addresses in a column address buffer Y-buf correspondingly arranged.
12 and the output of the column address buffer Y-buf12 is connected to a common column address bus 58.

A control signal (including a chip select, a write enable, etc.) input from the outside is input to a control signal buffer 11 corresponding to the control signal.
The output of 1 is connected to an external control signal 57.

The data input terminal of the a-system row address latch 2 is connected to the common row address bus 52, the latch control signal terminal is connected to the a-system row address latch control signal 25, and the data output terminal is connected to the a-system row address latch 2. The address line 53 is connected. An a-system row address line 53 is connected to a data input terminal of the a-system row address decoder 3, an a-system row address decoder control signal 26 is connected to a decoder control signal input terminal, and an a-system word is connected to a decode signal output terminal. Line 44 is connected.

A common row address bus 52 is connected to the data input terminal of the b-system row address latch 5, and the b-system row address latch control signal 27 is connected to the latch control signal input terminal.
Is connected, and the data output terminal is connected to the b-system row address line 5.
4 are connected. The data input terminal of the b-system row address decoder 6 is connected to the b-system row address line 54, the decoder control signal input terminal is connected to the b-system row address decoder control signal 28, and the decode signal output terminal is connected to the b-system word. Line 45 is connected.

A data input terminal of the control circuit T-CTRL4 is connected to a common row address bus 52 and a common column address bus 58, an external control signal input terminal is connected to an external control signal 57, and a control signal output terminal. Internal control signals 25 to 39 are connected.

The data input terminal of the a-system column address latch 7 is connected to a common column address bus 58, and the latch control signal input terminal is connected to the a-system column address latch control signal 29.
Is connected, and the data output terminal is connected to the a-system column address line 5.
5 is connected. The data input terminal of the a-system column address decoder 8 is connected to the a-system column address line 55, the decoder control signal input terminal is connected to the a-system column address decoder control signal 30, and the decode signal output terminal is connected to the a-system column address decoder 55. The selection line 46 is connected.

A common column address bus 58 is connected to the data input terminal of the b-system column address latch 10, and the b-system column address latch control signal 3 is connected to the latch control signal input terminal.
1 is connected, and the b-system column address line 56 is connected to the data output terminal. A b-system column address line 56 is connected to a data input terminal of the b-system column address decoder 9, a b-system column address decoder control signal 32 is connected to a decoder control signal input terminal, and b is connected to a decode signal output terminal.
The system column selection line 47 is connected.

An a-system precharge control signal 33 is connected to a precharge control signal input terminal of the a-system precharge circuit LOADa13, and a
System complementary bit lines 40 and 41 are connected. The b-system precharge control signal 34 is connected to the precharge control signal input terminal of the b-system precharge circuit LOADb14, and the b-system complementary bit line 4 is connected to the precharge output terminal.
2, 43 are connected.

The a-system word line 44 is connected to the a-system cell selection terminal of the memory cell MC15, the b-system word line 45 is connected to the b-system cell selection terminal, and the a-system cell data input / output terminal is connected to the a-system cell data input / output terminal. The complementary bit lines 40 and 41 are connected, and the b-system complementary bit lines 42 and 43 are connected to the b-system cell data input / output terminals.

An a-system column selection line 46 is connected to a column selection input terminal of the a-system column selection switch 16, and a-system complementary bit lines 40 and 41 are connected to data input / output terminals. The terminals are connected to a-system complementary common bit lines 48 and 49.

A b-system column selection line 47 is connected to a column selection input terminal of the b-system column selection switch 17, and b-system complementary bit lines 42 and 43 are connected to data input / output terminals. The terminals are connected to b-system complementary common bit lines 50 and 51.

An a-system sense amplifier control signal 35 is connected to a sense amplifier control signal input terminal of the a-system sense amplifier 18, and a-system complementary common bit lines 48 and 49 are connected to the sense amplifier data input terminal. The data line 59 is connected to the data output terminal.

The b-system sense amplifier 19 has a sense amplifier control signal input terminal connected to a b-system sense amplifier control signal 37, a sense amplifier data input terminal connected to b-system complementary common bit lines 50 and 51, and a sense amplifier. The data line is connected to the data output terminal.

A data line 59 is connected to the data input terminal 1 of the data output multiplexer 22, a data line 60 is connected to the data input terminal 2, and a data output multiplexer control signal 39 is connected to the data output multiplexer control signal input terminal. Connected, and the data line 6 is connected to the data output terminal.
3 are connected. A data line 63 is connected to a data input terminal of the data output buffer 23, and a data output terminal is connected to an external data bus.

The data input terminal of the a-system write amplifier 20 is connected to the data line 61, the write amplifier control signal input terminal is connected to the write amplifier control signal 36, and the data output terminal is connected to the a-system complementary common bit line 48. , 49 are connected.

A data line 62 is connected to a data input terminal of the b-system write amplifier 21, a write amplifier control signal 38 is connected to a write amplifier control signal input terminal, and a b-system complementary common bit line 50 is connected to a data output terminal. , 51 are connected. Data lines 61 and 62 are connected to data output terminals of the data input buffer 24, and data input terminals are connected to an external data bus.

In the memory array 100 in which a plurality of memory cells MC15 are arranged in a matrix, the memory cells MC15 are arranged in 2 (ku) powers in the column direction and 2 u powers in the row direction. .

FIG. 3 is a timing chart at the time of reading in this embodiment, and FIG. 4 is a timing chart at the time of writing.

Addresses A1 to A5 in FIGS. 3 and 4 are addresses and timings inputted from outside, and D1 to A5.
D5 is the input / output timing of data corresponding to A1 to A5.

Next, the operation of this embodiment will be described with reference to these timing charts. For convenience of explanation, the time when the a-system precharge operation is performed is referred to as a1 phase, a
The data input / output operation with the memory cell MC15 is performed by the system, the a2 phase is performed, the system precharge operation is performed by the b1 phase, and the data input / output operation with the memory cell MC15 is performed by the system b. Time is b2
Called a phase.

First, the read operation will be described in detail with reference to FIG. When the address changes ((b) in FIG. 3), the phase becomes the a1 phase, the a-system precharge control signal 33 is set to a high level ((d) in FIG. 3), and the a-system LOADa13 performs a precharge operation. The a-system row address latch control signal 25 and the a-system column address latch control signal 29 are set to a high level ((f) in FIG. 3), and the a-system row address latch 2 and the a-system column address latch 7 perform a write operation (FIG. 3). 3 (h)).

In response to the a-system row address decoder control signal 26, the a-system row address decoder Xa-DEC3 is in a non-selected state. a system column address decoder control signal 3
0 causes the a-system column address decoder Ya-DEC8 to
The state becomes the all-selected state, and precharging of the system a is started.

When the precharging of the a-system bit line is completed, the phase becomes the a2 phase and the control circuit T-CTRL
The following operation is performed by the control of No. 4. The a-system precharge signal 33 is set to a low level state ((d) in FIG. 3).
The precharge operation of the system LOADa13 is stopped. a
The system sense amplifier control signal 35 is set to a high level (see FIG.
Middle (l)), the a-system sense amplifier 18 is activated.

A system row address latch control signal 25, a
The system column address latch control signal 29 is set to low level ((f) in FIG. 3), and the a system row address latch 2 and the a system column address latch 7 hold the input addresses ((h) in FIG. 3).

A system row address decoder control signal 26,
The a-system column address decoder control signal 30 is enabled ((j) in FIG. 3), and the a-system row address decoder X
a-DEC3, a-system column address decoder Ya-DEC
8 is an a-system word line 44 corresponding to each input address.
, And one of the a-system column selection lines 46 is driven to the selection level. The above operation selects only the memory cell MC15 and activates the activated a-system sense amplifier 1.
8 to be amplified. At this time, the data output multiplexer 22 outputs the data amplified by the a-system sense amplifier 18 to the outside according to the data output multiplexer control signal 39 ((c) in FIG. 3).

When the address changes after the completion of the a1 phase, the b1 phase is entered, the b-system precharge control signal 34 is set to a high level ((e) in FIG. 3), and the b-system LOA is set.
Db14 performs a precharge operation. The b-system row address latch control signal 27 and the b-system column address latch control signal 31 are set to high level ((g) in FIG. 3), and the b-system row address latch 5 and the b-system column address latch 10 perform a write operation (FIG. 3). 3 (i)).

In response to the b-system row address decoder control signal 28, the b-system row address decoder Xb-DEC6 is in a non-selected state. b-system column address decoder control signal 3
2, the b-system column address decoder Yb-DEC 9
The state becomes the all-selected state, and the precharging of the b-system is started.

After the completion of the precharging of the b-system, the phase becomes the b2 phase, and the following operation is performed under the control of the control circuit T-CTRL4. The b-system precharge signal 34 is set to low level ((e) in FIG. 3), and the b-system LOADb14
Stops the pre-charge operation of. The b-system sense amplifier control signal 37 is set to a high level ((m) in FIG. 3), and the b-system sense amplifier 19 is activated. The b-system row address latch control signal 27 and the b-system column address latch control signal 31 are set to low level ((g) in FIG. 3), and the b-system row address latch 5 and the b-system column address latch 10 hold the input addresses. ((I) in FIG. 3).

The b-system row address decoder control signal 28,
According to the b-system column address decoder control signal 32 ((j) in FIG. 3), the b-system row address decoder Xb-DEC6
The b-system column address decoder Yb-DEC9 includes one of the b-system word lines 54 corresponding to the input address,
One of the b-system column selection lines 47 is driven to the selection level. As a result, only one memory cell MC15 is selected and amplified by the activated b-system sense amplifier 19.

At this time, the data output multiplexer 22 outputs the data amplified by the b-system sense amplifier 19 to the outside according to the data output multiplexer control signal 39 ((c) in FIG. 3). When the address changes after the completion of the b1 phase, the operation shifts to the a1 phase again, and thereafter, this operation is repeated to read data externally.

Although the data reading has been described above, the writing can be dealt with by performing the same operation, and will be described with reference to FIG. According to various control signals output from the T-CTRL 4 in response to an external address input, one of the write memory cell MC and one of the complementary write bit lines is selected. In the a2 phase, instead of the a-system sense amplifier 18 at the time of reading, a The system write control signal 36 is set to a high level ((l) in FIG. 4), and a system write amplifier WAM
The P-a 20 is activated, and data input from the input buffer I-buf 24 is written to the memory cell MC15 ((c) in FIG. 4).

In the b2 phase, the b-system write control signal 3 is used instead of the b-system sense amplifier 19 at the time of reading.
8 is set to the high level ((m) in FIG. 4), the b-system write amplifier WAMP-b20 is activated, and the input buffer Ib
The data input from uf24 is written into memory cell MC15 ((c) in FIG. 4).

The operation of the a1 phase and the b1 phase is started by a change in the address, and the phase shifts from the a1 phase to the a2 phase and from the b1 phase to the b2 phase after a precharge time. Further, since the a2 phase and the b2 phase respectively hold addresses internally, the input address can be changed in the a2 phase and the b2 phase.

Further, since there is no change in timing or the like between the write operation and the read operation, the same access can be performed not only when the read / write operation is continuous but also when the read / write order is random.

FIG. 5 is a block diagram of a second embodiment of the present invention, and the same parts as those of FIG. 1 are denoted by the same reference numerals. In this embodiment, the row address latches 2 and 5, the column address latches 7 and 10 and their control mechanism 2 are different from the first embodiment of FIG.
5, 27, 29 and 31 are excluded.

The data input terminal of the a-system row address decoder 3 is connected to the common row address bus 52, the data input terminal of the b-system row address decoder 6 is connected to the common row address bus 52, and the a-system column address decoder. 8 is connected to a common column address bus 58, the data input terminal of the b-system column address decoder 9 is connected to a common column address bus 58, and the control circuit T-CTRL4 controls various internal control signals 26, 28, 30
To 39 are output. The configuration other than the above is the same as the configuration shown in the first embodiment.

The operation of the second embodiment is based on the system a and the system b.
At the time of non-access to each of the systems, the bit line precharge signals 33 and 34 are always set to the high level, and the column address decoder Ya and the column address decoder control signals 30 and 32 are used.
-DEC8 and Yb-DEC9 are all selected and precharged.

In the a2 phase operation of the first embodiment, an externally input address is directly decoded by the a system column address decoders 3 and 8 ((g) in FIGS. 6 and 7).
((F) in FIGS. 6 and 7), an externally input address in the b2 phase operation is directly decoded by the b-system column address decoders 6 and 9 ((g) in FIGS. 6 and 7). The operation can access the memory cell at the address input in each phase by performing the same operation as the operation shown in the first embodiment. At this time, the a1, b2, and b1 phases have the same period as the a2 phase.

FIG. 6 is a timing chart at the time of reading in the second embodiment, and FIG. 7 is a timing chart at the time of writing.

Addresses A1 to A5 in FIGS. 6 and 7 are addresses and timings input from the outside,
D5 is the input / output timing of data corresponding to A1 to A5.

Although the case where the precharge time is shorter than the memory cell access time has been described above, when the precharge time is longer than the memory cell access time, the precharge time Tp and the memory access time Ta are used.
By connecting n + 1 sets of word lines and bit lines satisfying Ta × n> Tp to each memory cell, and sequentially accessing each set, it is possible to access the memory only with the read time.

[0066]

As described above, according to the present invention, 1
One memory cell has a plurality of write and data read paths, and operates by overlapping the precharge period with the other data read or data write period. There is an effect that high-speed operation can be performed only by a memory cell read time or a memory cell write time.

[Brief description of the drawings]

FIG. 1 is a configuration block diagram of an SRAM according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a memory cell in the SRAM used in the embodiment of the present invention.

FIG. 3 is a timing chart at the time of data reading in the SRAM according to the first embodiment of the present invention.

FIG. 4 is a timing chart at the time of data writing in the SRAM according to the first embodiment of the present invention.

FIG. 5 is a configuration block diagram of a RAM according to a second embodiment of the present invention.

FIG. 6 is a timing chart when data is read from a RAM according to a second embodiment of the present invention.

FIG. 7 is a timing chart at the time of data writing in a RAM according to a second embodiment of the present invention.

[Explanation of symbols]

 1 row address buffer 2 a system row address latch 3 a system row address decoder 4 control circuit 5 b system row address latch 6 b system row address decoder 7 a system column address latch 8 a system column address decoder 9 b system column address decoder 10 b system column address latch 11 control signal buffer 12 column address buffer 13 a system precharge circuit 14 b system precharge circuit 15 memory cell 16 a system line selection switch 17 b system line selection switch 18 a system sense amplifier 19 b system sense amplifier Reference Signs List 20 a system write amplifier 21 b system write amplifier 22 data output multiplexer 23 data output buffer 24 data input buffer 40, 41 a system complementary bit line 42, 43 b system complementary bit line 44 a system word line 5 b system word line 46 a system column selection line 46 b system column selection line 48, 49 a system complementary common bit line 50, 51 b system complementary common bit line 52 common row address 53 a system row address line 54 b system row address Line 55 a system column address line 56 b system column address line 57 external control signal 58 common column address bus 59 to 63 data line 64, 65 a system cell selection terminal 66, 67 b system cell selection terminal 68, 69 a system cell data Input / output terminal 70, 71 b-system cell data input / output terminal 72, 73 Inverter 74-77 Transfer gate

Claims (6)

[Claims] 1. A memory cell each having a plurality of systems of data input / output ports, and provided corresponding to each system of the data input / output ports of the memory cell, respectively connected to the corresponding system data input / output ports. A plurality of data input / output bit lines, a plurality of selection word lines provided corresponding to the respective data input / output bit lines, and a plurality of data input / output bit lines. A precharge means for performing precharge control independently of each other, and a corresponding one of the plurality of word lines and the plurality of data input / output bit lines when inputting / outputting data to / from the memory cell. Selecting means for selecting a set of systems, and data input / output using a set of word lines and data input / output bit lines selected by the selecting means. The semiconductor memory device characterized by comprising means for controlling so as to form a pre-charge of the other systems of data input bit line of the non-selected, the. 2. A memory cell each having first and second data input / output ports, and a data input / output port of a corresponding system provided corresponding to each of the data input / output ports of the memory cell. And a first and second system data input / output bit lines respectively connected to the first and second system data input / output bit lines, and a first and second system selection line provided corresponding to the first and second system data input / output bit lines, respectively. A word line; a precharge means for performing precharge control independently on each of the first and second data input / output bit lines; and a first data input / output by the precharge means During the precharge period for the bit line, a control is performed to select a pair of the second system selection word line and the corresponding second system data input / output bit line to perform data input / output. The semiconductor memory device which comprises a means. 3. The controller according to claim 1, wherein the controller is configured to control the first system select word line and the first system data corresponding to the first system select word line during precharge of the second system data input / output bit line by the precharge unit. 3. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured to select a pair with an input / output bit line and control input / output of data. 4. The apparatus according to claim 1, wherein said selecting means includes means for selectively supplying an address decode signal to one of a set of said word line and said bit line.
4. The semiconductor memory device according to any one of claims 1 to 3. 5. The apparatus according to claim 1, wherein said selecting means includes means for selectively providing a data input / output path to one of a set of said word line and said bit line.
The semiconductor memory device according to any one of the above. 6. The semiconductor memory device according to claim 1, wherein each cell of said memory cell group is a random-accessible static memory cell.