JPS6030225A - High frequency circuit of television tuner - Google Patents

High frequency circuit of television tuner

Info

Publication number
JPS6030225A
JPS6030225A JP13815983A JP13815983A JPS6030225A JP S6030225 A JPS6030225 A JP S6030225A JP 13815983 A JP13815983 A JP 13815983A JP 13815983 A JP13815983 A JP 13815983A JP S6030225 A JPS6030225 A JP S6030225A
Authority
JP
Japan
Prior art keywords
frequency
circuit
high frequency
input terminal
capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13815983A
Other languages
Japanese (ja)
Other versions
JPH0457135B2 (en
Inventor
Toshio Kato
敏夫 加藤
Koichi Matsuda
浩一 松田
Kazuhiko Maejima
前嶋 和彦
Akira Sato
彰 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP13815983A priority Critical patent/JPS6030225A/en
Publication of JPS6030225A publication Critical patent/JPS6030225A/en
Publication of JPH0457135B2 publication Critical patent/JPH0457135B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03JTUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J3/00Continuous tuning
    • H03J3/02Details
    • H03J3/16Tuning without displacement of reactive element, e.g. by varying permeability
    • H03J3/18Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
    • H03J3/185Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes

Abstract

PURPOSE:To obtain an excellent standing wave ratio over a wide band through simple circuit constitution by providing an input resistance which is much larger than the input terminal at an input terminal for a high frequency signal and decreases gradually according to an increase in frequency. CONSTITUTION:When a desired reception frequency is as high as the upper-limit frequency of the reception frequency band of the high frequency circuit, the capacity CV of a variable capacitor is much smaller than the capacity C1 of a capacitor C1, which is ignored. Then when the desired reception frequency is equal to the lower-limit frequency of the reception frequency band, the capacity CV increases almost to the capacity C1. In this case, the input impedance of an MOSFETQ becomes about {C1/(C1+C4)} times at a point P by the capacity division of the capacitors C1 and C4 and is sufficiently low. For the purpose, an impedance matching frequency f0 is set to the upper-limit frequency fH of the reception frequency band fL-fH to obtain the excellent standing wave ratio between fL and fH.

Description

【発明の詳細な説明】 産業上の利用分野 本発明はテレビチューナの高周波回路に関する。[Detailed description of the invention] Industrial applications The present invention relates to a high frequency circuit for a television tuner.

背景技術とその問題点 先ず第1図を参照して従来のテレビチューナの高周波回
路について説明する。tは高周波信号の供給される入力
端子(アンテナ端子)である。入力端子tが第1のコイ
ルL、−直流阻止用コンデンザC2を通じてダブルダー
ト型MO8電界効果トランジスタQの一方のゲートに接
続される。コイルL1及びコンデンサC2の接続中点は
第2のコイルL2を通じて接地される。更に、コイルL
2には、可変容量コンデンサ(可変客月ダイオード)C
v及び固定コンデンサC1の直列回路が並列に接続され
る。コイルL1及びコンデンサC2の接続中点は抵抗器
Rcを通じて、可変容量コンデンサCvに供給される容
量制御用直流電圧の供給される入力端子T1に接続され
る。尚、MOS電界効果トランジスタツタ他方のダート
はAGC信号入力端子T2に接続される。
BACKGROUND ART AND PROBLEMS First, the high frequency circuit of a conventional television tuner will be explained with reference to FIG. t is an input terminal (antenna terminal) to which a high frequency signal is supplied. An input terminal t is connected to one gate of a double dart type MO8 field effect transistor Q through a first coil L and a DC blocking capacitor C2. The midpoint of the connection between the coil L1 and the capacitor C2 is grounded through the second coil L2. Furthermore, coil L
2 is a variable capacitor (variable capacitor diode) C
A series circuit of V and a fixed capacitor C1 are connected in parallel. A midpoint of the connection between the coil L1 and the capacitor C2 is connected through a resistor Rc to an input terminal T1 to which a capacitance control DC voltage is supplied to the variable capacitor Cv. Note that the other dart of the MOS field effect transistor is connected to the AGC signal input terminal T2.

尚、第1及び第2のコイルL1 、L2のインダクタン
スを同じ符号り、 、L2にて表わし、コンデンサCv
Incidentally, the inductances of the first and second coils L1 and L2 are represented by the same symbols, , L2, and the capacitor Cv
.

C1の容量も同じ符号Cv、自にて表わすものとする。The capacity of C1 is also expressed by the same symbol Cv.

しかして、斯る高周波回路は、入力端子tの図において
左側を見たインピーダンス(抵抗) RO及びMO8電
界効果トランジスタQの入力インピーダンスZ1間の整
合をとるための整合回路と、入力同調回路とを兼ねてい
るものである。入力端子tの右側を見たインピーダンス
(抵抗)をRにとする。
Therefore, such a high-frequency circuit includes an impedance (resistance) of the input terminal t when looking to the left in the diagram, a matching circuit for matching between the input impedance Z1 of the MO8 field effect transistor Q, and an input tuning circuit. It also serves as Let R be the impedance (resistance) when looking at the right side of the input terminal t.

次にこの第1図の高周波回路の等価回路を第2図に示し
、これについて説明する。この等価回路では、MO8f
fi界効果トランジスタQの入ツタンピーダンスZ1を
、入力抵抗Ri及び入力零#ctの並列回路で表わして
いる。又、上述の可変容量コンデンサCv及び固定コン
デンサC1の直列容量を、容量Cx及びC3の並列容量
で表わしている。
Next, an equivalent circuit of the high frequency circuit shown in FIG. 1 is shown in FIG. 2, and will be explained. In this equivalent circuit, MO8f
The input tempedance Z1 of the fi field effect transistor Q is represented by a parallel circuit of an input resistance Ri and an input zero #ct. Further, the series capacitance of the variable capacitor Cv and fixed capacitor C1 described above is represented by the parallel capacitance of capacitances Cx and C3.

そして、とのド)周波回路を入力端子を側の回路に1、
MO8電界効果トランジスタQ側の回路に2とに分けて
考え、回路に1及びに2をまとめて回路にとする。尚、
容fjl、’ CXIC3IC1を有するコンデンサを
同じ符号Cz v C5C1にて表わし、抵抗Riを有
する抵抗器を同じ符号R1にて表わすものとする。即ち
、回路に1はコイルL1及びコンデンサcxからなるイ
ンピーダンス弊合口路となシ、回路に2は主としてコイ
ルL2、コンデンサC5,Ci及び抵抗器Riの並列回
路からなシ、回路に1と協同して入力同調回路Kを構成
することになる。
Then, connect the input terminal of the frequency circuit to the side circuit 1,
The circuit on the Q side of the MO8 field effect transistor will be considered separately, and the circuit 1 and 2 will be combined into a circuit. still,
A capacitor having a capacitance fjl,' CXIC3IC1 shall be designated by the same symbol Cz v C5C1, and a resistor having a resistance Ri shall be designated by the same symbol R1. That is, in the circuit 1, there is an impedance path consisting of the coil L1 and the capacitor cx, and in the circuit 2, there is mainly a parallel circuit of the coil L2, the capacitors C5, Ci, and the resistor Ri, which cooperates with the impedance circuit 1. The input tuning circuit K is constructed by the following.

第3図に整合回路に1を抜き出して示し、これについて
説明するに、入力端子tの左側と接地との間に抵抗R8
が接続され、入力端子tの右側に整合回路に1が接続さ
れ、出力端子t′と接地との間に抵抗器R2が接続され
る。この場合、整合回路に1はR8< R2の条件の下
でしか機能しない。又、入力端子tの右側を見たインピ
ーダンスGは第4図に示すごとき周波数特性を有し、周
波数fが0の時抵抗値R2を呈し、周波数fがf。の時
それに対応した抵抗値R8を呈する。即ち、この整合回
路に1の整合状態は、特定の周波数f。の時のみとなる
。そして、この周波数f。を可変するには、インダクタ
ンスL1及び容量C工を同時に変化させる必要があるが
、通常はインダクタンスL1を固定として使用される場
合が殆どである。従って、第2図においてもR8=Rt
となる周波数f。の設定列?インドが問題となる。
1 is extracted from the matching circuit in FIG. 3. To explain this, a resistor R8 is connected between the left side of the input terminal t and the ground.
1 is connected to the matching circuit on the right side of the input terminal t, and a resistor R2 is connected between the output terminal t' and ground. In this case, 1 in the matching circuit only functions under the condition of R8<R2. Further, the impedance G when looking at the right side of the input terminal t has a frequency characteristic as shown in FIG. 4, and exhibits a resistance value R2 when the frequency f is 0, and when the frequency f is f. When , a corresponding resistance value R8 is exhibited. That is, a matching state of 1 in this matching circuit corresponds to a specific frequency f. Only when. And this frequency f. In order to vary the inductance L1 and the capacitance C, it is necessary to change the inductance L1 and the capacitance C at the same time, but in most cases, the inductance L1 is usually fixed. Therefore, also in FIG. 2, R8=Rt
The frequency f. Setting column? India is the problem.

第5図は第1図の高周波回路に於ける周波数f。FIG. 5 shows the frequency f in the high frequency circuit of FIG.

の設定例を示しだもので、R1はMOS 電界効果トラ
ンジスタQの入力抵抗R4の周波数特性曲線を示し、こ
れはインピーダンス(抵抗)尻より充分大きく、しかも
周波数の増大に従ってその値が漸次低下する特性を呈し
ている。インピーダンス(抵抗)R,’の周波数特性は
、インダクタンスL1が小さいときB: rltt 線
R≦1の如く在り、インダクタンスし1が大きいときは
曲線R:、2の如くなる。曲想Rに1は受信周波数帯域
f!、〜fyの上限周波数fnにおいてインピーダンス
(抵抗) R4がR8に等しくなるようにした場合であ
り、曲aRo2は受信周波数帯域f■、〜fnの適当な
中間値fMにおいてインピーダンス(抵抗)R工がR6
にちしくなるようにした場合である。しかして、曲線n
:1の場合は、上限周波数fn近傍における定在波比が
良好となるが、下限周波数fL付近では定在波比がかな
シ悲くなる。曲線R8′2の場合は、中間の周波数fM
において定在波比が良好と々るが、下限及び上限周波数
fL、f■での定在波比は悪くなる。この様に、定在波
比が悪くなると、その近傍の′ri+、力利得が低下し
、雑音指数が態化することにができる。
This shows an example of the setting, where R1 indicates the frequency characteristic curve of the input resistance R4 of the MOS field effect transistor Q, which is sufficiently larger than the impedance (resistance) end, and whose value gradually decreases as the frequency increases. It shows. The frequency characteristic of the impedance (resistance) R,' is as shown in the curve R:,2 when the inductance L1 is small, and as shown in the curve R:,2 when the inductance L1 is large. 1 in Kyokuso R is the reception frequency band f! , ~fy, the impedance (resistance) R4 is made equal to R8 at the upper limit frequency fn of ~fy, and the song aRo2 is the case where the impedance (resistance) R is made equal to the reception frequency band f■, ~fn at an appropriate intermediate value fM. R6
This is a case where it is made to look like a day. However, the curve n
:1, the standing wave ratio near the upper limit frequency fn is good, but the standing wave ratio becomes poor near the lower limit frequency fL. In the case of curve R8'2, the intermediate frequency fM
Although the standing wave ratio is good at the lower limit and upper limit frequencies fL and f■, the standing wave ratio becomes poor. In this manner, when the standing wave ratio deteriorates, the 'ri+ and power gain in the vicinity thereof decrease, and the noise figure becomes materialized.

発明の目的 上述の点に鑑み、本発明は回路打・!成簡η1にして、
広帯域に亘って整合をとることのできるテレビチューナ
の高周波回路を提案しようとするものである。
Purpose of the Invention In view of the above-mentioned points, the present invention provides a circuit decoder! Set it to simple η1,
This paper attempts to propose a high frequency circuit for a television tuner that can perform matching over a wide band.

発明の概要 本発明によるテレビチューナの高周波回路は、高周波信
号入力端子の入力抵抗よシ十分大で、周波数の増大に従
って漸次減少する入力抵抗を有する半導体能動素子と、
第1及び第2のインダクタンス素子と、固定及び可変容
量才子とを有し、第1のインダクタンス素子の一端が高
周波信号入力端子に接続されると共に、他端が可変容量
才子を通じて接地され、固定容量素子の一端が第1のイ
ンダクタンス素子及び可変容量才子の接続中点に接続さ
れると共に、他端が第2のインダクタンス素子を通じて
接地され、固定容量素子及び第2のインダクタンス素子
の接続中点が半導体能動零子の入力電極に接続されて成
るものである。
Summary of the Invention A high frequency circuit for a television tuner according to the present invention includes a semiconductor active element having an input resistance that is sufficiently larger than an input resistance of a high frequency signal input terminal and that gradually decreases as the frequency increases;
It has first and second inductance elements and fixed and variable capacitance elements, one end of the first inductance element is connected to the high frequency signal input terminal, the other end is grounded through the variable capacitance element, and the fixed capacitance element is connected to the high frequency signal input terminal. One end of the element is connected to the connection midpoint between the first inductance element and the variable capacitance element, the other end is grounded through the second inductance element, and the connection midpoint between the fixed capacitance element and the second inductance element is connected to the semiconductor. It is connected to the input electrode of an active zero.

斯る本発明によれば、回路構成簡単にして広帯域に亘っ
て整合をとることのできるテレビチューナの高周波回路
を得ることができる。
According to the present invention, it is possible to obtain a high frequency circuit for a television tuner that has a simple circuit configuration and can perform matching over a wide band.

実施例 以下に第6図を参照して、本発明の一実施例を説明する
も、第6図において第1図と対応する部分には同一符号
を伺して説明する。入力端子tを第1のコイルL1−コ
ンデンサC1−コンデンザC2ヲ順次に通じてダブシダ
ー1MO8電界効果トランジスタQの一方のダートに接
続する。コイルL1及びコンデンサC1の接続中点を可
変容量コンデンサ(可変容週ダイオード)Cvのカソー
ドに接続し、そのアノードを接地する。コイルL1及び
コンデンサC1の接続中点を、抵抗器Rcを通じて可変
容量コンデン九Cvに対する容量制御用直流電圧の供給
される入力端子T1に接続する。更に、コンデンサC1
pC2の接続中点を第2のコイルL2を通じて接地する
Embodiment An embodiment of the present invention will be described below with reference to FIG. 6. In FIG. 6, parts corresponding to those in FIG. 1 are designated by the same reference numerals. The input terminal t is connected to one dart of the Dubcedar 1MO8 field effect transistor Q through the first coil L1, capacitor C1, and capacitor C2 in this order. The midpoint of the connection between the coil L1 and the capacitor C1 is connected to the cathode of a variable capacitor (variable capacitor diode) Cv, and its anode is grounded. The midpoint of the connection between the coil L1 and the capacitor C1 is connected to an input terminal T1 to which a DC voltage for capacitance control is supplied to the variable capacitance capacitor 9Cv through a resistor Rc. Furthermore, capacitor C1
The connection midpoint of pC2 is grounded through the second coil L2.

トランジスタQの他方のダートはAGC信号入力端子T
2に接続される。
The other dart of transistor Q is the AGC signal input terminal T.
Connected to 2.

この第6図の高周波回路において、希望受信周波数がこ
の高周波回路の受信周波数帯域の上限周波数と等しいと
すると、容量Cvは容量C1より充分小さくなり、コン
デンサC1及びCvによる容量分割は殆ど行なわれず、
コンデンサC1を無視することができる。
In the high frequency circuit shown in FIG. 6, if the desired reception frequency is equal to the upper limit frequency of the reception frequency band of this high frequency circuit, the capacitance Cv will be sufficiently smaller than the capacitance C1, and there will be almost no capacitance division by the capacitors C1 and Cv.
Capacitor C1 can be ignored.

次に希望受信周波数が受信周波数帯域の下限周波数に等
しいとすると、容量Cvは大きく外り1容量CvはC1
に略等しく力る。この場合には、第7図の等価回路に示
す様に、コンデンサC1及びC4の容量分割により、M
O8電界効果トランジスタQの入倍と女り、第1図の従
来の高周波回路に比較して、入力インピーダンス(抵抗
)弓が充分低くなる。
Next, if the desired receiving frequency is equal to the lower limit frequency of the receiving frequency band, the capacitance Cv will deviate greatly and 1 capacitance Cv is C1
force approximately equal to . In this case, as shown in the equivalent circuit of FIG. 7, by dividing the capacitors C1 and C4, M
The input impedance (resistance) of the O8 field effect transistor Q is sufficiently low compared to the conventional high frequency circuit shown in FIG.

尚、容量C4のコンデンサを同じ符号C4で示し、容i
c4はc4=cv−cXの関係にある。
Incidentally, a capacitor with a capacitance of C4 is indicated by the same symbol C4, and a capacitor with a capacitance of i
c4 has the relationship c4=cv-cX.

従って第6図の高周波回路のインピーダンス整合周波数
f。を、第8図に示すごとく受信周波数帯域ft、−f
mの上限周波数fHに等しく選べば、受信周波数帯域f
L−fmに亘たシ良好な定在波比を得ることができる。
Therefore, the impedance matching frequency f of the high frequency circuit of FIG. As shown in FIG. 8, the reception frequency band ft, -f
If selected equal to the upper limit frequency fH of m, the receiving frequency band f
A good standing wave ratio over L-fm can be obtained.

第8図において曲線Ro1は第5図の曲fPARotに
対応し、曲BRssが本発明による・入力端子t。の右
側を見たインピーダンス(抵抗)R9の周波数/i¥性
を示し、周波数の増大に従って漸次その値が低下するが
、その勾配は極く緩かであって、その変化量は少ない。
In FIG. 8, the curve Ro1 corresponds to the song fPARot in FIG. 5, and the song BRss is the input terminal t according to the present invention. The figure shows the frequency/i characteristic of impedance (resistance) R9 when looking at the right side of , and the value gradually decreases as the frequency increases, but the slope is extremely gentle and the amount of change is small.

従って、インピーダンス整合は周波数f、を受信周波数
帯域fL−fnの上限周波数fnに選べば、受信周波数
f L = 7gに亘シ良好な定在波比を得ることがで
き、その結果電力利得が大となシ、雑音指数も良好とな
る。
Therefore, for impedance matching, if the frequency f is selected as the upper limit frequency fn of the reception frequency band fL-fn, a good standing wave ratio can be obtained over the reception frequency fL = 7g, and as a result, the power gain is large. In addition, the noise figure is also good.

尚、第9図に示す如く、高周波回路の入力側にフィルタ
Fを挿入することも可能であって、この場合にはフィル
タFの出力インピーダンスがR8となるものである。
Incidentally, as shown in FIG. 9, it is also possible to insert a filter F on the input side of the high frequency circuit, and in this case, the output impedance of the filter F becomes R8.

発明の効果 上述せる本発明によれば、回路構成簡単にして広帯域に
亘って整合をとることのできるテレビチューナの高周波
回路を得ることができる。
Effects of the Invention According to the present invention described above, it is possible to obtain a high frequency circuit for a television tuner that has a simple circuit configuration and can perform matching over a wide band.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のテレビチューナの高周波回路を示す回路
図、第2図は第1図の高周波回路の等価回路を示す回路
図、第3図は第2図の一部の回路を示す回路図、第4図
及び第5図は入力抵抗の周波特性を示す曲線図、第6図
は本発明によるテレビチューナの高周波回路の一実施例
を示す回路図、第7図は第6図の高周波回路の等価回路
を示す回路図、第8図は入力抵抗の周波数特性を示す曲
線図、第9図は本発明の他の実施例を示す回路図である
。 L 1 + L 2は第1及び第2のインダクタ(コイ
ル)、C1ハ固定コンデンサ、Cvは可変容量コンデン
サ、Qは半導体能動素子としてのダブルヶ”−トMO8
電界効果トランジスタである。
Figure 1 is a circuit diagram showing the high frequency circuit of a conventional television tuner, Figure 2 is a circuit diagram showing an equivalent circuit of the high frequency circuit in Figure 1, and Figure 3 is a circuit diagram showing part of the circuit in Figure 2. , FIG. 4 and FIG. 5 are curve diagrams showing the frequency characteristics of the input resistance, FIG. 6 is a circuit diagram showing an embodiment of the high frequency circuit of the television tuner according to the present invention, and FIG. 7 is the high frequency circuit of FIG. 6. FIG. 8 is a curve diagram showing the frequency characteristics of the input resistance, and FIG. 9 is a circuit diagram showing another embodiment of the present invention. L 1 + L 2 are the first and second inductors (coils), C1 is a fixed capacitor, Cv is a variable capacitor, and Q is a double-type MO8 as a semiconductor active element.
It is a field effect transistor.

Claims (1)

【特許請求の範囲】[Claims] 高周波信号入力端子の入力抵抗よシ十分大で、周波数の
増大に従って漸次減少する入力抵抗を有する半導体能動
素子と、第1及び第2のインダクタンス素子と、固定及
び可変容量素子とを有し、上記第1のインダクタンス素
子の一端が上記高周波信号入力端子に接続されると共に
、他端が上記可変容量素子を通じて接地され、上記固定
容量素子の一端が上記第1のインダクタンス素子及び上
記可変容量素子の接続中点に接続されると共に、他端が
第2のインダクタンス素子を通じて接地され、上記固定
容量素子及び上記第2のインダクタンス素子の接続中点
が上記半導体能動素子の入力電極に接続されて成ること
を特徴とするテレビチューナの高周波回路。
a semiconductor active element having an input resistance that is sufficiently larger than the input resistance of the high frequency signal input terminal and gradually decreases as the frequency increases, first and second inductance elements, and fixed and variable capacitance elements; One end of the first inductance element is connected to the high frequency signal input terminal, the other end is grounded through the variable capacitance element, and one end of the fixed capacitance element is connected to the first inductance element and the variable capacitance element. and the other end is grounded through a second inductance element, and the connection midpoint of the fixed capacitance element and the second inductance element is connected to the input electrode of the semiconductor active element. The high frequency circuit of the TV tuner is a feature.
JP13815983A 1983-07-28 1983-07-28 High frequency circuit of television tuner Granted JPS6030225A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13815983A JPS6030225A (en) 1983-07-28 1983-07-28 High frequency circuit of television tuner

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13815983A JPS6030225A (en) 1983-07-28 1983-07-28 High frequency circuit of television tuner

Publications (2)

Publication Number Publication Date
JPS6030225A true JPS6030225A (en) 1985-02-15
JPH0457135B2 JPH0457135B2 (en) 1992-09-10

Family

ID=15215396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13815983A Granted JPS6030225A (en) 1983-07-28 1983-07-28 High frequency circuit of television tuner

Country Status (1)

Country Link
JP (1) JPS6030225A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS641337A (en) * 1987-04-01 1989-01-05 Iss Eng Inc Signal receiver
US5759161A (en) * 1994-03-31 1998-06-02 Kaneka Medix Corporation Medical wire and method for leaving implanted devices
US9622754B2 (en) 1998-12-21 2017-04-18 DePuy Synthes Products, Inc. Intravascular device deployment mechanism incorporating mechanical detachment

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS641337A (en) * 1987-04-01 1989-01-05 Iss Eng Inc Signal receiver
US5759161A (en) * 1994-03-31 1998-06-02 Kaneka Medix Corporation Medical wire and method for leaving implanted devices
US9622754B2 (en) 1998-12-21 2017-04-18 DePuy Synthes Products, Inc. Intravascular device deployment mechanism incorporating mechanical detachment

Also Published As

Publication number Publication date
JPH0457135B2 (en) 1992-09-10

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