JP3422195B2 - Tuner circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

TECHNICAL FIELD The present invention relates to a tuner circuit,
In particular, the present invention relates to a wideband tuner circuit for improving the interference (U / V interference) of a signal of a target frequency by a signal of another frequency within the band of the high frequency amplifier circuit.

[0002]

2. Description of the Related Art In recent years, a wide band of tuners has become mainstream, and in order to cope with this, it is indispensable to widen a band of an input circuit of a tuner circuit and a high frequency amplifier circuit. For example, in the UHF band, the coverage is 470
From 330 MHz to 900 MHz (hereinafter, referred to as HIGH band), 330 MHz to 470 MHz (hereinafter, referred to as LOW band) is added to widen the band from 330 MHz to 900 MHz. However, since the gain of the high frequency amplifier circuit decreases in the LOW band only with the input tuning circuit, L
In order to compensate the gain in the OW band, a peaking circuit is added to tune the signal in the LOW band to compensate the gain.

FIG. 3 shows an example of the input circuit and the high-frequency amplifier circuit of a conventional tuner circuit. In FIG. 3, the input circuit and the high frequency amplifier circuit of the tuner circuit are the input tuning circuit 1, the peaking circuit 2, the high frequency amplifier circuit 3, the signal input terminal 4, the power supply terminal 5, the AGC terminal 6, the signal output terminal 7,
It consists of a tuning terminal 8. Of these, the input tuning circuit 1 is composed of coils L1 and L2, capacitors C1 and C2, an input tuning varicap D1, and a resistor R1. The peaking circuit 2 is composed of a coil L3, capacitors C3 and Cin, and a resistor R2.

In the input tuning circuit 1, the signal input terminal 4
Is connected to the gate G2 of the FET Q1 of the high frequency amplifier circuit 3 via the coil L1 and the capacitor C2. The connection between the coil L1 and the capacitor C2 is grounded via the coil L2, and is also connected to the anode of the input tuning varicap D1, and the cathode of the input tuning varicap D1 is grounded via the capacitor C1. ,
It is connected to the tuning terminal 8 via the resistor R1.

On the other hand, in the peaking circuit 2, one end of the coil L3 is the gate G of the FET Q1 of the high frequency amplifier circuit 3.
While being connected to 2, the other end is grounded via a resistor R2 and further grounded via a capacitor C3. Further, the gate G2 of the FET Q1 is a capacitor Cin
Grounded through. Here, the capacitor Cin is F
This is the input capacitance of the gate G2 of the ETQ1 and is also a part of the peaking circuit 2. A bias voltage is supplied from the power supply terminal 5 to the connection between the coil L3 and the resistor R2.

In the high frequency amplifier circuit 3, the power supply terminal 5 and the AGC terminal 6 are connected, and the output is connected to the signal output terminal 7. However, the details of the configuration of the high-frequency amplifier circuit 3 are irrelevant to the essence of the present invention, and the description thereof is omitted.

In the tuner circuit thus constructed, first, in order to explain the operation of the input tuning circuit 1,
Input tuning circuit 1 with peaking circuit 2 omitted from the input circuit
Think about the case only. Since the input tuning circuit 1 in this case is composed of the coils L1 and L2, the capacitors C1 and C2, and the input tuning varicap D1, the gain of the high frequency amplifier circuit 3 is applied from the tuning terminal 8 to the input tuning varicap D1. The frequency of the gain peak changes as shown in FIG. 4A. FIG. 4A shows the gains d1, d2, d3, d4 of the high frequency amplifier circuit 3 at four tuning frequencies from the LOW band to the HIGH band. Figure 4
As can be seen from (a), the gain of the high frequency amplification circuit 3 is L
The gain in the OW band is smaller than that in the HIGH band.

On the other hand, in order to explain the operation of the peaking circuit 2, when the input tuning circuit 1 is omitted from the input circuit and only the peaking circuit 2 is provided, the peaking circuit 2 is composed of a coil L3 and capacitors C3 and Cin. Since the frequency is a fixed tuning circuit, the gain p of the high frequency amplifier circuit 3
Has a fixed frequency peak at the lower limit of the LOW band as shown in FIG.

Therefore, in the tuner circuit shown in this conventional example, LOW is insufficient when only the input tuning circuit 1 is used.
In order to compensate the gain in the band, the peaking circuit 2 in which the tuning frequency is adjusted to the lower limit frequency of the LOW band is added to the input tuning circuit 1.

Gains s1, s2, s3, and s4 of the high-frequency amplifier circuit 3 at four tuning frequencies similar to those shown in FIG. 4A in the state where the peaking circuit 2 is added to the input tuning circuit 1.
Is shown in FIG. As described above, the gains s1, s2, s3, and s4 of the high-frequency amplifier circuit 3 are obtained by overlapping the gains d1 and p, d2 and p, d3 and p, and d4 and p when the two tuning circuits are used independently. It becomes a shape.

[0011]

However, in the above example, the higher the tuning frequency, the wider the band of the high frequency amplifier circuit. Further, it has a relatively high gain even at a frequency between the two gain peaks of the input tuning circuit and the peaking circuit. Therefore, for example, in addition to the signal of the target frequency, there are two signals in the low frequency band within the band of the high-frequency amplifier circuit, and the frequency of the sum of the frequencies of the two signals is close to the frequency of the target signal. In such a case, these signals may become interference waves with respect to the target signal (hereinafter referred to as U / V interference).

An object of the present invention is to solve the above problems and to provide a tuner circuit with less U / V interference.

[0013]

In order to achieve the above object, a tuner circuit of the present invention is a tuner circuit having at least an input circuit and a high frequency amplifier circuit, wherein the input circuit includes an input tuning varicap . Input tuning
Circuit and tuning frequency at which the gain of the input tuning circuit is insufficient
Equipped with a peaking circuit matching the tuning frequency
The King circuit has the same gain as the input tuning circuit.
Tuning frequency of the peaking circuit itself
A peaking frequency varying varicap for changing the number and reducing the gain is provided.

In the tuner circuit of the present invention, the voltage applied to the varicap for varying the peaking frequency is
It is characterized in that it is interlocked with a tuning voltage applied to the input tuning varicap.

[0015]

1 shows an embodiment of a tuner circuit of the present invention. In FIG. 1, parts that are the same as or equivalent to those of the conventional example in FIG. 3 are given the same symbols, and descriptions thereof are omitted. In FIG. 1, the input circuit of the tuner circuit and the high-frequency amplifier circuit are the input tuning circuit 1, the peaking circuit 10,
High frequency amplifier circuit 3, signal input terminal 4, power supply terminal 5, AG
It is composed of a C terminal 6, a signal output terminal 7, and a tuning terminal 8. Of these, the peaking circuit 10 is the coil L.
3, capacitor C3 and Cin, peaking frequency variable varicap D2, and resistors R2 and R3.

In the peaking circuit 10, the coil L3
One is connected to the gate G2 of the FET Q1 of the high-frequency amplifier circuit 3, the other is grounded via the resistor R2, and is further connected to the cathode of the peaking frequency varying varicap D2 via the capacitor C3. The anode of the varicap D2 for varying the peaking frequency is grounded. The cathode of the peaking frequency varying varicap D2 is connected to the tuning terminal 8 via the resistor R3. Further, the gate G2 of the FET Q1 is grounded via the capacitor Cin. Here, the capacitor Cin is an input capacitance of the gate G2 of the FET Q1 and is also a part of the peaking circuit 10.
A bias voltage is supplied from the power supply terminal 5 to the connection between the coil L3 and the resistor R2.

In the tuner circuit thus constructed, first, the operation of the input tuning circuit 1 will be described.
Consider a case where the peaking circuit 10 is omitted from the input circuit and only the input tuning circuit 1 is provided. The gain of the high frequency amplifier circuit 3 in this case changes according to the tuning voltage input from the tuning terminal 8 to the input tuning varicap D1, and the frequency of the gain peak changes as shown in FIG. This is the same as the gain shown in FIG. 4A of the conventional example, and shows the gains d5, d6, d7 and d8 of the high frequency amplifier circuit 3 at four tuning frequencies from the LOW band to the HIGH band.

On the other hand, in order to explain the operation of the peaking circuit 10, a case where the input tuning circuit 1 is omitted from the input circuit and only the peaking circuit 10 is considered will be considered. In this case, the peaking circuit 10 includes a coil L3, capacitors C3 and Cin, and a varicap D for varying the peaking frequency.
In the tuning circuit composed of 2, since the tuning voltage is supplied from the tuning terminal 8 to the peaking frequency varying varicap D2, the gain of the high frequency amplifier circuit 3 differs depending on the tuning frequency as in the input tuning circuit 1. , As shown in FIG. FIG. 2B shows the gains p5, p6, p7 and p8 of the high frequency amplifier circuit 3 at four tuning frequencies from the LOW band to the HIGH band. In the peaking circuit 10, since the condition of the resonance circuit is different from that of the input tuning circuit 1, the change in frequency with respect to the tuning voltage is different and the change in frequency is smaller than that in the input tuning circuit 1. Further, the Q value of the peaking circuit 10 changes depending on the capacity of the peaking frequency varying varicap D2, and the Q value deteriorates as the tuning voltage increases and the capacity of the peaking frequency varying varicap D2 decreases. Therefore, the gain of the high frequency amplifier circuit 3 in this case also decreases as the tuning voltage increases and the peaking frequency increases.

Then, the input circuit is constructed by adding the peaking circuit 10 to the input tuning circuit 1 as shown in FIG.
Gains s5, s6, s7, and s8 of the high-frequency amplifier circuit 3 at four tuning frequencies similar to (a) are shown in FIG. 2 (c). As can be seen from FIG. 2C, the gains s5, s6, s7, and s8 of the high-frequency amplifier circuit 3 are gains d5 and p5, d6 and p when the two tuning circuits are used independently.
6, d7 and p7, and d8 and p8 are overlapped, but unlike the characteristic of the gain of the high frequency amplifier circuit 3 in the conventional example shown in FIG. 4 (c), peaking occurs as the tuning frequency increases. Since the frequency is high and the peaking gain is low at the same time, the band of the high frequency amplifier circuit 3 is not so wide.

As described above, according to the tuner circuit of the present invention, when the tuning frequency is low, the peaking circuit 10 works effectively and a sufficient gain of the high frequency amplifier circuit 3 can be secured. Then, as the tuning frequency becomes higher, the peaking frequency of the peaking circuit 10 becomes higher in conjunction with it, and the gain of the high frequency amplification circuit 3 at the peaking frequency decreases, and the gain of the high frequency amplification circuit 3 at frequencies other than the tuning frequency is suppressed. be able to. As a result, when the tuning frequency is high, the U / V interference in which the low frequency signal interferes with the tuning frequency signal can be reduced.

In the embodiment of FIG. 1, the peaking frequency varying varicap D2 of the peaking circuit 10 is used.
The voltage applied to the input tuning circuit 1 is interlocked with the tuning voltage applied to the input tuning varicap D1 of the input tuning circuit 1, but should be changed as necessary so as not to have a gain at an unnecessary peaking frequency. If you can, you do not necessarily need to work together.

[0022]

According to the tuner circuit of the present invention, since the peaking frequency variable varicap is provided in the peaking circuit of the input circuit, the peaking circuit works effectively when the tuning frequency is low, and the gain of the high frequency amplifier circuit is gained. Can be secured. Further, when the tuning frequency is high, the peaking frequency is also high and the gain at the peaking frequency is low, so that U / V interference due to signals of frequencies other than the tuning frequency can be reduced.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a tuner circuit of the present invention.

2A and 2B are diagrams showing the gain of the high-frequency amplifier circuit in the embodiment of FIG. 1, in which FIG. 2A shows the gain when the input circuit is only the input tuning circuit, and FIG. 2B shows the gain when the input circuit is only the peaking circuit. Gain, (c) shows the gain when the input circuit includes both the input tuning circuit and the peaking circuit.

FIG. 3 is a circuit diagram showing an example of a conventional tuner circuit.

4A and 4B are diagrams showing the gain of the high-frequency amplifier circuit in the embodiment of FIG. 3, in which FIG. 4A shows the gain when the input circuit is only the input tuning circuit, and FIG. 4B shows the gain when the input circuit is only the peaking circuit. Gain, (c) shows the gain when the input circuit includes both the input tuning circuit and the peaking circuit.

[Explanation of symbols]

1 ... Input tuning circuit 3 ... High frequency amplifier circuit 4 ... Signal input terminal 5 ... Power supply terminal 6 ... AGC terminal 7 ... Signal output terminal 8 ... Tuning terminal 10 ... peaking circuit L1, L2, L3 ... Coil C1, C2, C3, Cin ... Capacitor D1 ... Varicap for input tuning D2 ... Varicap for variable peaking frequency R1, R2, R3 ... Resistance Q1 ... FET G2 ... G2

Claims (2)

(57) [Claims] 1. A having at least tuner circuit an input circuit and the high frequency amplifying circuit, the input circuit, the input having an input tuning varicap
Tuning circuit and tuning circuit where the gain of the input tuning circuit is insufficient
The peaking circuit has a tuning frequency matched to the wave number, and the peaking circuit has a high gain of the input tuning circuit.
At the same tuning frequency, the peaking circuit itself
A tuner circuit having a varicap for varying the peaking frequency for changing the tuning frequency and reducing the gain . 2. The voltage applied to the peaking frequency variable varicap is interlocked with the tuning voltage applied to the input tuning varicap.
The tuner circuit according to claim 1.