JPH0457135B2 - - Google Patents
Info
- Publication number
- JPH0457135B2 JPH0457135B2 JP13815983A JP13815983A JPH0457135B2 JP H0457135 B2 JPH0457135 B2 JP H0457135B2 JP 13815983 A JP13815983 A JP 13815983A JP 13815983 A JP13815983 A JP 13815983A JP H0457135 B2 JPH0457135 B2 JP H0457135B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- frequency
- high frequency
- capacitance
- inductance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000007423 decrease Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 239000003990 capacitor Substances 0.000 description 26
- 230000005669 field effect Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
- H03J3/00—Continuous tuning
- H03J3/02—Details
- H03J3/16—Tuning without displacement of reactive element, e.g. by varying permeability
- H03J3/18—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
- H03J3/185—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes
Description
【発明の詳細な説明】
産業上の利用分野
本発明はテレビチユーナの高周波回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a high frequency circuit for a television tuner.
背景技術とその問題点
先ず第１図を参照して従来のテレビチユーナの
高周波回路について説明する。ｔは高周波信号の
供給される入力端子（アンテナ端子）である。入
力端子ｔが第１のコイルL1−直流阻止用コンデ
ンサC2を通じてダブルゲート型MOS電界効果ト
ランジスタＱの一方のゲートに接続される。コイ
ルL1及びコンデンサC2の接続中点は第２のコイ
ルL2を通じて接地される。更に、コイルL2には、
可変容量コンデンサ（可変容量ダイオード）CV
及び固定コンデンサC1の直列回路が並列に接続
される。コイルL1及びコンデンサC2の接続中点
は抵抗器RCを通じて、可変容量コンデンサCVに
供給される容量制御用直流電圧の供給される入力
端子T1に接続される。尚、MOS電界効果トラン
ジスタＱの他方のゲートはAGC信号入力端子T2
に接続される。BACKGROUND ART AND PROBLEMS First, a high frequency circuit of a conventional television tuner will be described with reference to FIG. t is an input terminal (antenna terminal) to which a high frequency signal is supplied. An input terminal t is connected to one gate of a double-gate MOS field effect transistor Q through a first coil L 1 and a DC blocking capacitor C 2 . The midpoint of the connection between the coil L 1 and the capacitor C 2 is grounded through the second coil L 2 . Furthermore, in coil L 2 ,
Variable capacitor (variable capacitor diode) C V
and a series circuit of fixed capacitor C 1 are connected in parallel. The midpoint of the connection between the coil L 1 and the capacitor C 2 is connected through the resistor R C to the input terminal T 1 to which the capacitance control DC voltage is supplied to the variable capacitor C V . Note that the other gate of the MOS field effect transistor Q is the AGC signal input terminal T 2
connected to.
尚、第１及び第２のコイルL1，L2のインダク
タンスを同じ符号L1，L2にて表わし、コンデン
サCV，C1の容量も同じ符号CV，C1にて表わすも
のとする。 Note that the inductances of the first and second coils L 1 and L 2 are represented by the same symbols L 1 and L 2 , and the capacitances of the capacitors C V and C 1 are also represented by the same symbols C V and C 1 . .
しかして、斯る高周波回路は、入力端子ｔの図
において左側を見たインピーダンス（抵抗）RO
及びMOS電界効果トランジスタＱの入力インピ
ーダンスZi間の整合をとるための整合回路と、入
力同調回路とを兼ねているものである。入力端子
ｔの右側を見たインピーダンス（抵抗）R′Oとす
る。 Therefore, in such a high frequency circuit, the impedance (resistance) R O
It also serves as a matching circuit for matching the input impedance Z i of the MOS field effect transistor Q and an input tuning circuit. Let it be the impedance (resistance) R' O when looking at the right side of the input terminal t.
次にこの第１図の高周波回路の等価回路を第２
図に示し、これについて説明する。この等価回路
では、MOS電界効果トランジスタＱの入力イン
ピーダンスZiを、入力抵抗Ri及び入力容量Ciの並
列回路で表わしている。又、上述の可変容量コン
デンサCV及び固定コンデンサC1の直列容量を、
容量Cx及びC3の並列容量で表わしている。 Next, the equivalent circuit of the high frequency circuit in Figure 1 is shown in the second diagram.
It is shown in the figure and will be explained. In this equivalent circuit, the input impedance Z i of the MOS field effect transistor Q is represented by a parallel circuit of an input resistance R i and an input capacitance C i . Also, the series capacitance of the variable capacitor C V and fixed capacitor C 1 mentioned above is
It is expressed as a parallel capacitance of capacitance C x and C 3 .
そして、この高周波回路を入力端子ｔ側の回路
K1、MOS電界効果トランジスタＱ側の回路K2と
に分けて考え、回路K1及びK2をまとめて回路Ｋ
とする。尚、容量Cx，C3，Ciを有するコンデンサ
を同じ符号Cx，C3，Ciにて表わし、抵抗Riを有す
る抵抗器を同じ符号Riにて表わすものとする。即
ち、回路K1はコイルL1及びコンデンサCxからな
るインピーダンス整合回路となり、回路K2は主
としてコイルL2、コンデンサC3，Ci及び抵抗器Ri
の並列回路からなり、回路K1と協同して入力同
調回路Ｋを構成することになる。 Then, this high frequency circuit is connected to the circuit on the input terminal t side.
K 1 and circuit K 2 on the Q side of the MOS field effect transistor are considered separately, and circuits K 1 and K 2 are combined into circuit K.
shall be. Note that capacitors having capacitances C x , C 3 , and C i are represented by the same symbols C x , C 3 , and C i , and resistors having a resistance R i are represented by the same symbols R i . That is, circuit K 1 is an impedance matching circuit consisting of coil L 1 and capacitor C x , and circuit K 2 mainly consists of coil L 2 , capacitors C 3 and C i , and resistor R i
The input tuning circuit K is composed of parallel circuits, and cooperates with the circuit K1 .
第３図に整合回路K1を抜き出して示し、これ
について説明するに、入力端子ｔの左側と接地と
の間に抵抗ROが接続され、入力端子ｔの右側に
整合回路K1が接続され、出力端子t′と接地との間
に抵抗器R2が接続される。この場合、整合回路
K1はRO＜R2の条件の下でしか機能しない、又、
入力端子ｔの右側を見たインピーダンスR′Oは第
４図に示すごとき周波数特性を有し、周波数が
０の時抵抗値R2を呈し、周波数がOの時それ
に対応した抵抗値ROを呈する。即ち、この整合
回路K1の整合状態は、特定の周波数Oの時のみ
となる。そして、この周波数Oを可変するには、
インダクタンスL1及び容量Cxを同時に変化させ
る必要があるが、通常はインダクタンスL1を固
定として使用される場合が殆どである。従つて、
第２図においてもRO＝R′Oとなる周波数Oの設定
ポイントが問題となる。 Fig. 3 shows the matching circuit K1 extracted, and to explain it, a resistor R O is connected between the left side of the input terminal t and ground, and the matching circuit K1 is connected to the right side of the input terminal t. , a resistor R 2 is connected between the output terminal t' and ground. In this case, the matching circuit
K 1 only works under the condition that R O < R 2 , and
The impedance R′ O when looking at the right side of the input terminal t has a frequency characteristic as shown in Fig. 4. When the frequency is 0, it exhibits a resistance value R 2 , and when the frequency is O , it exhibits a corresponding resistance value R O. present. That is, the matching state of this matching circuit K1 is only at a specific frequency O. And to vary this frequency O ,
Although it is necessary to change the inductance L 1 and the capacitance C x at the same time, the inductance L 1 is usually used as a fixed value in most cases. Therefore,
In FIG. 2 as well, the problem is the setting point of the frequency O at which R O =R' O.
第５図は第１図の高周波回路に於ける周波数O
の設定例を示したもので、RiはMOS電界効果ト
ランジスタＱの入力抵抗Riの周波数特性曲線を示
し、これはインピーダンス（抵抗）R′Oより充分
大きく、しかも周波数の増大に従つてその値が漸
次低下する特性を呈している。インピーダンス
（抵抗）R′Oの周波数特性は、インダクタンスL1が
小さいときは曲線R′O1の如くなり、インダクタン
スL1が大きいときは曲線R′O2の如くなる。曲線R′O
１は受信周波数帯域L〜Hの上限周波数Hにおい
てインピーダンス（抵抗）R′OがROに等しくなる
ようにした場合であり、曲線R′O2は受信周波数帯
域L〜Hの適当な中間値Mにおいてインピーダン
ス（抵抗）R′OがROに等しくなるようにした場合
である。しかして、曲線R′O1の場合は、上限周波
数H近傍における定在波比が良好となるが、下限
周波数L付近では定在波比がかなり悪くなる。曲
線R′O2の場合は、中間の周波数Mにおいて定在波
比が良好となるが、下限及び上限周波数L，Hで
の定在波比は悪くなる。この様に、定在波比が悪
くなると、その近傍の電力利得が低下し、雑音指
数が悪化することになる。尚、この場合の定在波
比は略R′／O／ROで表わすことができる。 Figure 5 shows the frequency O in the high frequency circuit shown in Figure 1.
In this example, R i represents the frequency characteristic curve of the input resistance R i of the MOS field effect transistor Q, which is sufficiently larger than the impedance (resistance) R′ O , and also increases as the frequency increases. It exhibits the characteristic that the value gradually decreases. The frequency characteristic of the impedance (resistance) R'O becomes a curve R'O1 when the inductance L1 is small, and a curve R'O2 when the inductance L1 is large. Curve R′ O
1 is the case where the impedance (resistance) R′ O is made equal to R O at the upper limit frequency H of the receiving frequency band L to H , and the curve R′ O2 is the case where the appropriate intermediate value M of the receiving frequency band L to H is set. This is the case where the impedance (resistance) R' O is made equal to R O. Therefore, in the case of curve R′ O1 , the standing wave ratio near the upper limit frequency H is good, but the standing wave ratio near the lower limit frequency L becomes considerably poor. In the case of the curve R'O2 , the standing wave ratio is good at the intermediate frequency M , but the standing wave ratio at the lower and upper limit frequencies L and H is poor. As described above, when the standing wave ratio deteriorates, the power gain in the vicinity thereof decreases, and the noise figure deteriorates. Incidentally, the standing wave ratio in this case can be expressed approximately as R'/ O / RO .
発明の目的
上述の点に鑑み、本発明は回路構成簡単にし
て、広帯域に亘つて整合をとることのできるテレ
ビチユーナの高周波回路を提案しようとするもの
である。OBJECTS OF THE INVENTION In view of the above-mentioned points, the present invention aims to propose a high frequency circuit for a television tuner that has a simple circuit configuration and can perform matching over a wide band.
発明の概要
本発明によるテレビチユーナの高周波回路は、
高周波信号入力端子の入力抵抗より十分大で、周
波数の増大に従つて漸次減少する入力抵抗を有す
る半導体能動素子と、第１及び第２のインダクタ
ンス素子と、固定及び可変容量素子とを有し、第
１のインダクタンス素子の一端が高周波信号入力
端子に接続されると共に、他端が可変容量素子を
通じて接地され、固定容量素子の一端が第１のイ
ンダクタンス素子及び可変容量素子の接続中点に
接続されると共に、他端が第２のインダクタンス
素子を通じて接地され、固定容量素子及び第２の
インダクタンス素子の接続中点が半導体能動素子
の入力電極に接続されて成るものである。Summary of the Invention A high frequency circuit for a television tuner according to the present invention comprises:
a semiconductor active element having an input resistance that is sufficiently larger than the input resistance of a high frequency signal input terminal and gradually decreases as the frequency increases, first and second inductance elements, and fixed and variable capacitance elements; One end of the first inductance element is connected to a high frequency signal input terminal, the other end is grounded through a variable capacitance element, and one end of the fixed capacitance element is connected to a midpoint between the first inductance element and the variable capacitance element. At the same time, the other end is grounded through the second inductance element, and the connection midpoint of the fixed capacitance element and the second inductance element is connected to the input electrode of the semiconductor active element.
斯る本発明によれば、回路構成簡単にして広帯
域に亘つて整合をとることのできるテレビチユー
ナの高周波回路を得ることができる。 According to the present invention, it is possible to obtain a high frequency circuit for a television tuner that has a simple circuit configuration and can perform matching over a wide band.
実施例
以下に第６図を参照して、本発明の一実施例を
説明するも、第６図において第１図と対応する部
分には同一符号を付して説明する。入力端子ｔを
第１のコイルL1−コンデンサC1−コンデンサC2
を順次に通じてダブルゲートMOS電界効果トラ
ンジスタＱの一方のゲートに接続する。コイル
L1及びコンデンサC1の接続中点を可変容量コン
デンサ（可変容量ダイオード）CVのカソードに
接続し、そのアノードを接地する。コイルL1及
びコンデンサC1の接続中点を、抵抗器RCを通じ
て可変容量コンデンサCVに対する容量制御用直
流電圧の供給される入力端子T1に接続する。更
に、コンデンサC1，C2の接続中点を第２のコイ
ルL2を通じて接地する。トランジスタＱの他方
のゲートはAGC信号入力端子T2に接続される。Embodiment An embodiment of the present invention will be described below with reference to FIG. 6. In FIG. 6, parts corresponding to those in FIG. 1 are given the same reference numerals. Connect the input terminal t to the first coil L 1 - capacitor C 1 - capacitor C 2
are connected to one gate of the double-gate MOS field effect transistor Q through the terminals sequentially. coil
Connect the midpoint between L1 and capacitor C1 to the cathode of variable capacitor (variable capacitance diode) C V , and ground its anode. The midpoint of the connection between the coil L 1 and the capacitor C 1 is connected to the input terminal T 1 to which the capacitance control DC voltage is supplied to the variable capacitor C V through the resistor R C. Furthermore, the connection midpoint of capacitors C 1 and C 2 is grounded through the second coil L 2 . The other gate of transistor Q is connected to AGC signal input terminal T2 .
この第６図の高周波回路において、希望受信周
波数がこの高周波回路の受信周波数帯域の上限周
波数と等しいとすると、容量CVは容量C1より充
分小さくなり、コンデンサC1及びCVによる容量
分割は殆ど行なわれず、コンデンサC1を無視す
ることができる。 In the high frequency circuit shown in Fig. 6, if the desired reception frequency is equal to the upper limit frequency of the reception frequency band of this high frequency circuit, the capacitance C V will be sufficiently smaller than the capacitance C 1 , and the capacitance division by the capacitors C 1 and C V will be Very little is done and capacitor C 1 can be ignored.
次に希望受信周波数が受信周波数帯域の下限周
波数に等しいとすると、容量CVは大きくなり、
容量CVはC1に略等しくなる。この場合には、第
７図の等価回路に示す様に、コンデンサC1及び
C4の容量分割により、MOS電界効果トランジス
タＱの入力インピーダンスは、点Ｐにおいて約
（C1／C1＋C4）2倍となり、第１図の従来の高周波回路
に比較して、入力インピーダンス（抵抗）R′Oが
充分低くなる。尚、容量C4のコンデンサを同じ
符号C4で示し、容量C4はC4＝CV−CXの関係にあ
る。 Next, if the desired receiving frequency is equal to the lower limit frequency of the receiving frequency band, the capacitance C V will increase,
The capacitance C V is approximately equal to C 1 . In this case, as shown in the equivalent circuit of Figure 7, capacitors C 1 and
Due to the capacitance division of C 4 , the input impedance of the MOS field effect transistor Q becomes approximately (C 1 /C 1 +C 4 ) twice at point P, and the input impedance ( resistance) R′ O becomes sufficiently low. Incidentally, a capacitor having a capacitance C 4 is indicated by the same symbol C 4 , and the capacitance C 4 has a relationship of C 4 =C V −C X.
従つて第６図の高周波回路のインピーダンス整
合周波数Oを、第８図に示すごとく受信周波数帯
域L〜Hの上限周波数Hに等しく選べば、受信周
波数帯域L〜Hに亘たり良好な定在波比を得るこ
とができる。第８図において曲線R′Oは第５図の
曲線R′O1に対応し、曲線R′O3が本発明による、入
力端子tOの右側を見たインピーダンス（抵抗）R′O
の周波数特性を示し、周波数の増大に従つて漸次
その値が低下するが、その勾配は極く緩かであつ
て、その変化量は少ない。従つて、インピーダン
ス整合は周波数Oを受信周波数帯域L〜Hの上限
周波数Hに選べば、受信周波数L〜Hに亘り良好
な定在波比を得ることができ、その結果電力利得
が大となり、雑音指数も良好となる。 Therefore, if the impedance matching frequency O of the high-frequency circuit shown in Fig. 6 is selected to be equal to the upper limit frequency H of the receiving frequency band L to H as shown in Fig. 8, a good standing wave can be obtained over the receiving frequency band L to H. You can get the ratio. In FIG. 8 , the curve R′ O corresponds to the curve R′ O1 in FIG .
It shows a frequency characteristic, and its value gradually decreases as the frequency increases, but the slope is extremely gentle and the amount of change is small. Therefore, for impedance matching, if the frequency O is selected as the upper limit frequency H of the receiving frequency band L to H , a good standing wave ratio can be obtained over the receiving frequency band L to H , and as a result, the power gain is large. The noise figure is also good.
尚、第９図に示す如く、高周波回路の入力側に
フイルタＦを挿入することも可能であつて、この
場合にはフイルタＦの出力インピーダンスROと
なるものである。 Incidentally, as shown in FIG. 9, it is also possible to insert a filter F on the input side of the high frequency circuit, and in this case, the output impedance of the filter F becomes R O.
発明の効果
上述せる本発明によれば、回路構成簡単にして
広帯域に亘つて整合をとることのできるテレビチ
ユーナの高周波回路を得ることができる。Effects of the Invention According to the present invention described above, it is possible to obtain a high frequency circuit for a television tuner that has a simple circuit configuration and can perform matching over a wide band.
第１図は従来のテレビチユーナの高周波回路を
示す回路図、第２図は第１図の高周波回路の等価
回路を示す回路図、第３図は第２図の一部の回路
を示す回路図、第４図及び第５図は入力抵抗の周
波特性を示す曲線図、第６図は本発明によるテレ
ビチユーナの高周波回路の一実施例を示す回路
図、第７図は第６図の高周波回路の等価回路を示
す回路図、第８図は入力抵抗の周波数特性を示す
曲線図、第９図は本発明の他の実施例を示す回路
図である。
L1，L2は第１及び第２のインダクタ（コイ
ル）、C1は固定コンデンサ、CVは可変容量コンデ
ンサ、Ｑは半導体能動素子としてのダブルゲート
MOS電界効果トランジスタである。
FIG. 1 is a circuit diagram showing a high frequency circuit of a conventional television tuner, FIG. 2 is a circuit diagram showing an equivalent circuit of the high frequency circuit in FIG. 1, and FIG. 3 is a circuit diagram showing a part of the circuit in FIG. 4 and 5 are curve diagrams showing the frequency characteristics of the input resistance, FIG. 6 is a circuit diagram showing an embodiment of the high frequency circuit of a television tuner according to the present invention, and FIG. 7 is an equivalent of the high frequency circuit of FIG. 6. FIG. 8 is a curve diagram showing the frequency characteristics of the input resistance, and FIG. 9 is a circuit diagram showing another embodiment of the present invention. L 1 and L 2 are the first and second inductors (coils), C 1 is a fixed capacitor, C V is a variable capacitor, and Q is a double gate as a semiconductor active element.
It is a MOS field effect transistor.
Claims (1)
で、周波数の増大に従つて漸次減少する入力抵抗
を有する半導体能動素子と、第１及び第２のイン
ダクタンス素子と、固定及び可変容量素子とを有
し、上記第１のインダクタンス素子の一端が上記
高周波信号入力端子に接続されると共に、他端が
上記可変容量素子を通じて接地され、上記固定容
量素子の一端が上記第１のインダクタンス素子及
び上記可変容量素子の接続中点に接続されると共
に、他端が第２のインダクタンス素子を通じて接
地され、上記固定容量素子及び上記第２のインダ
クタンス素子の接続中点が上記半導体能動素子の
入力電極に接続されて成ることを特徴とするテレ
ビチユーナの高周波回路。1. A semiconductor active element having an input resistance that is sufficiently larger than the input resistance of a high-frequency signal input terminal and gradually decreases as the frequency increases, first and second inductance elements, and fixed and variable capacitance elements. , one end of the first inductance element is connected to the high frequency signal input terminal, the other end is grounded through the variable capacitance element, and one end of the fixed capacitance element is connected to the first inductance element and the variable capacitance element. and the other end is grounded through a second inductance element, and the connection midpoint of the fixed capacitance element and the second inductance element is connected to the input electrode of the semiconductor active element. A high frequency circuit for a television tuner characterized by the following.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13815983A JPS6030225A (en) | 1983-07-28 | 1983-07-28 | High frequency circuit of television tuner |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13815983A JPS6030225A (en) | 1983-07-28 | 1983-07-28 | High frequency circuit of television tuner |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6030225A JPS6030225A (en) | 1985-02-15 |
| JPH0457135B2 true JPH0457135B2 (en) | 1992-09-10 |
Family
ID=15215396
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13815983A Granted JPS6030225A (en) | 1983-07-28 | 1983-07-28 | High frequency circuit of television tuner |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6030225A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2880070B2 (en) * | 1994-03-31 | 1999-04-05 | 株式会社カネカメディックス | Medical wire having an indwelling member |
| US6835185B2 (en) | 1998-12-21 | 2004-12-28 | Micrus Corporation | Intravascular device deployment mechanism incorporating mechanical detachment |
-
1983
- 1983-07-28 JP JP13815983A patent/JPS6030225A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6030225A (en) | 1985-02-15 |
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