JPH0454014A - Double tuning circuit - Google Patents
Double tuning circuitInfo
- Publication number
- JPH0454014A JPH0454014A JP16441990A JP16441990A JPH0454014A JP H0454014 A JPH0454014 A JP H0454014A JP 16441990 A JP16441990 A JP 16441990A JP 16441990 A JP16441990 A JP 16441990A JP H0454014 A JPH0454014 A JP H0454014A
- Authority
- JP
- Japan
- Prior art keywords
- capacitor
- frequency
- tuning
- selectivity
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims abstract description 55
- 230000008878 coupling Effects 0.000 claims description 17
- 238000010168 coupling process Methods 0.000 claims description 17
- 238000005859 coupling reaction Methods 0.000 claims description 17
- 230000009977 dual effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000007423 decrease Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、FMチューナ等の同調回路に係り、特にフロ
ントエンドの入力部に好適な複同調回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a tuning circuit such as an FM tuner, and particularly to a double tuning circuit suitable for an input section of a front end.
FMチューナ等においては、希望受信周波数に同調させ
るために、フロントエンドの入力部に同調回路が設けら
れている。同調回路としては、可変容量コンデンサとイ
ンダクタンスコイルからなる並列共振回路が使用される
。この並列共振回路が一つのものを単同調回路といい、
2以上のものを複同調回路という。In an FM tuner or the like, a tuning circuit is provided at the input section of the front end in order to tune to a desired reception frequency. A parallel resonant circuit consisting of a variable capacitor and an inductance coil is used as the tuning circuit. A single parallel resonant circuit is called a singly tuned circuit.
A circuit with two or more is called a double-tuned circuit.
複同調回路は、受信周波数の選択度を向上させる目的で
用いられ、通常一般に、同一構成の複数の並列共振回路
を容量結合して構成される。第3図に従来の複同調回路
の例を示す。A double-tuned circuit is used for the purpose of improving the selectivity of reception frequencies, and is generally constructed by capacitively coupling a plurality of parallel resonant circuits having the same configuration. FIG. 3 shows an example of a conventional double-tuned circuit.
第3図に示すように、アンテナ等の入力信号源Sからの
入力信号vINはカップリングコンデンサCを介して同
調コンデンサ01同調コイルL、からなる共振回路で選
択された所定の周波数信号はカップリングコンデンサC
2を介して同調コンデンサC1同調コイルL2からなる
共振臼路によりさらに選択され、カップリングコンデン
サCを介して出力信号V として負荷インピ3
OUT
−ダンスZLに供給される。As shown in FIG. 3, an input signal vIN from an input signal source S such as an antenna is coupled via a coupling capacitor C to a selected predetermined frequency signal in a resonant circuit consisting of a tuning capacitor 01 and a tuning coil L. Capacitor C
2 is further selected by a resonant circuit consisting of a tuning capacitor C1 and a tuning coil L2.
OUT - Supplied to Dance ZL.
上記従来の複同調回路において問題となるのは、受信周
波数によって選択度Qが変動する点である。A problem with the conventional double-tuned circuit described above is that the selectivity Q varies depending on the receiving frequency.
すなわち、第4図に示すように、例えば、同調コンデン
サC%Cの値をそれぞれ20(pF)、25 (pF)
、30 (pF) 、35 (pF)というように変
化させた場合、低い受信周波数になるほど選択度Qが鋭
くなって、周波数の帯域幅が狭くなり、高い受信周波数
になるほど選択度Qが甘くなって帯域幅が広くなるとい
う現象を生ぜしめる。このように、同調回路の選択度Q
が受信周波数において変動することは受信機の特性上好
ましくない。That is, as shown in FIG. 4, for example, the values of the tuning capacitor C%C are 20 (pF) and 25 (pF), respectively.
, 30 (pF), and 35 (pF), the lower the reception frequency, the sharper the selectivity Q and the narrower the frequency bandwidth, and the higher the reception frequency, the sweeter the selectivity Q. This causes the phenomenon that the bandwidth becomes wider. In this way, the selectivity Q of the tuned circuit is
It is undesirable for the characteristics of the receiver to fluctuate in the receiving frequency.
本発明の目的は、選択度の周波数依存性を抑制しうる複
同調回路を提供することにある。An object of the present invention is to provide a double-tuned circuit that can suppress frequency dependence of selectivity.
上記課題を解決するために、本発明は、コンデンサとイ
ンダクタンスからなる少なくとも2つ以上の並列共振回
路をその一端側において容量結合した複同調回路におい
て、前記各並列共振回路の各コンデンサの他端同士を結
合し、その結合点を他のコンデンサを介して接地し、各
インダクタンスを接地して構成する。In order to solve the above-mentioned problems, the present invention provides a double-tuned circuit in which at least two parallel resonant circuits each including a capacitor and an inductance are capacitively coupled at one end thereof, in which the other ends of each capacitor of each of the parallel resonant circuits are connected to each other. The connection point is grounded via another capacitor, and each inductance is grounded.
本発明によれば、互に容量結合された複数の並列共振回
路中のコンデンサ同士が結合されたことになり、前段側
のコンデンサから高周波信号の一部が後段側のコンデン
サに回り込む状態で共振回路同士が結合され、その結合
の度合は付加された他のコンデンサのインピーダンスが
大となる低い周波数になるほど大となる。その結果、低
い周波数になるに従って選択度Qの周波数帯域幅が広く
なるため、周波数の違いによる選択度の変動を抑制し、
安定した選択性能を得ることが可能となる。According to the present invention, capacitors in a plurality of parallel resonant circuits that are capacitively coupled to each other are coupled to each other, and a part of the high frequency signal from the capacitor in the previous stage goes around to the capacitor in the latter stage, and the resonant circuit The degree of the coupling increases as the frequency becomes lower and the impedance of the other added capacitor increases. As a result, as the frequency becomes lower, the frequency bandwidth of selectivity Q becomes wider, suppressing the variation in selectivity due to differences in frequency,
It becomes possible to obtain stable selection performance.
次に、本発明の実施例を図面に基づいて説明する。 Next, embodiments of the present invention will be described based on the drawings.
第1図に本発明の実施例を示す。アンテナ等の入力信号
源Sからの入力信号■INはカップリングコンデンサC
1に入力される。カップリングコンデンサC1の他端側
には可変容量の同調コンデンサC1同調コイルL、から
なる第1の同調回路の一端とカップリングコンデンサC
2の一端が接続されている。カップリングコンデンサC
2の他端には可変容量の同調コンデンサC1同調コイル
L2からなる第2の同調回路の一端とカップリングコン
デンサC3の一端が接続されている。カップリングコン
デンサC3の他端は負荷インピーダンスZLに接続され
、ここに出力信号■。0.が出力される。FIG. 1 shows an embodiment of the present invention. Input signal from input signal source S such as antenna ■IN is coupling capacitor C
1 is input. The other end of the coupling capacitor C1 has one end of a first tuning circuit consisting of a variable capacitance tuning capacitor C1 and a tuning coil L, and a coupling capacitor C1.
One end of 2 is connected. Coupling capacitor C
One end of a second tuning circuit consisting of a variable capacitance tuning capacitor C1 and a tuning coil L2 and one end of a coupling capacitor C3 are connected to the other end of the coupling capacitor C3. The other end of the coupling capacitor C3 is connected to the load impedance ZL, and the output signal ■ is here. 0. is output.
第1の同調回路(C,L、)と第2の同調口路(C,L
)はカップリングコンデンサC2により容量結合されて
いる。同調コンデンサc4の他端と同調コンデンサC5
の他端とは共通結合され、その結合点からコンデンサC
6を介して接地されている。同調コイルL 、L
の他端は共に直接接地されている。The first tuning circuit (C,L,) and the second tuning path (C,L,)
) are capacitively coupled by a coupling capacitor C2. The other end of tuning capacitor c4 and tuning capacitor C5
It is commonly connected to the other end, and the capacitor C is connected from that connection point.
It is grounded via 6. Tuning coil L, L
The other ends of both are directly grounded.
以上の構成において、入力信号vINはカップリングコ
ンデンサCIを介して同調コンデンサC4、同調コイル
Llに与えられるが、同調コンデンサCを通った高周波
信号はコンデンサC6を介して接地に流れるとともに、
その一部は同調コンデンサCと結合関係にある同調コン
デンサC5に流れ込む。コンデンサC6のインピーダン
スは周波数に逆比例して周波数が低くなるほど大きくな
り、同調コンデンサCから同調コンデンサC5への信号
の流れ込み量は増加する。その結果、出力信号■ の
周波数帯域が広くなる。その結果、11T
周波数が低くなるほど出力信号V の周波数帯tlT
域が広くなり、選択度Qの鋭さは甘くなる。しかし、も
ともと、高い周波数になるほど選択度Qが甘くなる特性
を有する複同調回路の場合、特性面からすれば、周波数
に依存する選択度Qの変動は抑制され安定した特性とな
る。この例を第2図に示す。第4図の従来例と比較して
わかるように、選択度が統一されている。In the above configuration, the input signal vIN is applied to the tuning capacitor C4 and the tuning coil Ll via the coupling capacitor CI, but the high frequency signal passing through the tuning capacitor C flows to the ground via the capacitor C6, and
A portion of it flows into tuning capacitor C5, which is in coupling relationship with tuning capacitor C. The impedance of the capacitor C6 is inversely proportional to the frequency, and increases as the frequency decreases, and the amount of signal flowing from the tuning capacitor C to the tuning capacitor C5 increases. As a result, the frequency band of the output signal (2) becomes wider. As a result, as the 11T frequency becomes lower, the frequency band tlT of the output signal V becomes wider, and the selectivity Q becomes less sharp. However, in the case of a double-tuned circuit which originally has the characteristic that the selectivity Q becomes weaker as the frequency becomes higher, from the viewpoint of characteristics, fluctuations in the selectivity Q depending on the frequency are suppressed and stable characteristics are obtained. An example of this is shown in FIG. As can be seen from a comparison with the conventional example in FIG. 4, the selectivity is unified.
以上の通り、本発明によれば、受信周波数によって選択
度が変動することを抑制することができ、安定したチュ
ーニング動作が可能となる。As described above, according to the present invention, it is possible to suppress the selectivity from varying depending on the receiving frequency, and stable tuning operation is possible.
S・・・入力信号源S...Input signal source
第1図は本発明の実施例を示す回路図、第2図は同調コ
ンデンサをパラメータとする選択特性図、
第3図は従来の複同調回路を示す回路図、第4図は同調
コンデンサをパラメータとする従来の選択特性図である
。
vIN・・・入力信号
■ ・・・出力信号
UT
C1・・・カップリングコンデンサ
C2・・・カップリングコンデンサ
C3・・・カップ−リングコンデンサ
C4・・・同調コンデンサ
C5・・・同調コンデンサ
C6・・・コンデンサ
L、・・・同調コイル
L2・・・同調コイル
Z、・・・負荷インピーダンスFig. 1 is a circuit diagram showing an embodiment of the present invention, Fig. 2 is a selection characteristic diagram using a tuning capacitor as a parameter, Fig. 3 is a circuit diagram showing a conventional double-tuned circuit, and Fig. 4 is a diagram showing a tuning capacitor as a parameter. FIG. 3 is a conventional selection characteristic diagram. vIN...Input signal■...Output signal UT C1...Coupling capacitor C2...Coupling capacitor C3...Coupling capacitor C4...Tuning capacitor C5...Tuning capacitor C6...・Capacitor L, ... Tuning coil L2 ... Tuning coil Z, ... Load impedance
Claims (1)
上の並列共振回路をその一端側において容量結合した複
同調回路において、 前記各並列共振回路の各コンデンサの他端同士を結合し
、その結合点を他のコンデンサを介して接地し、各イン
ダクタンスを接地したことを特徴とする複同調回路。[Claims] In a double-tuned circuit in which at least two or more parallel resonant circuits each consisting of a capacitor and an inductance are capacitively coupled at one end thereof, the other ends of each capacitor of each of the parallel resonant circuits are coupled to each other, and the coupling A double-tuned circuit characterized in that a point is grounded through another capacitor, and each inductance is grounded.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16441990A JPH0454014A (en) | 1990-06-22 | 1990-06-22 | Double tuning circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16441990A JPH0454014A (en) | 1990-06-22 | 1990-06-22 | Double tuning circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0454014A true JPH0454014A (en) | 1992-02-21 |
Family
ID=15792790
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16441990A Pending JPH0454014A (en) | 1990-06-22 | 1990-06-22 | Double tuning circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0454014A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0459633U (en) * | 1990-09-28 | 1992-05-21 | ||
JP2004129053A (en) * | 2002-10-04 | 2004-04-22 | Mitsubishi Electric Corp | Dc blocking circuit and communication equipment |
-
1990
- 1990-06-22 JP JP16441990A patent/JPH0454014A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0459633U (en) * | 1990-09-28 | 1992-05-21 | ||
JP2004129053A (en) * | 2002-10-04 | 2004-04-22 | Mitsubishi Electric Corp | Dc blocking circuit and communication equipment |
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