KR100243838B1 - Input circuit of television tuner - Google Patents

Input circuit of television tuner Download PDF

Info

Publication number
KR100243838B1
KR100243838B1 KR1019970013895A KR19970013895A KR100243838B1 KR 100243838 B1 KR100243838 B1 KR 100243838B1 KR 1019970013895 A KR1019970013895 A KR 1019970013895A KR 19970013895 A KR19970013895 A KR 19970013895A KR 100243838 B1 KR100243838 B1 KR 100243838B1
Authority
KR
South Korea
Prior art keywords
frequency
capacitor
circuit
varactor
image
Prior art date
Application number
KR1019970013895A
Other languages
Korean (ko)
Other versions
KR970073038A (en
Inventor
쯔또무 구니시마
Original Assignee
가타오카 마사타카
알프스 덴키 가부시키가이샤
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 가타오카 마사타카, 알프스 덴키 가부시키가이샤 filed Critical 가타오카 마사타카
Publication of KR970073038A publication Critical patent/KR970073038A/en
Application granted granted Critical
Publication of KR100243838B1 publication Critical patent/KR100243838B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/26—Circuits for superheterodyne receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N5/00—Details of television systems
    • H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
    • H04N5/50—Tuning indicators; Automatic tuning control
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/12—Bandpass or bandstop filters with adjustable bandwidth and fixed centre frequency
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1708—Comprising bridging elements, i.e. elements in a series path without own reference to ground and spanning branching nodes of another series path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/175—Series LC in series path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00—Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/01—Frequency selective two-port networks
    • H03H7/17—Structural details of sub-circuits of frequency selective networks
    • H03H7/1741—Comprising typical LC combinations, irrespective of presence and location of additional resistors
    • H03H7/1758—Series LC in shunt or branch path
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J3/00—Continuous tuning
    • H03J3/02—Details
    • H03J3/16—Tuning without displacement of reactive element, e.g. by varying permeability
    • H03J3/18—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance
    • H03J3/185—Tuning without displacement of reactive element, e.g. by varying permeability by discharge tube or semiconductor device simulating variable reactance with varactors, i.e. voltage variable reactive diodes
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Multimedia (AREA)
  • Input Circuits Of Receivers And Coupling Of Receivers And Audio Equipment (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)
  • Noise Elimination (AREA)

Abstract

본 발명은 이미지트랩 주파수의 가변범위를 넓게 하고, 또 목적하는 이미지주파수에 이미지트랩 주파수를 용이하게 맞추려는 것이다.The present invention aims to widen the variable range of the image trap frequency and to easily adjust the image trap frequency to the desired image frequency.

본 발명에서는 인덕턴스(L2)및 제 1 버랙터다이오드(28)의 직렬회로와, 콘덴서(C3)와 제 2 버랙터 다이오드(29)의 직렬회로를 병렬로 접속함으로써 이미지트랩회로가 구성된다. 낮은 주파수를 수신하는 경우에는 콘덴서(C3)와 제 1, 2 버랙터다이오드(28, 29)의 전체용량은 거의 콘덴서(C3)의 용량이 되고 실질상 제 1, 2 버랙터다이오드(28, 29)의 용량은 무시할 수 있다. 높은 주파수를 수신하는 경우에는 인덕턴스(L2)가 작고 또 제 1, 2 버랙터다이오드(28, 29)의 용량이 작아지기 때문에 콘덴서(C3)와 제 1, 2 버랙터다이오드(28, 29)의 전체용량은 작아진다.In the present invention, an image trap circuit is formed by connecting the series circuit of the inductance L2 and the first varactor diode 28 and the series circuit of the capacitor C3 and the second varactor diode 29 in parallel. In the case of receiving a low frequency, the total capacity of the capacitor C3 and the first and second varactor diodes 28, 29 is almost the capacity of the capacitor C3, and the first and second varactor diodes 28, 29 are substantially. ) Can be ignored. In the case of receiving a high frequency, the inductance L2 is small and the capacities of the first and second varactor diodes 28 and 29 become small, so that the capacitors C3 and the first and second varactor diodes 28 and 29 are reduced. The total capacity is small.

Description

텔레비젼튜너의 입력회로{INPUT CIRCUIT OF TELEVISION TUNER}Input circuit of TV tuner {INPUT CIRCUIT OF TELEVISION TUNER}

본 발명은 소망하는 동조주파수에 대하여 방해파가 되는 영상(이미지)주파수를 제거하는 이미지트랩회로를 가지는 텔레비젼튜너의 입력회로에 관한 것이다.The present invention relates to an input circuit of a television tuner having an image trap circuit for removing an image (image) frequency which becomes a disturbing wave with respect to a desired tuning frequency.

일반적으로 텔레비젼튜너 등의 튜너에서는 소망하는 수신주파수에 대하여 중간주파수분만큼 높은 국부발진주파수를 혼합함으로써 중간주파수를 얻을 수 있다. 이 경우, 국부발진주파수보다 중간주파수의 분만큼 높은 수신주파수(이미지주파수)가 입력되면, 이미지방해가 발생한다.In general, in a tuner such as a television tuner, an intermediate frequency can be obtained by mixing a local oscillation frequency as high as an intermediate frequency with respect to a desired reception frequency. In this case, if a reception frequency (image frequency) higher than the local oscillation frequency by an intermediate frequency is input, image disturbance occurs.

도 3은 종래의 텔레비젼튜너의 입력회로(1)의 기본회로를 나타내고 있다. 안테나(2)를 거쳐 수신한 신호중 VHF대(40∼470MHz)가 VHF대 선택필터(IF필터)(3)에 의하여 축출되고, 결합콘덴서(C1), 입력회로(1)를 거쳐 고주파증폭회로(4)에 인가된다. 입력회로(1)에서는 결합콘덴서(C1)에 대하여 가변인덕턴스(L1, L2)의 각 일단이 접속되고, 가변인덕턴스(L1)의 타단은 콘덴서(C2)를 거쳐 접지되어 있다. 또 가변인덕턴스(L2)의 타단은 버랙터다이오드(VD1)를 거쳐 접지됨과 동시에 버랙터다이오드(VD2)를 거쳐 고주파증폭회로(4)에 접속되고, 또한 가변인덕턴스(L2)및 버랙터다이오드(VD2)의 양단에 콘덴서(C3)가 병렬로 접속되어 있다.3 shows the basic circuit of the input circuit 1 of the conventional television tuner. Among the signals received through the antenna 2, the VHF band (40 to 470 MHz) is evicted by the VHF band selection filter (IF filter) 3, and the high frequency amplifier circuit (C1) and the input circuit (1) pass through the coupling capacitor (C1). 4) is applied. In the input circuit 1, one end of the variable inductances L1 and L2 is connected to the coupling capacitor C1, and the other end of the variable inductance L1 is grounded through the capacitor C2. The other end of the variable inductance L2 is grounded through the varactor diode VD1 and connected to the high frequency amplification circuit 4 through the varactor diode VD2, and the variable inductance L2 and the varactor diode VD2. The capacitor C3 is connected in parallel at both ends of the circuit.

여기서 VHF대(40∼470MHz)의 최저주파수와 최대주파수의 비가 크기 때문에 소망하는 동조주파수가 고채널대인지 또는 저채널대인지에 따라 가변인덕턴스(L1, L2)는 높은 주파수의 수신시에 작아지도록 하고 반대로 저주파수의 수신시에는 커지도록 제어함으로써 전대역에서 동조하도록 구성되어 있다.Since the ratio of the lowest frequency and the maximum frequency of the VHF band (40 to 470 MHz) is large, the variable inductances L1 and L2 become small at the time of receiving the high frequency depending on whether the desired tuning frequency is the high channel band or the low channel band. On the contrary, it is configured to tune in the entire band by controlling the signal to be large when receiving low frequencies.

또 버랙터다이오드(VD1, VD2)의 용량은 높은 주파수의 수신시에 작아지도록 하고 반대로 저주파수의 수신시에는 커지도록 제어함으로써 희망주파수에 있어서의 임피던스의 정합을 행한다. 또 도 4에 나타낸 바와같이 가변인덕턴스(L2)및 버랙터다이오드(VD2)의 직렬회로에 대하여 콘덴서(C3)를 병렬로 접속함으로써 소망하는 동조주파수에 대하여 방해파가 되는 이미지주파수를 트랩하는 이미지트랩회로가 구성된다.In addition, the capacitance of the varactor diodes VD1 and VD2 is made smaller when receiving a high frequency and, on the contrary, becomes larger when receiving a lower frequency, thereby matching impedance at a desired frequency. As shown in Fig. 4, by connecting the capacitor C3 in parallel to the series circuits of the variable inductance L2 and the varactor diode VD2, an image trap circuit for trapping an image frequency which becomes a disturbing wave to a desired tuning frequency. Is composed.

그러나 상기 종래의 입력회로(1)에서는 이미지트랩회로를 구성하기 위하여 콘덴서(C3)를 인덕턴스(L2) 및 버랙터다이오드(VD2)의 직렬회로에 대하여 병렬로 접속하고 있기 때문에 콘덴서(C3)용량의 설정이 매우 곤란하며, 그 결과 이미지방해가 발생한다는 문제점이 있다. 즉 콘덴서를 크게 하면 이미지트랩주파수의 가변범위는 넓어지나, 고주파수까지 가변으로 할 수 없다. 왜냐하면, 높은 주파수의 수신시에는 가변인덕턴스(L1, L2)는 작은 값으로 동조하고, 이 인덕턴스가 작은 L2에 콘덴서(C3)가 병렬로 접속되고 또 목적하는 이미지트랩주파수는 이 수신동조주파수에서 (중간주파수 ×2)분만큼 높기 때문에 이 상태에서 목적하는 이미지트랩주파수에 맞추기 위해서는 C3를 작게 하지 않으면 않된다.However, in the conventional input circuit 1, the capacitor C3 is connected in parallel to the series circuit of the inductance L2 and the varactor diode VD2 in order to form an image trap circuit. The setting is very difficult, and as a result, there is a problem that image disturbance occurs. In other words, when the capacitor is enlarged, the variable range of the image trap frequency becomes wider, but it cannot be changed to high frequency. For high frequency reception, the variable inductance L1, L2 is tuned to a small value, and the capacitor C3 is connected in parallel to L2 with a small inductance, and the desired image trap frequency is ( Since it is as high as the intermediate frequency x 2) minutes, C3 must be made small in order to meet the desired image trap frequency.

그러나 C3를 작게 하면, 이미지트랩주파수의 가변범위가 전체적으로 좁아지고, 목적으로 하는 이미지주파수에 이미지트랩주파수를 맞추기 어렵게 된다.However, if C3 is made small, the variable range of the image trap frequency becomes narrow as a whole, making it difficult to match the image trap frequency to the desired image frequency.

본 발명은 상기 종래의 문제점을 감안하여 이미지트랩주파수의 가변범위를 넓게 할 수 있음과 동시에 목적으로 하는 이미지주파수에 이미지트랩주파수를 용이하게 맞출 수 있는 텔레비젼튜너의 입력회로를 제공하는 것을 목적으로 한다.SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to provide an input circuit of a TV tuner capable of widening a variable range of an image trap frequency and at the same time easily fitting an image trap frequency to a desired image frequency. .

본 발명은 상기 목적을 달성하기 위하여 이미지트랩용 콘덴서에 대하여 버랙터다이오드를 추가하여 수신주파수에 따라 버랙터다이오드의 용량을 변화시키도록 한 것이다.The present invention is to add a varactor diode to the capacitor for the image trap to achieve the above object to change the capacity of the varactor diode according to the reception frequency.

도 1은 본 발명에 관한 텔레비젼튜너의 입력회로의 일실시예를 나타낸 회로도,1 is a circuit diagram showing an embodiment of an input circuit of a television tuner according to the present invention;

도 2는 도 1의 입력회로의 기본회로 및 이미지트랩회로를 나타낸 회로도,2 is a circuit diagram illustrating a basic circuit and an image trap circuit of the input circuit of FIG. 1;

도 3은 종래의 텔레비젼튜너의 입력회로의 기본회로를 나타낸 회로도,3 is a circuit diagram showing a basic circuit of an input circuit of a conventional television tuner;

도 4는 도 3의 이미지트랩회로를 나타낸 회로도이다.4 is a circuit diagram illustrating the image trap circuit of FIG. 3.

(도면의 주요부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)

L2 : 인덕턴스 C3 : 콘덴서L2: Inductance C3: Capacitor

28, 29 : 제 1, 제 2 버랙터다이오드28, 29: 1st and 2nd varactor diodes

이와 같은 구성에 의하여 이미지트랩용 콘덴서의 용량을 비교적 크게 하여도 높은주파수의 수신시에 콘덴서와 버랙터다이오드의 전체용량을 작게 할 수 있다. 그 결과, 이미지트랩의 주파수의 가변범위를 넓게 할 수 있음과 동시에 목적으로 하는 이미지주파수에 이미지트랩주파수를 용이하게 맞출 수 있다.By such a configuration, even when the capacitance of the image trap capacitor is relatively large, the total capacitance of the capacitor and the varactor diode can be reduced at the time of reception of high frequency. As a result, the variable range of the frequency of the image trap can be widened and the image trap frequency can be easily adjusted to the desired image frequency.

본 발명의 실시예는 동조용 인덕턴스 및 제 1버랙터다이오드의 직렬회로에 대하여 이미지트랩용 콘덴서 및 버랙터다이오드의 직렬회로를 병렬로 접속하고 상기 제 1, 제 2버랙터다이오드에 공통의 동조용 전압을 인가하여 그 용량을 변화시킴으로써 각각 동조주파수와 이미지트랩주파수를 변화시키는 것을 특징으로 한다.An embodiment of the present invention connects a series circuit of an image trap capacitor and a varactor diode in parallel to a tuning inductance and a series circuit of a first varactor diode, and has a common tuning for the first and second varactor diodes. It is characterized in that the tuning frequency and the image trap frequency are changed by applying a voltage and changing its capacitance.

(실시예)(Example)

이하 도면을 참조하여 본 발명의 실시예를 설명한다. 도 1은 본 발명에 관한 텔레비젼튜너의 입력회로의 일실시예를 나타낸 회로도, 도 2는 도 1의 입력회로의 기본회로 및 이미지트랩회로를 나타낸 회로도이다. 또한 종래예와 동일한 구성부재에는 동일참조부호를 붙힌다.Hereinafter, embodiments of the present invention will be described with reference to the drawings. 1 is a circuit diagram showing an embodiment of an input circuit of a television tuner according to the present invention, and FIG. 2 is a circuit diagram showing a basic circuit and an image trap circuit of the input circuit of FIG. The same constituent members as in the prior art are given the same reference numerals.

도 1에 있어서, 안테나(2)를 거쳐 수신한 신호중 VHF대(40∼470 MHz)가 VHF대선택용 필터(3)에 의하여 추출되고, 입력회로(1a), 결합콘덴서(5)를 거쳐 고주파증폭회로(4)에 인가된다. 입력회로(1a)의 입력단자(23)는 인덕터(6, 7, 8), 콘덴서(9), 인덕턴스(L2), 제 1 버랙터다이오드(28)를 거쳐 출력단자(24)에 접속됨과 동시에 이미지트랩용 콘덴서(C3) 및 제 2 버랙터다이오드(29)의 직렬회로를 거쳐 출력단자(24)에 접속되어 있다.In Fig. 1, the VHF band (40 to 470 MHz) among the signals received via the antenna 2 is extracted by the VHF band selection filter 3, and is amplified by the high frequency amplifier through the input circuit 1a and the coupling capacitor 5. Is applied to the circuit 4. The input terminal 23 of the input circuit 1a is connected to the output terminal 24 via the inductors 6, 7, 8, the condenser 9, the inductance L2, and the first varactor diode 28. It is connected to the output terminal 24 via the series circuit of the image trap capacitor C3 and the 2nd varactor diode 29. As shown in FIG.

또 인덕터(6, 7)의 접속점은 다이오드(13)와 인덕터(16)를 거쳐 저항(20, 22), 콘덴서(21)의 각 일단에 접속되고, 저항(22)의 타단은 VHF의 저채널대 선택전압공급단자(27)에 접속되어 있다. 저항(20)과 콘덴서(21)의 각 타단은 접지되어 있다. 인덕터(7, 8)의 접속점은 인덕터(12)의 일단에 접속되고, 인덕터(12)의 타단은 콘덴서(18)를 거쳐 접지됨과 동시에 저항(R31)을 거쳐 VHF의 고채널대 선택전압공급단자(26)에 접속되어 있다.In addition, the connection points of the inductors 6 and 7 are connected to the respective ends of the resistors 20 and 22 and the capacitor 21 via the diode 13 and the inductor 16, and the other end of the resistor 22 is the low channel of the VHF. It is connected to the large select voltage supply terminal 27. Each other end of the resistor 20 and the capacitor 21 is grounded. The connection points of the inductors 7 and 8 are connected to one end of the inductor 12, and the other end of the inductor 12 is grounded through the capacitor 18 and at the same time through the resistor R31, the high channel to select voltage supply terminal of the VHF. It is connected to (26).

또한 인덕터(8)와 콘덴서(9)의 접속점은 다이오드(14)를 거쳐 다이오드(13)와 인덕터(16)의 접속점에 접속되어 있다. 또 동조전압공급단자(25)를 거쳐 공급되는 역방향의 전압이 저항(19)을 거쳐 버랙터다이오드(15, 28)에 인가됨과 동시에 저항(30)을 거쳐 제 2 버랙터다이오드(29)에 인가된다.In addition, the connection point of the inductor 8 and the condenser 9 is connected to the connection point of the diode 13 and the inductor 16 via the diode 14. In addition, the reverse voltage supplied via the tuning voltage supply terminal 25 is applied to the varactor diodes 15 and 28 via the resistor 19 and to the second varactor diode 29 via the resistor 30. do.

여기서 VHF대(40∼470MHz)의 최저주파수와 최대주파수의 비가 크기 때문에 고채널대 선택전압공급단자(26) 또는 저채널대 선택전압공급단자(27)에 대하여 선택적으로 전압이 인가되고, 도 2(a)에 나타낸 인덕턴스(L1, L2)가 변화하도록 제어된다. 도 2(a)를 참조하여 이 기본회로를 설명하면, 입력측이 가변인덕턴스(L1, L2)의 각 일단이 접속되고, 인덕턴스(L1)의 타단은 콘덴서(C2)를 거쳐 접지되어 있다.Since the ratio between the lowest frequency and the maximum frequency of the VHF band (40 to 470 MHz) is large, a voltage is selectively applied to the high channel select voltage supply terminal 26 or the low channel select voltage supply terminal 27, and FIG. 2. The inductance L1, L2 shown in (a) is controlled to change. Referring to Fig. 2 (a), the basic circuit is described, and one end of each of the variable inductances L1 and L2 is connected to the input side, and the other end of the inductance L1 is grounded through the capacitor C2.

또 인덕턴스(L2)의 타단은 버랙터다오드(VD1)를 거쳐 접지됨과 동시에 제 1 버랙터다이오드(28)를 거쳐 고주파증폭회로(4)에 접속되고 또한 인덕턴스(L2)및 제 1 버랙터다이오드(28)의 양단에 콘덴서(C3)와 제 2 버랙터다이오드(29)의 직렬회로가 병렬로 접속되어 있다. 여기서 인덕턴스(L1, L2)는 높은주파수의 수신시에는 작아지도록, 반대로 낮은주파수의 수신시에는 커지도록 제어된다.The other end of the inductance L2 is grounded through the varactor diode VD1 and is connected to the high frequency amplification circuit 4 via the first varactor diode 28, and the inductance L2 and the first varactor diode ( The serial circuits of the capacitor C3 and the second varactor diode 29 are connected in parallel at both ends of the circuit 28. Here, the inductances L1 and L2 are controlled to be smaller when receiving a high frequency and, conversely, larger when receiving a lower frequency.

또 이와 같은 구성의 이미지트랩회로는 도 2(b)에 나타낸 바와같이 인덕턴스(L2)와 제 1 버랙터다이오드(28)의 직렬회로 및 콘덴서(C3)와 제 2 버랙터다이오드(29)의 직렬회로가 병렬로 접속된 회로가 된다. 여기서 버랙터 다이오드 (VD1, 28, 29)의 용량은 그 역방향 전압이 커지면 작아지기 때문에 높은주파수를 수신할 경우에는 용량이 작아지도록 또한 낮은주파수를 수신할 경우에는 용량이 커지도록 역방향 전압이 제어된다.As shown in FIG. 2 (b), the image trap circuit having such a configuration includes a series circuit of an inductance L2 and a first varactor diode 28 and a series of a capacitor C3 and a second varactor diode 29. FIG. The circuit is a circuit connected in parallel. In this case, the capacity of the varactor diodes VD1, 28, 29 decreases as the reverse voltage increases, so that the reverse voltage is controlled so that the capacity decreases when receiving a high frequency and increases when the low frequency is received. .

도 2(b)에 있어서, 낮은주파수를 수신할 경우에는 인덕턴스(L2)가 크고, 또 제 1, 2 버랙터다이오드(28, 29)의 용량이 커지기 때문에 콘덴서(C3)와 제 1, 2 버랙터다이오드(28, 29)의 전체용량은 거의 콘덴서(C3)의 용량이 되고, 실질상 제 1, 2 버랙터다이오드(28, 29)의 용량은 무시할 수 있다.In FIG. 2 (b), when receiving a low frequency, the inductance L2 is large and the capacitances of the first and second varactor diodes 28 and 29 become large, so that the capacitor C3 and the first and second burrs are large. The total capacity of the varactor diodes 28, 29 is almost the capacity of the capacitor C3, and the capacity of the first and second varactor diodes 28, 29 can be ignored.

이것에 대하여 높은주파수를 수신할 경우에는 인덕턴스(L2)가 작고 또 제 1, 2 버랙터다이오드(28, 29)의 용량이 작아지기 때문에 콘덴서(C3)와 제 1, 2 버랙터다이오드(28, 29)의 전체용량은 작아진다. 여기서 예를 들어 콘덴서(C3)의 용량이 4pF정도이며, 제 1, 2 버랙터다이오드(28, 29)의 용량이 4∼40pF의 범위에서 가변이고 최소치(4pF)의 경우에는 콘덴서(C3)와 제 1, 2 버랙터다이오드(28, 29)의 전체용량은 2pF정도가 된다.On the other hand, when receiving a high frequency, the inductance L2 is small and the capacities of the first and second varactor diodes 28 and 29 become small, so that the capacitor C3 and the first and second varactor diodes 28, The total capacity of 29) becomes small. Here, for example, the capacity of the capacitor C3 is about 4pF, and the capacity of the first and second varactor diodes 28 and 29 is variable in the range of 4 to 40pF, and in the case of the minimum value 4pF, the capacitor C3 and The total capacity of the first and second varactor diodes 28, 29 is about 2pF.

따라서 이미지트랩주파수를 최저주파수로부터 최고주파수까지의 범위의 동조주파수를 따라 동시에 변화시킬 수 있기 때문에 이미지트랩주파수의 가변범위를 넓게할 수 있음과 동시에 목적으로 하는 이미지주파수에 이미지트랩주파수를 용이하게 맞출 수 있다.Therefore, the image trap frequency can be simultaneously changed along the tuning frequency from the lowest frequency to the highest frequency, so that the variable range of the image trap frequency can be widened and the image trap frequency can be easily adjusted to the desired image frequency. Can be.

이상 설명한 바와같이 본 발명에 의하면, 이미지트랩용 콘덴서에 대하여 버랙터다이오드를 추가하여 수신주파수에 따라 버랙터다이오드의 용량을 변화시키도록 하였기 때문에 콘덴서의 용량을 비교적 크게 하여도 높은주파수의 수신시에 콘덴서와 버랙터다이오드의 전체용량을 작게 할 수 있고 따라서 이미지트랩의 주파수의 가변범위를 넓게 할 수 있음과 동시에 목적으로 하는 이미지주파수에 이미지트랩주파수를 용이하게 맞출 수 있다.As described above, according to the present invention, since a varactor diode is added to the image trap capacitor to change the capacity of the varactor diode according to the reception frequency, even when the capacitor capacity is relatively high, The total capacitance of the capacitor and the varactor diode can be made small, so that the variable range of the frequency of the image trap can be widened and the image trap frequency can be easily matched to the desired image frequency.

Claims (1)

동조용 인덕턴스(L2) 및 제 1 버랙터다이오드(28)의 직렬회로에 대하여 이미지트랩용 콘덴서(C3) 및 제 2 버랙터다이오드(29)의 직렬회로를 병렬로 접속하고, 상기 제 1, 제 2 버랙터다이오드에 공통의 동조용 전압을 인가하고 이들의 용량을 변화시킴으로써 각각 동조주파수와 이미지트랩주파수를 변화시키는 것을 특징으로 하는 텔레비젼튜너의 입력회로.The series circuits of the image trap capacitor C3 and the second varactor diode 29 are connected in parallel to the series circuit of the tuning inductance L2 and the first varactor diode 28. 2. An input circuit of a television tuner characterized by varying the tuning frequency and the image trap frequency by applying a common tuning voltage to the varactor diodes and changing their capacitance.
KR1019970013895A 1996-04-17 1997-04-16 Input circuit of television tuner KR100243838B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP8095487A JPH09284157A (en) 1996-04-17 1996-04-17 Tuner provided with distribution circuit
JP8-095487 1996-04-17

Publications (2)

Publication Number Publication Date
KR970073038A KR970073038A (en) 1997-11-07
KR100243838B1 true KR100243838B1 (en) 2000-02-01

Family

ID=14138970

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019970013895A KR100243838B1 (en) 1996-04-17 1997-04-16 Input circuit of television tuner

Country Status (6)

Country Link
JP (1) JPH09284157A (en)
KR (1) KR100243838B1 (en)
CN (1) CN1164795A (en)
DE (1) DE19715956C2 (en)
GB (1) GB2312345A (en)
MX (1) MX9702782A (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3592160B2 (en) 1999-11-25 2004-11-24 アルプス電気株式会社 Tuner double tuning circuit
WO2003065580A1 (en) * 2002-02-01 2003-08-07 Koninklijke Philips Electronics N.V. Television tuner and printed circuit board used therein
JP3675438B2 (en) * 2002-10-31 2005-07-27 松下電器産業株式会社 High frequency receiver
JP3096170U (en) * 2003-02-27 2003-09-05 アルプス電気株式会社 Television tuner input circuit
JP3097064U (en) * 2003-04-09 2004-01-15 アルプス電気株式会社 Input tuning circuit
DE10330449B3 (en) * 2003-07-05 2005-02-24 Daimlerchrysler Ag Camshaft adjuster for internal combustion engine has stator and first thrust washer bounding adjuster towards cam frictionally joined to camshaft by cylindrical surface
US7936235B2 (en) 2005-06-09 2011-05-03 Telefonaktiebolaget L M Ericsson (Publ) Method to increase the tuneability of varactors
CN101179677B (en) * 2006-11-08 2011-12-14 奇景光电股份有限公司 Television tuner and manufacturing method thereof

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6352510A (en) * 1986-08-22 1988-03-05 Toshiba Corp Electronic tuner
US4835608A (en) * 1988-05-31 1989-05-30 Zenith Electronics Corporation Image trap filter circuit
JPH0352323A (en) * 1989-07-19 1991-03-06 Matsushita Electric Ind Co Ltd Electronic tuner
US5054117A (en) * 1989-08-01 1991-10-01 Zenith Electronics Corporation Tunable UHF filter for switchable VHF/UHF receiver
JP3053150B2 (en) * 1993-02-26 2000-06-19 アルプス電気株式会社 TV tuner input tuning circuit

Also Published As

Publication number Publication date
CN1164795A (en) 1997-11-12
DE19715956C2 (en) 2003-08-14
GB2312345A (en) 1997-10-22
MX9702782A (en) 1998-04-30
JPH09284157A (en) 1997-10-31
DE19715956A1 (en) 1997-11-06
KR970073038A (en) 1997-11-07
GB9707390D0 (en) 1997-05-28

Similar Documents

Publication Publication Date Title
KR19990007997A (en) Tunable Interstage Filters
US6064866A (en) Switchable bandpass filter for a multiband tuner
US20050118968A1 (en) Double conversion tuner
US5376907A (en) High-frequency tunable filter
KR100243838B1 (en) Input circuit of television tuner
US7106149B2 (en) Switchable tuneable bandpass filter with optimized frequency response
US4835608A (en) Image trap filter circuit
US7609134B2 (en) Variable tuning circuit using variable capacitance diode and television tuner
US4628540A (en) Tuning arrangement having a substantially constant frequency difference between an RF-circuit and an oscillator circuit
KR100286474B1 (en) Antenna tuning circuit
MXPA97002782A (en) Entry circuit for a televis tuner
US6734761B2 (en) Radio-frequency input stage
US4646360A (en) Constant bandwidth RF filter with improved low frequency attenuation
KR930006547Y1 (en) Variable if filter
JP3146916B2 (en) Electronic tuner input circuit
EP0920735B1 (en) Receiver with a tunable parallel resonant circuit
KR100406353B1 (en) Switching circuit for input tuning in television tuner
JP3103017U (en) Television tuner
JPS607853B2 (en) input tuning circuit
JP3050884B2 (en) Electronic tuner input circuit
KR0168954B1 (en) Tuner filter circuit of satellite broadcasting tuner
JP3127711B2 (en) Electronic tuner
WO2001084709A1 (en) Bandswitichable double tuned circuit
JPH06204803A (en) Electronic tuner
JPS6056328B2 (en) input tuning circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20061031

Year of fee payment: 8

LAPS Lapse due to unpaid annual fee