JPS6030171A - Hybrid integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to use a package formed in a small type, to meet standarized requirements, and to be used for an ultraviolet rays erasable programmable read-only memory (UV-EPROM) by a method wherein the ultraviolet rays transmitting window of the package of the UV-EPROM is enabled to be covered with a printed substrate equipped with other integrated circuit elements. CONSTITUTION:A UV-EPROM is mounted on a leadless chip carrier 14 together with a decoder, an inverter and a gate circuit, the carrier is equipped on a printed substrate 13, a CMOS static RAM is mounted on a flat package 16, the package is equipped on a printed substrate 15, and the substrate 13 and the substrate 15 are connected electrically to a flexible printed-substrate 17. Data are written to the memory elements of the UV-EPROM, the substrate 15 is folded back on the substrate 13, and the ultraviolet rays transmitting window of the package of the UV-EPROM is covered with the flat package 16 to shield ultraviolet rays. The pin function and pin width of lead terminals 18 are made to size specified by the JEDEC to enable to use an IC and a PROM writer for a wide use.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an ultraviolet erasable read-only memory (hereinafter abbreviated as UV-EPROM) that is electrically connected to other integrated circuit elements and converted into an IA. It relates to a hybrid integrated circuit device constructed.

[Technical Background of the Invention] Uv-E PROM is capable of erasing information stored in memory cells by irradiating the integrated circuit chip with ultraviolet rays from the outside, and then storing new information again. It is configured so that it can be stirred.

Figure 1 shows <-(7)J: U'j U V E P
It shows ROM 1, and this UV-EP I
'< OM In 1, an ultraviolet transmitting window 4 is provided on the upper surface of the package 3 housing the integrated circuit chip 2, and the integrated circuit deep 2 inside the package 3 is transmitted through the transmitting window 4.
It becomes cold when irradiated with ultraviolet IF 5. The ultraviolet light transmitting window 41J is made of quartz glass, sapphire plate, transparent alumina, etc. At times, an ultraviolet light shielding sticker (not shown) is pasted on the ultraviolet light transmitting window 4 so that the information stored in the memory cells can be transmitted. It is protected. The master of this information then peels off the ultraviolet ray shielding seal and irradiates strong ultraviolet rays from the "C ultraviolet transmitting window 1."

By the way, in UV-EPROM, there is a geodic (jo
int electron device engine
earing council: JEDEC
) Packages other than those specified by M < are rarely used in reality. However, due to the need to miniaturize electronic devices, there is a demand for mounting elements on small leadless chip carriers or directly mounting paired chips, and UV-E I) ROM is also being mounted on hybrid integrated circuit devices. There was a strong desire to use it.

[Problems with the Background Art] However, when a UV-EPROM is mounted on a hybrid integrated circuit device and used in a hybrid integrated circuit device, it is sometimes necessary to update the information written in the memory cells of the UV-EPROM. Therefore, the UV-transparent window of the package with uv −E p + Okan() must not be. Also, U
It is desirable to fit the V-EPROM into an 11-element integrated circuit, and the size of the memory element of the UV-EPROM is small.
There is a drawback that the I-' ROM Lake 11) eraser cannot be used to erase the data.

Furthermore, if it is integrated with other integrated circuit elements such as UV-E PROM, it takes up a large space in terms of plane, making it difficult to downsize. This was done in response to the conventional constraints, and by hybridizing U'V-E PROM and other integrated circuit elements, it was possible to create a
The purpose of the present invention is to provide a Sawanari INi circuit device that can use a package standardized in C, is compact, and has a wide range of applications.

[Summary of the Invention] That is, the present invention provides a hybrid integrated circuit device in which other integrated circuit elements are electrically connected to and integrated with an ultraviolet-erasable read-only device having an ultraviolet-transmitting window in the package. 1 out of the above votes! +l Erase type read only
The memory and other integrated circuit elements are mounted on separate printed circuit boards, and the printed circuit board on which the ultraviolet-erasable read-only memory is mounted and the printed circuit board on which other integrated circuit elements are mounted are combined into a flexible printed circuit board c. 'Hybrid integration characterized in that the printed circuit board electrically connected and mounted with the other integrated circuit element covers the ultraviolet transmitting window of the package of the ultraviolet erasable read-only memory so as to cover 1q. It is a circuit device.

[Embodiments of the Invention] The details of the present invention will be explained below with reference to the drawings and an embodiment of the invention.

FIG. 2 is a block diagram without showing an example of a circuit used in an embodiment of the hybrid integrated circuit device according to the present invention, and FIG.
4 is a side view C showing an embodiment of a hybrid integrated circuit device according to the present invention in which the circuit example of FIG. 2 is implemented.

In FIGS. 2 to 4, a3, numerals 6 to 8 represent the bin h CM OS study RA IVI in 64,
The CMOS static RAMs 6 to 8 are mounted on a flat package 16. In addition, the first issue 9 was a 64-bit UV-EPROM, and a (7) UV-EPR
The OM9 is mounted on the leadless chip carrier i' 14 along with other circuit elements such as a decoder 10, an inverter 11, and a gate circuit 12. The CMOS static RAM 67-8 and UV-E PRO
Each data input terminal A o "□AI2 of M9 is connected to the data signal line AC.2I.

In addition, each chip enable signal input terminal CE+ of CMOS static RAM 6 to 8 is connected to the decoder 1.
0 is connected to the output J terminal YO"-Y2. Also, the CMOS study RAM (3 to 8 chip enable signal input) j terminal CE2 is commonly connected to the chip enable signal line CE2. Roughly speaking, each read/write signal input terminal R/W of the CMOS study 1 memory AM6-8 is connected to the signal line 1</W> to the read/write 1.
Input horn signal terminals I/O+ to I/O of AM 6-8 and UV-EP ROM 9.

are connected to a common input signal line I10.

Roughly CMOS static RAM 6~F3
, and the output 1 to enable signal terminal OE of the UV-EP ROM 9 are connected to a common output enable signal line OE. Each CMOS static RAM 6 to 8J5cL of the decoder 10: OUV
-Chip select signal input terminal A to select EpRoM9
+, A2 are chip select r-4g line A1, respectively.
Connected to A2.

Furthermore, the enable signal input terminal IENB that enables the operation of the data processor 10 is connected via the inverter 11 to the program control signal line PGM that enables the writing 2J of the UV-EPROM 9. There is.

This program control signal line PGM is connected to the program control signal input terminal PG IVI of the program control signal input terminal PG IVI and the chip enable signal input terminal CF of the program OIVI9. I'm there. Further, one input terminal of the gate 12 is connected to the output terminal Y3 of the decoder 10.

The operation of this example circuit constructed in this manner will be described next.

First, each CMOS study RAM 6~8LJ
24, K by l-RAM is formed 4^), and only one CMOS static RAM is selected to operate according to the output signal of the card 10. Also, U
In the V-lx P ROM 9, the output signal i of the decoder 10 is passed through the circuit 1 to the circuit 12 to the circuit 12 to control the operation state r. Boot select 1 input to decoder 10 to dip select 1 on signal line AtXA2
・The signal causes the output terminal Yo”Y3 of this decoder 10 to
When only one of the outputs reaches the O level, it is connected to the output terminal j that has reached the O level.
is working.

However, when the program control signal on the program control line PGM is at 0 level (b), the enable signal input terminal ENB of the decoder 10 becomes a level by the inverter 11, and while this enable signal input terminal ENB is at a level, the output YO .about.Y3 is kept at a level regardless of the voltage levels of the signal input terminals A+ and A2 to the dipstick 1. Therefore, the decoder 10 stops selecting each integrated circuit element in this state.

In this state, the program control signal on the program control signal line PGM is at the O level, so the program control signal input terminal 1) of the UV-EPROM 9 is set to the O level via the circuit 1-2. Saved, UV-EPRO
M9 is in a writable state.

However, in this state, the output terminal Yo'' of the decoder 10
Y3 is Lebel, each CMOS static RAM6~8
The chip enable signal input terminals CE+ are all level, and each CMOS static RAM 6 to 8 has stopped its operation, while the U V-E P ROM
9 deep enable creed 3 input terminals CE and 1]
Since the program control signal input terminal PGM is kept at the O level by the program control signal on the program control signal line PGM transmitted through the circuit
Only OM9 is in a state where rounding is possible.

Accordingly, data can be written into the memory element of the CUV-I3P ROM 9 by the PROM writer cap.

In this way, when the data gl input into the UV-EPROM 9 is completed and the program control signal on the program control signal line PGM becomes level at 1 (-4*), the inverter 1
Enable signal input for decoder 10 via terminal E)
The operation of the C1 decoder 10 is enabled when NB becomes O level, and the CMOS static RAM 6 is activated by the depth select signal on the chip select signal lines A+ and A2.
-81, t, , tuv -E, any one integrated circuit element from PROM9 is selected, and the data is read from the selected integrated circuit element or the data is read from the CMOS static RAMs 6 to 8. IB will also be included.

As shown in FIGS. 3 and 4, the circuit of this embodiment has U
The V E P ROM 9 J3, decoder 10, inverter 11, and gate circuit 12 are mounted on a trench chip carrier 14 and mounted on a printed circuit board 13. Further, CMOS devices 1<AM6-8 are mounted on a flat package 16 and attached to a printed circuit board '15. The printed circuit board 13 and the printed circuit board 15 (also electrically connected by a flexible printed circuit board 17) are lead terminals 18 for the purpose of connecting the circuit board 1 to the circuit board 13 with an external circuit. RO
Enables the use of M writers.

J in Figure 2: Each leadless depth carrier 14
After writing data to the memory module of UV41) ROM9 with the flat package 16 attached to the board 13.15, as shown in FIG.
The UV-E PROM 9 is folded back onto the substrate 13, and the UV-transmitting window of the package of the UV-E PROM 9 mounted in the leadless chip carrier 14 is covered with the flat package 16 to block the UV rays. At this time, the flan 1 to the package 16 and the leadless depth carrier 14 are pasted with adhesive.

In this way, the package 16 and the dress chip carrier 14 are attached to the flange 1.
It is covered with a flat package 16 in which the MOS study RAMs 6 to 8 are mounted and sealed to shield light from the outside. At this time, in order to completely block light and strengthen the mechanical strength, if the entire C circuit is backed with black Evo 4-sheet resin in the pasted state shown in Figure 4, the whole C one-depth Hybrid integrated circuit device “Ritoshi”
C can be used.

FIG. 5 is a side view showing another embodiment of the hybrid M5 product circuit device according to the present invention. In this example, J5-C is UV
-Fl) This is a case in which a ROM is mounted in a package and a leadless deep carrier is used, and DIP19 of the 7j specification specified by JTODEC is used.

In this case, UV-13P f< OM J13[]1
Implemented in DIP19 of Zo01shi 4 drugs, this DIP
19 into the IC socket 21. This IC socket [
-21 is electrically connected to the flexible printed circuit board 22 and the reprinted circuit board 20, and a flat package 24 mounting a CMOS static RAM is mounted on this printed circuit board 20.

#1 f”r 23 is an output lead terminal of the IC socket 21.

If the TUV-EPROM is installed on the DIPl 9, the UV-EPR01V+ user can be transferred to a commercially available PROM writer or eraser 2.

Then, in the state shown in FIG. 5, after writing the data into the memory element of the ROM, bend the flexible print 1 to the nest plate 22 in the same manner as shown in FIG. Cover over IC socket 21, flange 1
- The surfaces of the package 24 and the DIPs 1"' and 9 are adhered with adhesive to seal the ultraviolet light transmitting window of the rUV-EPROM.

In addition to the circuit example shown in FIG. 2, for example, a CIvl OS static R is installed in the flat package 24 shown in FIG.
A one-step microcomputer with AM and I10 controllers is installed, and the A operating system of the microcomputer is installed in the UV-EPROM.
If you avoid memorizing 8, you can compose a big song like (11+) with a piggyback microcomputer.

[Effects of the Invention] In the integrated phase integrated circuit device according to the present invention, the chip mounted with LIV-E F) ROM and the chip mounted with other integrated circuit elements are printed separately. Connect each pudding 1 to the board electrically with blue coating on the board,
After writing data to the memory element of the OM, the board on which other integrated circuit elements are mounted is folded back onto the board on which the UV-EPROM is mounted, and the UV-transmitting window is sealed. l) By mounting the ROM in a hybrid integrated circuit device, it becomes possible to write and erase data into and from the UV-EPROM using a commercially available l) ROM writer and eraser.

Furthermore, there is no longer a need to prepare a separate seal for blocking UV light, and when debugging a circuit, the circuit is spread out flat, and after the debugging operation is completed, it is necessary to use a UV shield before incorporating it into equipment. It becomes possible to bend the pull-printed circuit board and paste/cover other integrated circuit elements such as UUV-EPROM, making it easy to deback the circuit, and also to improve the performance of electronic equipment such as this) resultant circuit device. When mounting \, it is also possible to obtain the effect of increasing the degree of planar mounting closure.

[Brief explanation of drawings]

Fig. 1 shows a conventional hybrid integrated circuit device from a tlA perspective, and Fig. 2 shows a conventional hybrid integrated circuit device.
The figures show an example of a circuit implemented in a hybrid integrated circuit device according to the present invention. FIG. 5 is a side view of another embodiment of the 11N integrated circuit neck according to the present invention. 1.9...UV-1 three[tsu[R()~12...
......Integrated circuit depth 3...
・・・・・・Package 4・・・・・・・・・・・・Ultraviolet transmission window 5・・・・・・・・・Ultraviolet rays 6 to 8・・・・・・CMOS static RAM 10・
......Decoder 13.15.20...
・Printed circuit board 14...Leadless chip carrier 16...Flannel 1 to package 17... Flexible pudding 1-
Basic handling 18.21...Lead terminal 19...DIP 21......IC socket 1-Representative patent attorney Satoshi Suyama - Chapter Figure 1, Figure 2 (Mu)

Claims (1)

[Claims] (1) In a hybrid integrated circuit device comprising an ultraviolet erasable read-only memory whose package has an ultraviolet transmitting window and other integrated circuit elements electrically connected and integrated, the ultraviolet erasable read-only memory and other integrated circuit elements are mounted on separate printed circuit boards, and the printed circuit board on which the ultraviolet erasable read-only memory is mounted and the printed circuit board on which the other integrated circuit elements are mounted are combined into a flexible printed circuit board. and electrically connected to each other so that the printed circuit board mounted with the other integrated circuit element can cover the ultraviolet light transmitting window of the pancage of the ultraviolet erasable read-only memory described in nU. circuit device.