JPS6029069A - Error detection/correction encoding system - Google Patents

Error detection/correction encoding system

Info

Publication number
JPS6029069A
JPS6029069A JP11121983A JP11121983A JPS6029069A JP S6029069 A JPS6029069 A JP S6029069A JP 11121983 A JP11121983 A JP 11121983A JP 11121983 A JP11121983 A JP 11121983A JP S6029069 A JPS6029069 A JP S6029069A
Authority
JP
Japan
Prior art keywords
circuit
encoder
time base
stage
error detection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11121983A
Other languages
Japanese (ja)
Inventor
Keiichi Kameda
亀田 啓一
Kenichi Takahashi
賢一 高橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP11121983A priority Critical patent/JPS6029069A/en
Publication of JPS6029069A publication Critical patent/JPS6029069A/en
Pending legal-status Critical Current

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  • Error Detection And Correction (AREA)

Abstract

PURPOSE:To shorten decoding time by using a multiple-stage encoder and time base control circuit so as to conduct reverse operation of time base operation, which is to be conducted after the first-stage encoder, before it. CONSTITUTION:Input signal data series to be encoded enters a time base operation circuit 9. The circuit 9 conducts reverse operation of the operation which is conducted by a time base operation circuit 11. An encoder 10 adds error detection/correction code which is to be processed in the circuit 11. However, this reverse operation is conducted beforehand, and therefore this output is input signal data series as it is. An encoder 12 adds the second-stage error detection/ correction codes, and finally a time base control circuit 13 processes, transmits and records them. On the other hand, signals which are transmitted in such form are processed by a time base control circuit 14 which conducts reverse operation of the circuit 13, and corrected by a decoder 15. At a point of this time, unless errors exist, data series can be outputted as it is. Consequently, there is no necessity of conducting final stage time base operation and data are outputted in a short time.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、ディジタルデータの伝送嗜記録において発生
するデータ誤りに対処するために用いる誤り検出訂正符
号化方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an error detection and correction encoding method used to deal with data errors that occur in the transmission and recording of digital data.

従来例の構成とその問題点 近年、ディジタルデータの伝送や記録に際し、その伝送
系、記録媒体の不完全性により発生するデータ誤りに対
処し、システムの信頼性を向上させるために、誤り検出
訂正符号が盛んに用いられている。これは符号器におい
て、一連のデータ列に誤り検出訂正符号を付加して伝送
・記録を行ない、復号器においてはその符号よりデータ
の訂正や補正を行なって出力するものである。この符号
化方法の中に多重符号化方法といわれるものがある。こ
れは符号器を多段に構成し、それらの間に時間軸操作を
施し符号化する方法であり、それぞれの符号器は単純な
構成にすることができ、効率よく高い訂正能力を得るこ
とができる。
Conventional configurations and their problems In recent years, when transmitting or recording digital data, error detection and correction techniques have been developed to deal with data errors that occur due to imperfections in the transmission system or recording medium, and to improve system reliability. Symbols are widely used. In this method, an encoder adds an error detection and correction code to a series of data strings for transmission/recording, and a decoder corrects or corrects the data using the code and outputs the result. Among these encoding methods, there is one called a multiple encoding method. This is a method of configuring encoders in multiple stages and performing encoding by performing time axis operations between them.Each encoder can have a simple configuration and can efficiently obtain high correction ability. .

以下、図面を参照しながら、従来の多重の誤り検出訂正
符号化方法について説明する。第1図は従来の2重符号
化方法の符号化装置のブロック図であり、第2図は同じ
く復号化装置のブロック図であり、1,3は符号器、6
,8は復号器、2゜4、 5. 7は時間軸操作回路で
ある。
Hereinafter, a conventional multiplex error detection and correction encoding method will be described with reference to the drawings. FIG. 1 is a block diagram of an encoding device using a conventional dual encoding method, and FIG. 2 is a block diagram of a decoding device, in which 1 and 3 are encoders, 6
, 8 is a decoder, 2°4, 5. 7 is a time axis operation circuit.

以上のように構成された2重符号化方法の符号化装置及
び復号化装置についてその動作を以下に説明する。デー
タ列はまず符号器1で第1の誤り検出訂正符号が付加さ
れる。その後時間軸操作回路2でデータの並べかえを行
ない、異なるデータ列とし、符号器3で第2の誤り検出
訂正符号が付加され、時間軸操作回路4でもう一度デー
タ列の並べかえを行ない、信号を伝送・記録する。
The operation of the encoding device and decoding device for the dual encoding method configured as described above will be described below. First, a first error detection and correction code is added to the data string by an encoder 1. After that, the time axis manipulation circuit 2 rearranges the data to create a different data string, the encoder 3 adds a second error detection and correction code, and the time axis manipulation circuit 4 rearranges the data sequence once again to transmit the signal. ·Record.

以上が符号化装置の動作であシ、復号化装置においては
、上記の逆処理を行なう。すなわち、記録媒体からの再
生信号あるいは伝送されてきた信号は、時間軸操作回路
4の逆操作である時間軸操作回路6でデータ列の並べが
えを行なった後、復号器6で第1段目の復号動作が行な
われる。これは符号器3で付加された誤り検出訂正符号
を用いて行なわれる。次に時間軸操作回路7で符号化装
置における時間軸操作回路2の逆操作が施され、復号器
8において、符号器1で付加された誤り検出訂正符号を
用いた復号動作が行なわれる。
The above is the operation of the encoding device, and the decoding device performs the inverse processing described above. That is, the reproduced signal from the recording medium or the transmitted signal is rearranged in the data string by the time axis operation circuit 6, which is the reverse operation of the time axis operation circuit 4, and then the data sequence is rearranged by the decoder 6 at the first stage. A second decoding operation is performed. This is done using the error detection and correction code added by the encoder 3. Next, the time axis operation circuit 7 performs the reverse operation of the time axis operation circuit 2 in the encoding device, and the decoder 8 performs a decoding operation using the error detection and correction code added by the encoder 1.

以上は2重符号化方法について説明を行なったが3重以
上についても同様に構成することができ、符号器と時間
軸操作回路の縦続接続で符号化装置が、復号器と時間軸
操作回路との縦続接続で復号化装置が構成される。
The above description has been about a double encoding method, but the same configuration can be applied to triple or more encoding methods. The decoding device is configured by cascading the .

しかしながら、上記のような符号化方法においては、時
間軸操作を含むため、復号側において、復号信号を得る
に時間を要し、特に記録媒体中の特定のデータを取り出
す際に問題となる。また、記録媒体や伝送系が良好であ
り、データ誤りのほとんどが最終段の復号までに訂正さ
れる場合、データが正しいにもかかわらず、最終段の時
間軸操作を施さないと出力できないという問題点も有し
ていた。
However, since the above encoding method involves time axis manipulation, it takes time on the decoding side to obtain a decoded signal, which poses a problem particularly when extracting specific data from a recording medium. In addition, if the recording medium and transmission system are in good condition and most data errors are corrected before decoding in the final stage, there is a problem that even if the data is correct, it cannot be output unless time axis manipulation is performed in the final stage. It also had points.

発明の目的 本発明の目的は、復号に要する時間を短縮でき、必要な
らば最終段の時間軸操作回路と復号器の処理に施す時間
軸操作の逆操作を初段の符号器の前に施すようにして、
多段の符号器と時間軸操作回路を使用するようにしたも
のであり、これにより、最終段の時間軸操作を施す前の
時点で、出力データの並び方にすることができるもので
ある。
Purpose of the Invention The purpose of the present invention is to shorten the time required for decoding, and if necessary, perform the reverse operation of the time axis operation performed on the final stage time axis manipulation circuit and decoder processing before the first stage encoder. and then
This uses a multi-stage encoder and a time-base manipulation circuit, which allows the arrangement of output data to be adjusted before the final-stage time-base manipulation is performed.

実施例の説明 以下、本発明の実施例について、図面を参照しながら説
明する。
DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments of the present invention will be described with reference to the drawings.

第3図は本発明を2重符号化に適用した実施例における
誤り検出訂正方法を用いた符号化装置のブロック図、第
4図は同じく復号化装置のブロック図を示すものである
。両図において、10.12は符号器、15.17は符
号器、9,11,13゜14.16は時間軸操作回路、
18は誤り訂正制御器である。また第6図は、第3図お
よび第4図のブロック図の各部における符号語の構成を
示す図である・ 4゜ 以下、本実施例の誤り検出訂正符も法についてその動作
を説明する。まず、符号化装置について説明する。符号
化されるべき入力信号のデータ列は時間軸操作回路9へ
入る。ここでは第5図(八に示すようにW1〜W6の6
ワードで1つの単位と考え、以下誤り検出訂正のための
符号が付加される場合を考える。時間軸操作回路9では
、第1段目の符号器の後に施す時間操作の逆操作、すな
わちこの例では時間軸操作回路11が施す操作の逆操作
を施す。この時点でのWl を含む符号語は第5図(B
)に示す形となる。
FIG. 3 is a block diagram of an encoding apparatus using an error detection and correction method in an embodiment in which the present invention is applied to double encoding, and FIG. 4 is a block diagram of a decoding apparatus. In both figures, 10.12 is an encoder, 15.17 is an encoder, 9, 11, 13°, 14.16 is a time axis operation circuit,
18 is an error correction controller. FIG. 6 is a diagram showing the structure of code words in each part of the block diagrams of FIGS. 3 and 4. 4. Below, the operation of the error detection and correction code method of this embodiment will be explained. First, the encoding device will be explained. The data string of the input signal to be encoded enters the time axis manipulation circuit 9. Here, 6 of W1 to W6 as shown in Figure 5 (8)
A word is considered to be one unit, and below we will consider the case where a code for error detection and correction is added. The time axis manipulation circuit 9 performs the reverse operation of the time manipulation performed after the first-stage encoder, that is, the reverse operation of the operation performed by the time base manipulation circuit 11 in this example. The codeword containing Wl at this point is shown in Figure 5 (B
).

次に符号器1oで誤シ検出訂正符号が付加され、ここで
はPl の1ワードの付加され、第6図qに示す形とな
る。次に時間軸操作回路11で処理されるが、この逆操
作が前もって施こされているので、この出力においては
第5図p)に示すようにW1〜W6について入力信号の
データ列そのままとなっている。その後、符号器12で
第2段目の符号が行なわれ、この例では第5図(E)に
示す構成となり、最後に時間軸操作回路13で処理され
、第5図(F)の構成となり、伝送・記録される。
Next, an error detection and correction code is added in the encoder 1o, in which one word of Pl is added, resulting in the form shown in FIG. 6q. Next, it is processed by the time axis operation circuit 11, but since this reverse operation has been performed in advance, the data string of the input signal is unchanged for W1 to W6 in this output, as shown in Figure 5 p). ing. After that, the encoder 12 performs the second stage of encoding, resulting in the configuration shown in FIG. 5(E) in this example.Finally, the time axis operation circuit 13 processes the code, resulting in the configuration shown in FIG. 5(F). , transmitted and recorded.

一方、第4図に示す復号化装置の動作について説明する
。第6図(F′)に示す形で送られてくる信号は、時間
軸操作回路13の逆操作を施す時間軸操作回路14で第
5図(E)の形となり、第1段目の復号器で誤り検出訂
正動作を行ない、第6図pの構成となる。この時点でデ
ータW1〜W6は入力信号のデータ列と同じであるので
、誤りが存在しなければそのまま出力することができる
。なお、誤りが存在する場合には、時間軸操作回路11
の逆操作を施す時間軸操作回路16での操作の後、復号
器17で第2段目の誤り訂正動作を行ない、誤り訂正制
御器18で、最終データ列に対する訂正を行なうように
することができる。
On the other hand, the operation of the decoding device shown in FIG. 4 will be explained. The signal sent in the form shown in FIG. 6 (F') becomes the form shown in FIG. The device performs error detection and correction operations, resulting in the configuration shown in FIG. At this point, the data W1 to W6 are the same as the data string of the input signal, so if there are no errors, they can be output as they are. Note that if there is an error, the time axis operation circuit 11
After the operation in the time axis operation circuit 16 that performs the inverse operation, the decoder 17 performs the second stage error correction operation, and the error correction controller 18 performs correction on the final data string. can.

以上のように本実施例によれば、入力信号に第一段目の
後に施す時間軸操作の逆操作を前もって施すことにより
、復号側において、第2段目の時間軸操作を施す前に、
入力信号と同じデータ列の出力を得ることを実現してい
る。なお、上記実施例においては、2重符号化について
述べたが、3重以上の多重符号化においても同様に扱え
ることは言うまでもない。
As described above, according to this embodiment, by performing the inverse operation on the input signal in advance to the time axis operation performed after the first stage, on the decoding side, before performing the second stage time axis manipulation,
This makes it possible to obtain an output with the same data string as the input signal. In the above embodiment, double encoding has been described, but it goes without saying that triple or more multiple encoding can be handled in the same way.

発明の効果 以上の説明から明らかなように、本発明は初段の符号器
の後に゛施す時間軸操作の逆操作を初段の符号器の前に
施すようにして、多段の符号器と時間軸操作回路を使用
するようにしているので、復号側において、最終段の時
間軸操作の前の時点で入力信号のデータ列と同じとなり
、誤りが存在しなければその時点で出力信号を得られる
という優れだ効果が得られるものである。特に、記録媒
体にデータが記録され、特定のデータを出力する場合に
おいて、最終段の時間軸操作回路を施す必要がなく、短
時間にデータを出力できるという効果が得られるもので
ある。
Effects of the Invention As is clear from the above explanation, the present invention performs the inverse operation of the time axis operation performed after the first stage encoder before the first stage encoder, thereby combining multistage encoders and time axis operations. Since the circuit is used, on the decoding side, the data string becomes the same as the input signal at the point before the time axis operation in the final stage, and if there is no error, the output signal can be obtained at that point. It is something that can be effective. Particularly, when data is recorded on a recording medium and specific data is to be output, there is no need to provide a final-stage time axis manipulation circuit, and the advantage is that the data can be output in a short time.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来の2重符号化の誤り検出訂正符号化方法の
符号化装置のブロック図、第2図は同じく復号化装置の
ブロック図、第3図および第4図は本発明の一実施例に
係る誤り検出訂正符号化方法を採用した符号化装置およ
び復号化装置のブロック図、第6図は第3図および第4
図のブロック図の各部における符号語の構成を示す図で
ある。 9.11,13,14.16・・印・時間軸操作回路、
10.12・・・・・・符号器、15.17・・・・・
・復号器、18・・・・・・誤り訂正制御器。
FIG. 1 is a block diagram of an encoding device of a conventional double-encoding error detection and correction encoding method, FIG. 2 is a block diagram of a decoding device, and FIGS. 3 and 4 are one embodiment of the present invention. A block diagram of an encoding device and a decoding device employing the error detection and correction encoding method according to the example, FIG. 6 is similar to FIGS. 3 and 4.
It is a figure which shows the structure of the code word in each part of the block diagram of a figure. 9. 11, 13, 14. 16... mark/time axis operation circuit,
10.12... Encoder, 15.17...
- Decoder, 18...Error correction controller.

Claims (1)

【特許請求の範囲】[Claims] 初段の符号器の後に施す時間軸操作の逆操作を初段の符
号器の前に施すようにして、多段の符号
A multi-stage code is created by applying the inverse of the time axis operation performed after the first-stage encoder before the first-stage encoder.
JP11121983A 1983-06-20 1983-06-20 Error detection/correction encoding system Pending JPS6029069A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11121983A JPS6029069A (en) 1983-06-20 1983-06-20 Error detection/correction encoding system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11121983A JPS6029069A (en) 1983-06-20 1983-06-20 Error detection/correction encoding system

Publications (1)

Publication Number Publication Date
JPS6029069A true JPS6029069A (en) 1985-02-14

Family

ID=14555540

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11121983A Pending JPS6029069A (en) 1983-06-20 1983-06-20 Error detection/correction encoding system

Country Status (1)

Country Link
JP (1) JPS6029069A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003257A (en) * 1988-06-17 1991-03-26 Nissan Motor Company, Ltd. Digital speedometer displaying of measured object without flickering of least significant digit of displayed value

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5003257A (en) * 1988-06-17 1991-03-26 Nissan Motor Company, Ltd. Digital speedometer displaying of measured object without flickering of least significant digit of displayed value

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