JPS6029029A - Analog-digital converter - Google Patents

Abstract

PURPOSE:To obtain a high speed A/D converter by providing the A/D converter for the number of sample holding circuits in a serial/parallel A/D converter so as to increase the transmission speed of the first stage A/D conversion - D/A conversion circuit. CONSTITUTION:The sample holding circuits 21, 22 sample and hold an analog signal 100 at a half period different from each other, A/D convert (4 and 5) the higher bit of the signal 100, outputs the result from a register 42 and gives it to one input terminal of a differential amplifier 1 via a D/A converter 2. An output of the circuits 21, 22 is fed to the other input terminal of the amplifier 1 via an analog switch, the lower bit of the signal 100 is outputted from an amplifier 31, the result is A/D converted (3) and outputted via a register 43. Thus, the high speed serial/parallel A/D conversion is attained by using the A/D converters 4, 5 in place of an analog switch being a cause to delay of propagation.

Description

[Detailed description of the invention] [Field of application of the invention] The present invention relates to a series/parallel AD converter.

[Background of the invention]

BACKGROUND ART Conventionally, there is a series/parallel AD converter (hereinafter abbreviated as ADC) consisting of a plurality of sample-and-hold circuits (hereinafter abbreviated as S/H) and an analog switch (hereinafter abbreviated as ASW). For details, see Japanese Patent Application No. 108348/1983.

An example using two sample-and-hold circuits is shown in FIG. First, the analog signal 100 is sampled by the S/H 21- by the control signal SHI to the S/H, and then held. At that time, the ASW 32 outputs the control signal SA
, the signal of the S/H 21 is output to the first AD converter 4. The first AD converter 4 A/D converts the signal held by the S/H 21 and determines the upper pit. The output is passed through the register 41 and converted into an analog signal by the DA converter 2.

This DA ratio output and the input signal held in the sample hold 21 are selected by the analog switch 31 and input to the subtracter 1, the difference between the two is taken, and it is input to the second AD converter 3. This determines the lower bits.

The key to increasing the speed of this system is to increase the speed at which the sampled and held signal is AD converted by the first AD converter 4 and the DA ratio output of the DA converter 2 is obtained. This configuration has the problem that a signal propagation delay occurs because the output of 8/H21 passes through A8W32, and it takes time until the DA output value is obtained after the sample/hold ends.

[Purpose of the invention]

An object of the present invention is to eliminate such drawbacks and provide a high-speed and stable AD converter.

[Summary of the invention]

The present invention provides a first ADC without using an analog switch.
By using the same number of S/H as the number of S/H and switching the output digitally, a series-parallel type ADC is realized.

[Embodiments of the invention]

The present invention will be explained below using examples. FIG. 2 shows its circuit configuration, and FIG. 3 shows its time chart. First, the S/H 21 samples the analog signal 100 with the logic "1" of the control signal sH1 and holds it with the logic "0". It is assumed that the output of the S/H 21 is connected to the AD converter 5, and AD conversion of the upper bit is performed at the falling edge of the control signal ADZ-1. This AD conversion outlet is connected to the switch 51, and the logic "1" of the control signal MPX is output from the switch 51. This output signal passes through the register 41, becomes upper bit data of the entire AD converter, is inputted to the DA converter 2, is passed through the analog signal again, and is connected to one input of the differential amplifier 1. At this time, the analog switch 31 outputs the signal of the S/H 21 with the logic '1' of the control signal 8B, and the differential amplifier 1
is connected to the other input of The differential amplifier 1 takes the difference between the signal from the analog switch 31 and the signal from the DA converter, and its output is converted into a control signal AD by the AD converter 3.
For example, at the falling edge of 2, AD conversion is performed to lower bit data. Until this time, 8/H21 is holding the data. Now A for the value held in S/H21
D conversion ends.

The S/H 22 samples the analog signal 100 a half cycle later than the S/H 21 and holds it. The AD converter 4 AD converts this into high-order bit data, the control signal MPX of the switch 51 is switched, and the high-order bit data of the A/D converter 4 is then DA-converted, and the analog switch 31
is also switched in the opposite direction and outputs a signal of S/1-122. The differential amplifier 1 takes the difference between them, and the AD converter 3 performs AD conversion on the lower bit data. In this way, while the output of one S/H is AD converted for the upper bits by the corresponding first AD converter, the output of the other S/H is AD converted for the lower bits by the second AD converter. It is possible to increase the speed by using a traveling wave type configuration that performs conversion. Moreover, according to this embodiment, the output of each S/H is directly input to the first AD converter without passing through an analog switch etc.
A digital value switch that can easily operate at high speed switches the digital signal corresponding to the hold value of each S/H, eliminating the propagation delay caused by passing through an analog switch, resulting in higher speeds than conventional methods. can. Furthermore, AD converter ICs are becoming cheaper than analog switches, and have the effect of being realized at low cost.

In the above embodiment, the case where two sets of sample/hold and first AD converters are used is shown, but similarly, the number of S/H,
It is clear that it is possible to increase the number of first AD converters, the number of switching devices, and the number of analog switches, thereby reducing the operating speed of each part.

〔Effect of the invention〕

According to the present invention, a series/parallel type AD converter can be realized without using an analog switch that causes a propagation delay problem, so the speed of the first stage AD-D converter is improved and a faster converter can be realized. In addition, inexpensive ICs can be obtained as multiple AD converters used in the first stage, which not only increases speed, but also
The effect is also significant in terms of economy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional serial-parallel AD converter, FIG. 2 is a block diagram showing an embodiment of the present invention, and FIG. 3 is a timing diagram thereof.

Claims (1)

[Claims] a plurality of sample and hold means for sequentially sampling and holding analog input signals; a plurality of first AD conversion means for converting the outputs of the plurality of sample and hold means into digital signals; calculation means for sequentially converting each output of the AD conversion means into an analog signal and sequentially determining the difference between the analog signal and each output of the sample and hold means; and a calculation means for converting the output of the calculation means into a digital signal. An AD converter comprising: 2 AD converting means.