JPS6028320A - Comparator circuit - Google Patents

Comparator circuit

Info

Publication number
JPS6028320A
JPS6028320A JP58135975A JP13597583A JPS6028320A JP S6028320 A JPS6028320 A JP S6028320A JP 58135975 A JP58135975 A JP 58135975A JP 13597583 A JP13597583 A JP 13597583A JP S6028320 A JPS6028320 A JP S6028320A
Authority
JP
Japan
Prior art keywords
output
comparator
section
circuit
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP58135975A
Other languages
Japanese (ja)
Other versions
JPH0475687B2 (en
Inventor
Masao Hotta
正生 堀田
Kenji Maio
健二 麻殖生
Kotaro Okiguchi
沖口　光太郎
Toshihiko Yokoyama
敏彦 横山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Hitachi Ltd
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP58135975A priority Critical patent/JPS6028320A/en
Publication of JPS6028320A publication Critical patent/JPS6028320A/en
Publication of JPH0475687B2 publication Critical patent/JPH0475687B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/26—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback
    • H03K3/28—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback
    • H03K3/281—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator
    • H03K3/286—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable
    • H03K3/288—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit
    • H03K3/2885—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of bipolar transistors with internal or external positive feedback using means other than a transformer for feedback using at least two transistors so coupled that the input of one is derived from the output of another, e.g. multivibrator bistable using additional transistors in the input circuit the input circuit having a differential configuration

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Analogue/Digital Conversion (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

PURPOSE:To offer a comparator circuit for AD/DA having the capacity for improvement of the conversion speed and attaining low power consumption by providing a differential amplifier to a pre-stage of a latching comparator and giving the output of the amplifier to an input of the latching comparator while keeping a differential signal. CONSTITUTION:The comparator circuit comprises a differential amplifier section 110, a latch section 120, a current output section 130 for DA output and a digital output section 140. the latch section 120 receiving a comparator output of the differential amplifier section 110 switches transistors (TRs) Q5, Q6 and TRs Q3, Q4 so as to attain latch operation. The output section 130 conducts switchig with an output of the pre-stage while keeping a direct differential signal. The output section 140 switches the current with the output of the latch section 120 and converts it into a binary code while keeping the direct differential signal. Since the differential amplifier section 110 is operated while the latch section 120 keeps a prescribed value for a certain period as the comparator output in this way, the response speed when the operation is changed over from the holding into the comparison is improved. Further, the current output section 130 starts switching operation when the latch output starts changing, thereby attaining high speed response.

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は、比較器回路に関し、特に直並列形ＡＤ変換器
における部分ＡＤ変換器を構成するコンパレータ回路に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a comparator circuit, and particularly to a comparator circuit constituting a partial AD converter in a series-parallel AD converter.

〔発明の背景〕[Background of the invention]

例えば、Ｖ　Ｔ　Ｒ（Ｖｉｄｅｏ　Ｔａｐｅ　Ｒｅｃｏ
ｒｄｅｒ）　（７）時間軸補正器として、高速のＡＤ変
換器が用いられる。このような高性能を実現するために
は、直並列ＡＤ変換方式が適しているが、この方式は上
位ビットをＡＤ変換し、そのＤＡ変換値と入力の差を再
度ＡＤ変換することによシ、下位ビットを決定するもの
であって、ＡＤ変換−ＤＡ変換動作がその速度を決めて
いる。、 第１図は、従来の直並列形ＡＤ変換器のブロック図であ
る。For example, VTR (Video Tape Reco
(7) A high-speed AD converter is used as a time axis corrector. In order to achieve such high performance, a series/parallel AD conversion method is suitable, but this method involves AD converting the upper bits and then AD converting the difference between the DA conversion value and the input again. , which determines the lower bits, and the AD conversion-DA conversion operation determines its speed. , FIG. 1 is a block diagram of a conventional serial-parallel AD converter.

１と３はＡＤ変換器、２はＤＡ変換器、４は減算器、５
はレジスタである。先ず、ＭｌのＡＤ変換器（以下ＡＤ
Ｃと記す）ｌによシ入カアナログ信号の上位ビットのＡ
Ｄ変換を行い、その結果をＤＡ変換器（以下ＤＡＣと記
す）２によシアナログ信号に戻して、減算器４によシ入
力信号との差をとシ、第２のＡＤＣ３によシ下位ビット
のＡＤ変換を行う。1 and 3 are AD converters, 2 is a DA converter, 4 is a subtracter, 5
is a register. First, the Ml AD converter (hereinafter referred to as AD
A of the upper bit of the input analog signal
D conversion is performed, the result is returned to an analog signal by a DA converter (hereinafter referred to as DAC) 2, the difference with the input signal is calculated by a subtracter 4, and the result is converted by a second ADC 3 into a lower analog signal. Performs AD conversion of bits.

このような直並列形ＡＤＣにおいて、高速化のために、
第１のＡＤＣＩとＤ４Ｃ２とを区別しない方式、つまｐ
ＡＤｃｌの出力が得られるとほぼ同時に、それに対応す
るＤＡ変換出力が得られる方式が提案されている。In such a series/parallel type ADC, in order to increase the speed,
A method that does not distinguish between the first ADCI and D4C2, that is, p
A method has been proposed in which a corresponding DA conversion output can be obtained almost at the same time as the ADcl output is obtained.

第２図は、第１図において、ＡＤＣｌとＤＡＣ２とを区
別しない方式の構成図である。FIG. 2 is a block diagram of a system in which ADCl and DAC2 are not distinguished in FIG. 1.

第２図においては、ＡＤＣｌとして並列形を用いておシ
、並列に配置された比較器１１でアナログ入力と参照電
圧とを比較し、サンプリング値を決めて後段のスイッチ
１３に反転出力とともに出力する。スイッチ１３は、入
力された値により定電流源１２をスイッチし、アナログ
電流値Ｉｏ。In Fig. 2, a parallel type ADCl is used, and a comparator 11 arranged in parallel compares the analog input with the reference voltage, determines a sampling value, and outputs it to the subsequent switch 13 along with an inverted output. . The switch 13 switches the constant current source 12 according to the input value to obtain an analog current value Io.

Ｉｏを得る。この回路の詳細動作は、公知文献（出水他
「昭和５０年度電子通信学会全国大会予稿４７８）を参
照されたい。Get Io. For detailed operation of this circuit, please refer to a known document (Izumi et al., 1975 Institute of Electronics and Communication Engineers National Conference Proceedings 478).

このようなりＡ変換出力が得られるＡＤＣ（以下ＡＤ／
ＤＡと記す〕用のコンパレータにおいては、入力が変化
してもＤＡ出力値は一定期間だけ一定値を保持しなけれ
ばならないため、ラッチ機能を有したラッチング・コン
パレータが適してい　、。An ADC (hereinafter referred to as AD/
A latching comparator with a latch function is suitable for a comparator for DA], since the DA output value must maintain a constant value for a certain period of time even if the input changes.

ΦＯ 第３図は、従来のラッチング・コンパレータの回路構成
図である。ΦO FIG. 3 is a circuit diagram of a conventional latching comparator.

ラッチング・コンパレータとしては、第３図に示すよう
に、増幅部（トランジスタＱ３１．　Ｑ３２）と、ラッ
チ部（トランジスタＱ３３．Ｑ３４）とを、トランジス
タＱ３５．Ｑ３６で切シ替えて使用するものである。こ
のようなラッチング・コンパレータをＡ　Ｄ／Ｄ　Ａに
使用する場合、ラッチ部が動作している間は、増幅部が
動作しないため、増幅動作に切り替わった時点では十分
な変換速度が得られない欠点がある。さらに、コンパレ
ータ群の出力全２進符号に変換するデコーダを含めて、
低電力化に対して必ずしも最適な構成になっていない点
もあった。As a latching comparator, as shown in FIG. 3, an amplifier section (transistors Q31, Q32) and a latch section (transistors Q33, Q34) are connected to transistors Q35, . It is used by switching at Q36. When such a latching comparator is used for A D/D A, the amplifying section does not operate while the latching section is operating, so a sufficient conversion speed cannot be obtained when switching to amplifying operation. There is. Furthermore, including a decoder that converts the output of the comparator group into full binary code,
In some cases, the configuration was not necessarily optimal for reducing power consumption.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、このような従来の欠点を除去し、変換
速度の向上と低消費電力化を図ることができるＡ　Ｄ／
Ｄ　Ａ用の比較器回路を提供することにある。An object of the present invention is to eliminate such conventional drawbacks, and to improve conversion speed and reduce power consumption.
An object of the present invention is to provide a comparator circuit for DA.

〔発明の概要〕[Summary of the invention]

上記目的を達成するため、本発明の比較器回路は、差動
増幅回路と、該差動増幅回路の出力にそれぞれトランジ
スタを正帰還させて構成するラッチ回路とを電流スイッ
チによシ交互に切り替えるラッチング・コンパレータに
おいて、該ラッチング・コンパレータの前段に差動増幅
器を設け、該差動増幅器の出力を差動のまま上記ラッチ
ング・コンパレータの入力に接続することに特徴がある
。In order to achieve the above object, the comparator circuit of the present invention alternately switches between a differential amplifier circuit and a latch circuit configured by positively feeding a transistor to the output of the differential amplifier circuit using a current switch. The latching comparator is characterized in that a differential amplifier is provided before the latching comparator, and the output of the differential amplifier is connected to the input of the latching comparator as it is differential.

〔発明の実施例〕[Embodiments of the invention]

以下、本発明の実施例を図面によシ説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第４図は、本発明の第１の実施例を示す比較器回路の構
成図である。FIG. 4 is a configuration diagram of a comparator circuit showing a first embodiment of the present invention.

第４図においては、差動増幅部１１０、ラッチ部１２０
、ＤＡ出力用の電流出力部１３０、およびディジタル出
力部１４０で比較器回路を構成する。In FIG. 4, a differential amplifier section 110, a latch section 120
, a current output section 130 for DA output, and a digital output section 140 constitute a comparator circuit.

差動増幅部１１０け、トランジスタＱｌ、Ｑ２、定電流
源１１１等で構成され、この増幅部１１０によシ入力信
号１１２と比較参照電圧１１３との差が増幅される。こ
の出力は、次段のラッチ部１２０に入力される。ラッチ
部１２０は、増幅用トランジスタＱ３．Ｑ４、ラッチ用
トランジスタＱ５．Ｑ６Ｎスイッチ用トランジスタＱ７
．Ｑ８、定電流源１２１等によシ構成されておシ、ラッ
チ用トランジスタＱ５．Ｑ６と増幅用トランジスタＱ３
．Ｑ４とを切り替えて使用することにより、ラッチ動作
を行うものである。ＤＡ出力用の電流出力部１３０は、
トランジスタＱ９．ＱＩＯと定電流源１３１で構成され
、ラッチ部１２０の出力で直接差動信号のまま、トラン
ジスタＱ９．ＱＩＯを駆動し、電流のスイッチングを行
うものである。A differential amplification section 110 is composed of transistors Ql, Q2, a constant current source 111, etc., and the difference between the input signal 112 and the comparison reference voltage 113 is amplified by this amplification section 110. This output is input to the latch section 120 at the next stage. The latch section 120 includes an amplification transistor Q3. Q4, latch transistor Q5. Q6N switch transistor Q7
．． Q8, a constant current source 121, etc., and a latch transistor Q5. Q6 and amplification transistor Q3
．． A latch operation is performed by switching between Q4 and Q4. The current output section 130 for DA output is
Transistor Q9. QIO and a constant current source 131, the transistor Q9. It drives the QIO and performs current switching.

ディジタル出力部１４０は、トランジスタＱ１１゜Ｑ１
２．Ｑ１３と抵抗′ｆＬｄｏと定電流源１４１等によシ
構成され、ラッチ部１２０の出力で直接差動信号のまま
、トランジスタＱ１１．Ｑ１２を駆動し、電流をスイッ
チした後、デコーダによシ２進化符号に変換するもので
ある。すなわち、このデコーダは、ラッチ部１２０の差
動出力で駆動されるトランジスタ対Ｑｌｌ、Ｑ１２の一
方のコレクタに抵抗Ｒａｏの一端を接続し、抵抗比４Ｑ
の他端を電源Ｖｃｃあるいはグランドに接続し、そのコ
レクタに別のトランジスタＱ１３のベースを接続し、ト
ランジスタＱ１３のエミッタから電圧出力を得る。同時
に、トランジスタ対の他方のコレクタを開放する。なお
、上記開放されたコレクタは、比較器回路を複数個並列
に配置したとき、隣り合う比・較器回路のトランジスタ
対の抵抗が接続されているコレクタに接続される。この
ようにして、ラッチ部１２０の出力は、電流出力部１３
０とディジタル出力部１４０とを並列に駆動している。The digital output section 140 is a transistor Q11゜Q1
2. Q13, a resistor 'fLdo, a constant current source 141, etc., and the transistors Q11. After driving Q12 and switching the current, it is converted into a binary code by a decoder. That is, in this decoder, one end of the resistor Rao is connected to one collector of the transistor pair Qll and Q12 driven by the differential output of the latch section 120, and the resistance ratio is 4Q.
The other end is connected to the power supply Vcc or ground, its collector is connected to the base of another transistor Q13, and a voltage output is obtained from the emitter of transistor Q13. At the same time, the collector of the other transistor pair is opened. Note that, when a plurality of comparator circuits are arranged in parallel, the open collector is connected to the collector to which the resistors of the transistor pairs of adjacent comparator circuits are connected. In this way, the output of the latch section 120 is transmitted to the current output section 13.
0 and the digital output section 140 are driven in parallel.

このような構成により、先ずラッチ部１２０がコンパレ
ータ出力として、ある期間一定値を保持している間、入
力部である差動増幅部１１０は動作しているため、ラッ
チの保持動作からコンパレータとしての比較動作に切り
替ったときの応答速度が従来に比べて改善され、全体と
して、高速比較動作、ラッチ動作が可能となる。また、
電流出力部１３０は、ラッチ出力を差動で入力している
ため、ラッチ出力が変化し始めた時点からスイッチ動作
を開始することができ、したがって遅延カニ少なく、高
速の応答が可能となる。With this configuration, first, while the latch section 120 holds a constant value as a comparator output for a certain period of time, the differential amplifier section 110, which is the input section, is operating, so the latch holding operation is changed from the latch holding operation to the comparator output. The response speed when switching to comparison operation is improved compared to the conventional method, and overall high-speed comparison operation and latch operation are possible. Also,
Since the current output section 130 inputs the latch output differentially, the switching operation can be started from the time when the latch output starts to change. Therefore, a high-speed response is possible with less delay.

コンパレータのディジタル出力部１４０は、このような
コンパレータを用いて並列形ＡＤＣを構成した場合に、
各コンノくレータ出力からＡＤＣ出力である２進化符号
に変換するためのデコーダ゛を有している。The digital output section 140 of the comparator is, when a parallel ADC is configured using such a comparator,
It has a decoder for converting the output of each converter into a binary code which is the output of the ADC.

第５図は、本発明のコンノ（レータを用いたＡＤ／ＤＡ
の構成図である。FIG. 5 shows an AD/DA controller using the controller of the present invention.
FIG.

第４図に示したコンノくレータ１０のディジタル出力部
１４０の出力Ｅ。と１０を、第５図のように並列に配置
された各コンノ（レーク１０間で相互に接続する。これ
によシ、入力信号に応じてコンパレータ出力が′１″か
ら′０＃に変わる変化点に対応するコンパレータ１０の
ディジタル出力ＥＯＩＪＴのみが′１”レベルとなる。Output E of the digital output section 140 of the converter 10 shown in FIG. and 10 are connected to each other between each controller (rake 10) arranged in parallel as shown in Figure 5.This allows the comparator output to change from '1' to '0#' depending on the input signal Only the digital output EOIJT of the comparator 10 corresponding to the point becomes '1' level.

各コンノくレータ１０の出力ＥＯＵＴを、そのコンノく
レータ１０力；対応する２進化符号に応じてそれぞれの
ビット線でワイアード・オアをとれば、２進化符号に変
換することができ、デコーダが簡単に実現できる。The output EOUT of each converter 10 can be converted into a binary code by performing a wired OR on each bit line according to the corresponding binary code, making the decoder simple. can be realized.

第６図は、本発明の第２の実施例を示す比較器回路の構
成図である。FIG. 6 is a configuration diagram of a comparator circuit showing a second embodiment of the present invention.

第６図においては、ラッチ部１２０の上部でバッファ用
トランジスタＱ２１．Ｑ２２を介してディジタル出力Ｅ
ｏ　、Ｅｏを得る構成であり、デコーダ部に関する接続
は第１の実施例の場合と同じである。第６図の構成では
、ラッチ部１２０の上部から出力を得るので、定電流源
が共通化できる等の利点がある。In FIG. 6, buffer transistor Q21. Digital output E via Q22
o and Eo, and the connections regarding the decoder section are the same as in the first embodiment. In the configuration shown in FIG. 6, since the output is obtained from the upper part of the latch section 120, there is an advantage that a constant current source can be shared.

第４図、第６図の実施例から明らかなように、ラッチ部
１２０の前段に増幅部１１０を配置することによシ比較
動作の高速化が可能となる。また、ラッチ部１２０の入
力で増幅された入力信号が得られることによシ、動作電
流を低減しても十分な変換速度が得られる。さらに、デ
ィジタル出力部１４０についても、差動で駆動する方式
を用いることにより、速度低下が少なく、電源電圧を低
く抑えることができるため、低消費電力化が可能となる
。As is clear from the embodiments shown in FIGS. 4 and 6, by arranging the amplifier section 110 before the latch section 120, it is possible to speed up the comparison operation. Further, since an amplified input signal is obtained at the input of the latch section 120, a sufficient conversion speed can be obtained even if the operating current is reduced. Furthermore, by using a differential drive method for the digital output section 140, there is little speed reduction and the power supply voltage can be kept low, making it possible to reduce power consumption.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明によれば、直並列形ＡＤＣ
用の部分構成要素としてのＡ　Ｄ／Ｄ　Ａに対して、高
速変換および低消費電力化が可能となるので、システム
全体の性能向上および経済性の向上を図ることができる
利点がある。As explained above, according to the present invention, the series-parallel type ADC
Since high-speed conversion and low power consumption are possible for AD/DA as a partial component for the system, there is an advantage that the performance and economy of the entire system can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、従来の直並列形ＡＤ変換器のブロック図、第
２図は第１図においてＡＤＣとＤＡＣを区別しない方式
の構成図、第３図は従来のラッチング・コンパレータの
回路構成図、第４図は本発明の第１の実施例を示す比較
器回路の構成図、第５図は本発明のコンパレータを用い
たＡＤ／ＤＡの構成図、第６図は本発明の第２の実施例
を示す比較器回路の構成図である。 １．３・・・ＡＤ変換器、２・・・ＤＡ変換器、４・・
・減算器、５・・・レジスタ、１１・・・コンパレータ
、１３・・・スイッチ、１１１，１２１，１３１，１４
１゜１２・・・定電流源、１１０・・・差動増幅部、１
２０・・・ラッチ部、１３０・・・電流出力部、１４ｏ
・・・ディジタル出力部。 遁　１　λ よう立　下位 尤　４−　図 ｒ ／　３７１　／４−ν ＺＳ　図 ”Ｉｃｅ ｖｂｔ　１２θFig. 1 is a block diagram of a conventional serial-parallel AD converter, Fig. 2 is a block diagram of a system that does not distinguish between ADC and DAC in Fig. 1, and Fig. 3 is a circuit diagram of a conventional latching comparator. FIG. 4 is a block diagram of a comparator circuit showing a first embodiment of the present invention, FIG. 5 is a block diagram of an AD/DA using the comparator of the present invention, and FIG. 6 is a block diagram of a second embodiment of the present invention. FIG. 2 is a configuration diagram of a comparator circuit showing an example. 1.3...AD converter, 2...DA converter, 4...
・Subtractor, 5...Register, 11...Comparator, 13...Switch, 111, 121, 131, 14
1゜12...constant current source, 110...differential amplifier section, 1
20... Latch section, 130... Current output section, 14o
...Digital output section. Release 1 λ Yotachi Lower value 4- Figure r / 371 /4-ν ZS Figure "Ice vbt 12θ

Claims (1)

【特許請求の範囲】 １、差動増幅回路と、該差動増幅回路の出力にそれぞれ
トランジスタを正帰還させて構成するラッチ回路とを電
流スイッチによシ交互に切シ替えるラッチング働コンパ
レータにおいて、該ラッチング・コンパレータの前段に
差動増幅器を設け、該差動増幅器の出力を差動のまま上
記ラッチング・コンパレータの入力に接続することを特
徴とする比較器回路。 ２、前記ラッチング−コンパレータの差動出力は、後段
に接続された電流出力回路の定電流源からの電流を！１
７Ｊ、ｂ替えることを特徴とする特許請求の範囲第１項
記載の比較器回路。 ３、前記ランチング・コンパレータの差動出力は、トラ
ンジスタ対の一方のコレクタに抵抗の一端を接続し、該
抵抗の他端を電源またはグランドに接続し、上記コレク
タに別のトランジスタのペースを接続して、該トランジ
スタのエミッタから電圧出力を得るとともに、上記トラ
ンジスタ対の他方のコレクタを開放して構成されたコー
ド変換回路のトランジスタ対を駆動すること器回路。 ４、前記コード変換回路のトランジスタ対の開放された
コレクタは、前記比較器回路を複数個並列に配置したと
き、隣接する比較器回路のトランジスタ対の抵抗が接続
されたコレクタに接続されることを特徴とする特許請求
の範囲第３項記載の比較器回路。 ５、前記ラッチング・コンパレータの差動出力は、前記
電流出力回路と前記コード変換回路とを並列に駆動する
ことを特徴とする特許請求の範囲第１項、第２項または
第３項記載の比較器回路。[Claims] 1. A latching comparator in which a current switch alternately switches between a differential amplifier circuit and a latch circuit configured by positive feedback of a transistor to the output of the differential amplifier circuit, A comparator circuit characterized in that a differential amplifier is provided before the latching comparator, and the output of the differential amplifier is connected to the input of the latching comparator in a differential state. 2. The differential output of the latching comparator outputs the current from the constant current source of the current output circuit connected to the subsequent stage! 1
7. The comparator circuit according to claim 1, characterized in that 7J and 7B are changed. 3. The differential output of the launching comparator is obtained by connecting one end of a resistor to the collector of one of the transistor pairs, connecting the other end of the resistor to a power supply or ground, and connecting the collector of another transistor to the collector of the resistor. A circuit for driving a transistor pair of a code conversion circuit configured by obtaining a voltage output from the emitter of the transistor and opening the collector of the other transistor pair. 4. The open collector of the transistor pair of the code conversion circuit is connected to the collector connected to the resistor of the transistor pair of the adjacent comparator circuit when a plurality of the comparator circuits are arranged in parallel. A comparator circuit according to claim 3, characterized in that: 5. Comparison according to claim 1, 2 or 3, wherein the differential output of the latching comparator drives the current output circuit and the code conversion circuit in parallel. device circuit.
JP58135975A 1983-07-27 1983-07-27 Comparator circuit Granted JPS6028320A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58135975A JPS6028320A (en) 1983-07-27 1983-07-27 Comparator circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58135975A JPS6028320A (en) 1983-07-27 1983-07-27 Comparator circuit

Publications (2)

Publication Number Publication Date
JPS6028320A true JPS6028320A (en) 1985-02-13
JPH0475687B2 JPH0475687B2 (en) 1992-12-01

Family

ID=15164244

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58135975A Granted JPS6028320A (en) 1983-07-27 1983-07-27 Comparator circuit

Country Status (1)

Country Link
JP (1) JPS6028320A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186534U (en) * 1986-05-19 1987-11-27
JPS6344537U (en) * 1986-09-08 1988-03-25
JPS63191419A (en) * 1987-02-04 1988-08-08 Hitachi Ltd Ad converter
JPH02105631A (en) * 1988-08-25 1990-04-18 Brooktree Corp Self-synchronizing analog/digital converter system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731226A (en) * 1980-08-04 1982-02-19 Matsushita Electric Ind Co Ltd Comparator circuit
JPS59122016A (en) * 1982-12-27 1984-07-14 Sony Corp Latched comparator

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5731226A (en) * 1980-08-04 1982-02-19 Matsushita Electric Ind Co Ltd Comparator circuit
JPS59122016A (en) * 1982-12-27 1984-07-14 Sony Corp Latched comparator

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62186534U (en) * 1986-05-19 1987-11-27
JPS6344537U (en) * 1986-09-08 1988-03-25
JPS63191419A (en) * 1987-02-04 1988-08-08 Hitachi Ltd Ad converter
JPH02105631A (en) * 1988-08-25 1990-04-18 Brooktree Corp Self-synchronizing analog/digital converter system

Also Published As

Publication number Publication date
JPH0475687B2 (en) 1992-12-01

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