JP2000188517A - Differential amplifier, comparator, a/d converter, semiconductor integrated circuit and storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the voltage amplification gain without increase of a load impedance by providing a first load resistor where one terminal is connected to the second polarities of first and third transistors and the other terminal is connected to a first power line, connecting one terminal to the second electrodes of second and fourth transistors and the other terminal to a first power line. SOLUTION: A differential amplifier is provided with a p-type MOS transistor TP 3 which is connected in series between a power line to which first voltage VDD is applied and an installation line to which second voltage is applied. PMOSTP1 and TP2 of differential constitution, n-type MOS transistors TN1 and TN2 of the differential constitution and NMOSTN3 are also provided. PMOSTP3 where a source electrode is connected to the power line constitutes a first constant current source and constant bias voltage VGP is applied to a gate electrode. NMOSTN3 where a source electrode is connected to the installation line constitutes a second constant current source.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a differential amplifier, a comparator, an A / D converter, a semiconductor integrated circuit device, and a storage device. The present invention relates to a technique that is effective in improving the operation speed.

[0002]

2. Description of the Related Art In recording devices such as hard disk devices (HDDs), digital VTRs, and optical disk devices, PR
A signal processing technology called ML (Partial Response Maximum Likelihood) is employed. This PRML technology
Generally, the waveform of an analog signal read from a recording medium such as a magnetic disk, a magnetic tape, and an optical disk is converted into a digital signal by an A / D converter, and the PR (Partial Respons
e) After equalization by a PR equalizer having characteristics, finally, decoding is performed by a Viterbi decoding circuit that is a maximum likelihood decoding method. By adopting this PRML technology, it is possible to improve the recording density by about 1.2 to 1.5 times by signal processing without largely changing the existing recording / reproducing system. In this case, the A / D
A comparator is used as an internal circuit of the converter, and a folded cascode type comparator is known as this comparator. The folded cascode type comparator is described in, for example, the following document (a). (A) 'A 70-MS / s 110mW 8-b CMOS Folding and Interp
olating A / D Convertor'IEEE JOURNAL OF SOLID-STATE
CIRCUITS VOL.30, NO.12, DECEMBER 1995 P.1306

[0003]

In order to improve the operation speed of the A / D converter, it is effective to increase the comparator voltage amplification gain used as an internal circuit of the A / D converter. is there. In order to increase the voltage amplification gain of the folded cascode comparator used as the internal circuit of the A / D converter, the current flowing through the folded cascode comparator must be increased or the resistance of the load must be increased. Ingredients need to be increased. However, when the current flowing through the folded cascode type comparator is increased, the current consumption increases, and when the resistance component of the load is increased, the output impedance is increased. There was a problem that the time to do was slow. SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to improve a voltage amplification gain in a differential amplifier without increasing current consumption and load impedance. It is to provide a technology that makes it possible.

It is another object of the present invention to provide a technique that enables an operation speed of a comparator to be improved without increasing power consumption.

It is another object of the present invention to provide a technique which enables an A / D converter to improve an operation speed without increasing power consumption.

It is another object of the present invention to provide a technique capable of improving the operation speed of a storage device without increasing power consumption.

Another object of the present invention is to provide a semiconductor integrated circuit device equipped with the A / D converter.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0009]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. That is, according to the present invention, in a differential amplifier, a first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode Is the first of the first transistor
A second transistor of the first conductivity type connected to the first electrode, a second electrode connected to the control electrode of the first transistor, and a second electrode connected to the second electrode of the first transistor.
A third transistor of a conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor,
A fourth transistor of a second conductivity type having a first electrode connected to a first electrode of the third transistor;
A first constant current source connected between a first electrode of the second and second transistors and a first power supply line to which a first voltage is applied; and a first constant current source of the third and fourth transistors. A second constant current source connected between the electrode and a second power supply line to which a second voltage is applied; one terminal connected to a second electrode of the first and third transistors; A first load resistor having the other terminal connected to the first power supply line, one terminal connected to second electrodes of the second and fourth transistors, and a second terminal connected to the first terminal. And a second load resistor connected to the power supply line.

Further, according to the present invention, in a differential amplifier, a control electrode is connected to a first input terminal.
, A control electrode is connected to a second input terminal, a first electrode is connected to a first electrode of the first transistor, a second transistor of a first conductivity type, and a control electrode is 1 input terminal, and the second electrode is connected to the first input terminal.
A third transistor of a second conductivity type connected to a second electrode of the second transistor; a control electrode connected to a second input terminal; and a second electrode connected to a second electrode of the second transistor. A fourth transistor of a second conductivity type having a first electrode connected to a first electrode of the third transistor, and a fourth transistor of the first and second transistors. A first constant current source connected between one electrode and a first power supply line to which a first voltage is applied;
A first electrode of the third and fourth transistors;
A second constant current source connected to a second power supply line to which a voltage is applied, a first electrode connected to a second electrode of the first and third transistors, and a control electrode connected to a second electrode. A seventh transistor of a second conductivity type to which a constant first bias voltage is applied, a first electrode connected to second electrodes of the second and fourth transistors, and a constant first electrode connected to a control electrode. An eighth transistor of the second conductivity type to which the bias voltage is applied, one terminal is connected to the second electrode of the seventh transistor, and the other terminal is connected to the first power supply line. A first load resistor, one terminal connected to the second electrode of the eighth transistor, and the other terminal connected to the first electrode;
And a second load resistor connected to the power line.

Further, the present invention is characterized in that the differential amplifier has an output terminal connected to one terminal of the first load resistor or one terminal of the second load resistor. .

Further, according to the present invention, in a differential amplifier, a first output terminal connected to one terminal of the first load resistor, and a first output terminal connected to one terminal of the second load resistor. And two output terminals.

Further, the present invention is characterized in that, in the differential amplifier, an active load circuit is used instead of the first and second load resistors.

Further, according to the present invention, in the differential amplifier, when the current value of the first constant current source is (I1) and the current value of the first constant current source is (I2), I1 <I2 Is satisfied.

According to the present invention, in a comparator, a first transistor of a first conductivity type having a control electrode connected to a first input terminal; a control electrode connected to a second input terminal;
A second transistor of a first conductivity type, a first electrode connected to a first electrode of the first transistor; a control electrode connected to a first input terminal; and a second electrode connected to the first electrode. A third of a second conductivity type connected to a second electrode of the transistor;
And a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, wherein a first electrode is connected to the third electrode. Connected to the first electrode of the second transistor
A fourth transistor of a conductivity type, a first constant current source connected between first electrodes of the first and second transistors, and a first power supply line to which a first voltage is applied; A second constant current source connected between a first electrode of the third and fourth transistors and a second power supply line to which a second voltage is applied; Transistor second
A first output terminal connected to an electrode, a second output terminal connected to a second electrode of the second and fourth transistors, and a first electrode connected to the first power supply line; A fifth transistor having two electrodes connected to the first output terminal, a fifth transistor of a first conductivity type having a control electrode connected to a second output terminal, and a first electrode connected to the fifth transistor; 1
A sixth transistor having a second electrode connected to the second output terminal and a control electrode connected to the first output terminal. And a switching element connected between the first output terminal and the second output terminal and turned on within a predetermined period.

According to the present invention, in a comparator, a first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal,
A second transistor of a first conductivity type, a first electrode connected to a first electrode of the first transistor; a control electrode connected to a first input terminal; and a second electrode connected to the first electrode. A third of a second conductivity type connected to a second electrode of the transistor;
And a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, wherein a first electrode is connected to the third electrode. Connected to the first electrode of the second transistor
A fourth transistor of a conductivity type, a first constant current source connected between first electrodes of the first and second transistors, and a first power supply line to which a first voltage is applied; A second constant current source connected between a first electrode of the third and fourth transistors, a second power supply line to which a second voltage is applied, and a first electrode connected to the first electrode. A seventh transistor of the second conductivity type, which is connected to the second electrodes of the first and third transistors and has a constant first bias voltage applied to the control electrode; and wherein the first electrode is connected to the second and fourth transistors. An eighth transistor of a second conductivity type, which is connected to a second electrode of the first transistor and a constant first bias voltage is applied to a control electrode, and a first transistor connected to a second electrode of the seventh transistor. And the second terminal connected to the second electrode of the eighth transistor. A fifth transistor having a force terminal and a first electrode connected to the first power supply line, and a second electrode connected to the first output terminal, wherein a control electrode is connected to the second output terminal A fifth transistor of a first conductivity type, and a sixth transistor having a first electrode connected to the first power supply line and a second electrode connected to the second output terminal. A first electrode whose electrode is connected to the first output terminal;
A sixth transistor of a conductivity type, and a switching element that is connected between the first output terminal and the second output terminal and that is turned on within a predetermined period is provided.

Further, the invention is characterized in that, in the comparator, the switching element is a transistor to which a clock signal is applied to a control electrode.

Further, according to the present invention, in the comparator, when the current value of the first constant current source is (I1) and the current value of the first constant current source is (I2), I1 <I2 is satisfied. It is characterized by satisfaction.

The present invention also provides a T / H circuit for sampling an analog input signal at a predetermined timing;
/ H circuit, a plurality of comparators for comparing the output voltage with a reference voltage, a latch circuit for latching a comparison output from the comparator, and an encoder for outputting a digital signal based on the output from the latch circuit A reference voltage generating circuit for supplying a plurality of different reference voltages to the plurality of comparators, and a timing for supplying a clock signal to the T / H circuit, the comparator, and the latch circuit A / including a generation circuit
In the D converter, the comparator is the comparator described above.

The present invention also provides a T / H circuit for sampling a differential analog input signal at a predetermined timing, a positive-phase output voltage from the T / H circuit for a positive-phase reference voltage, and A level shift circuit for level-shifting the negative-phase output voltage from the H circuit by the negative-phase reference voltage; a positive-phase output voltage level-shifted by the positive-phase reference voltage from the level shift circuit; A plurality of comparators for comparing a negative-phase output voltage level-shifted by the negative-phase reference voltage, a latch circuit for latching a comparative output from the comparator, and a digital signal based on an output from the latch circuit. And a plurality of different positive-phase reference voltages and negative-phase references for the plurality of comparators, respectively. A / D converter comprising: a reference voltage generating circuit for supplying a voltage; and a timing generating circuit for supplying a clock signal to the T / H circuit, the comparator, and the latch circuit. It is characterized by being.

The present invention also provides an A / D converter,
The level shift circuit includes a first and a second pair which share a pair of diode-connected transistors as a load circuit.
A first differential amplifier in which a positive-phase output voltage is applied to a first input terminal and a positive-phase reference voltage is applied to a second input terminal; A second differential amplifier to which a negative-phase reference voltage is applied and a negative-phase output voltage is applied to a second input terminal is provided.

Further, the present invention provides an A / D converter,
The latch circuit includes a cascode latch circuit, an RTZ latch circuit, and a NOR latch circuit connected in cascade.

According to the present invention, there is provided a semiconductor integrated circuit device having an A / D converter, wherein the A / D converter is the A / D converter described above.

According to another aspect of the present invention, there is provided a storage device comprising: a storage medium for recording a digital signal; writing means for storing the digital signal in the storage medium; and reading means for reading the digital signal from the storage medium. A storage device having an A / D converter for converting an analog signal read from the recording medium into a digital signal, wherein the A / D converter is configured to execute the A / D conversion according to the above description.
It is a converter.

According to the present invention, in the storage device, the read means includes a PR type equalizer, an A / D converter,
And a decoder of a maximum likelihood decoding method.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted.

[First Embodiment] FIG. 1 is a circuit diagram showing a circuit configuration of a differential amplifier according to a first embodiment of the present invention. The differential amplifier according to the present embodiment includes a power supply line (first power supply line) to which the first voltage (VDD) is applied and a second voltage (G
ND) and a ground line (second power supply line) to which a p-type MOS transistor (hereinafter, referred to as a second power supply line) is applied.
Called PMOS. ) (TP3) and PMO with differential configuration
S (TP1, TP2) and an n-type MOS transistor having a differential configuration (hereinafter referred to as NMOS) (TN1, TN)
2) and an NMOS (TN3). Here, a PMOS (TP3) whose source electrode is connected to the power supply line
Constitutes a first constant current source, and a constant bias voltage (VGP) is applied to the gate electrode. Similarly, an NMOS (T) whose source electrode is connected to the ground line
N3) constitutes a second constant current source, and a constant bias voltage (VGN) is applied to the gate electrode.
Each source electrode of the PMOS (TP1, TP2) is
Similarly, each source electrode of the NMOS (TN1, TN2) is connected to the drain electrode of the PMOS (TP3).
Connected to the drain electrode of MOS (TN3).

The drain electrode of the PMOS (TP1) is connected to the drain electrode of the NMOS (TN1), and the gate electrode of the PMOS (TP1) is connected to the NMOS (TN1).
The gate electrode of (TN1) is a first input terminal (IN
P). Similarly, the drain electrode of the PMOS (TP2) is connected to the drain electrode of the NMOS (TN2), and the gate electrode of the PMOS (TP2)
The gate electrode of the NMOS (TN2) is connected to the second input terminal (INM).

Further, a drain electrode of the PMOS (TP1) (or a drain electrode of the NMOS (TN1))
Load resistance (R1) and NMOS (T
N4). Where NMOS
(TN4) has a source electrode connected to a drain electrode of a PMOS (TP1) (or a drain electrode of an NMOS (TN1)), and a drain electrode connected to a load resistor (R1). Similarly, a load resistor (R2) and an NMOS (TN) are connected between the drain electrode of the PMOS (TP2) (or the drain electrode of the NMOS (TN2)) and the power supply line.
5) is connected. Here, NMOS (T
N5) the source electrode is the drain electrode of the PMOS (TP2) (or the drain electrode of the NMOS (TN2))
, And the drain electrode is connected to the load resistance (R2). A constant bias voltage (VB) is applied to each gate electrode of the NMOS (TN4, TN5), and the drain electrode of the NMOS (TN4) is connected to the second output terminal (OUTM). The drain electrode is connected to a first output terminal (OUTP). This NM
OS (TN4, TN5) includes a drain electrode of the PMOS (TP1) (or a drain electrode of the NMOS (TN1)) and a drain electrode of the PMOS (TP2) (or
This is for maintaining the drain voltage of the NMOS (TN2) at a constant voltage, and is the drain electrode of the PMOS (TP1) (or the drain electrode of the NMOS (TN1)).
And the drain electrode of PMOS (TP2) (or NM
This is not necessary if the voltage of the OS (TN2) drain electrode is kept constant.

Hereinafter, the operation of the differential amplifier according to the present embodiment will be described with reference to FIG. However, in order to simplify the description, the current flowing through the PMOS (TP3) is 2 · I, NM
Assuming that the current flowing through OS (TN3) is 4 · I,
The resistance values of the load resistors (R1, R2) are both RL. The voltages of the input signals applied to the first input terminal (INP) and the second input terminal (INM) are the same (V)
In the case of, the current flowing through the PMOS (TP1) and the current flowing through the PMOS (TP2) are the same (I), and the current flowing through the NMOS (T
N1) and the current flowing through the NMOS (TN2) are the same (2
・ I). Therefore, the current flowing through the load resistors (R1, R2) is also the same (I), and the potential difference (VOUT) between the first output terminal (OUTP) and the second output terminal (OUTM) is as follows: As shown in equation (1), they are the same (VOUT = 0).

[0031]

VOUT = (VDD−RL · I) − (VDD−RL · I) = 0 (1) where When the voltage of the input signal applied to the first input terminal (INP) becomes (V + Δv) and the voltage of the input signal applied to the second input terminal (INM) becomes (V−Δv), P
The current flowing through the MOS (TP1) is (I−Δio), PM
The current flowing through the OS (TP2) is (I + Δio),
The current flowing through the NMOS (TN1) is (2 · I + Δ
ip), the current flowing through the NMOS (TN2) is (2 · I−
Δip). Therefore, the current flowing through the load resistance (R1) is (I + Δio + Δip), and the current flowing through the load resistance (R2) is (I−Δio−Δip). Therefore, as shown in the following equation (2), the first output terminal (OU
TP) and the second output terminal (OUTM) have a potential difference (VOUT) of 2 · (Δio + Δip) · RL.

[0032]

VOUT = (VDD−RL · (I−Δio−Δip)) − (VDD−RL · (I + Δio + Δip)) = 2 · (Δio + Δip) · RL (2) FIG. 2 is a circuit diagram showing a circuit configuration in which the conventional folded cascode type comparator shown in the above document (a) is in the form of an amplifier. As shown in FIG. 2, a conventional folded cascode amplifier is a PMOS transistor constituting a differential amplifier circuit.
In series with (TP1, TP2), NMOS (TN6, TN
7) is different from the differential amplifier of the present embodiment in that it is connected. Here, the NMOSs (TN6, TN7)
Both constitute a constant current source, a constant bias voltage (VGN) is applied to the gate electrode, and the drain electrode is connected to the drain electrode of the PMOS (TP1, TP2).
A source electrode is connected to the ground line.

Hereinafter, the operation of the conventional folded cascode amplifier will be described with reference to FIG. However, in order to simplify the description, it is assumed that the current flowing through the PMOS (TP3) is 2 · I and the current flowing through the NMOSs (TN6, TN73) is 2 · I, and the load resistances (R1, R2)
Are RL. The first input terminal (IN
When the voltage of the input signal applied to P) and the input signal applied to the second input terminal (INM) are the same (V), the currents flowing through the PMOS (TP1) and the PMOS (TP2) are the same (I), The currents flowing through the NMOS (TN1) and the NMOS (TN2) are also the same (2 · I). Therefore, the current flowing through the load resistors (R1, R2) is the same (I), and the potential difference (VOUT) between the first output terminal (OUTP) and the second output terminal (OUTM) is 0 ( VO
UT = 0). Here, the first input terminal (INP)
And the voltage of the input signal applied to the second input terminal (INM) is (V−ΔV).
Δv), the current flowing through the PMOS (TP1) is (I−Δi), and the current flowing through the PMOS (TP2) is (I−Δi).
+ Δi), the current flowing through the load resistance (R1) is (I + Δi), and the current flowing through the load resistance (R2) is (I−
Δi). Therefore, as shown in the following equation (3),
A first output terminal (OUTP) and a second output terminal (OUT
M) is 2 · Δi · RL.

[0034]

VOUT = (VDD−RL · (I−Δi)) − (VDD−RL · (I + Δi)) = 2 · Δi · RL (3) As can be understood from the equations (2) and (3), in the differential amplifier of the present embodiment and the conventional folded cascode amplifier, assuming that the resistance values of the load resistors (R1, R2) are constant, the present embodiment In the differential amplifier of the embodiment, the voltage amplification gain can be increased as compared with the conventional folded cascode amplifier. The current flowing through the entire differential amplifier of the present embodiment is (4 · I), which is the same as the current flowing through the conventional folded cascode amplifier.

The mutual conductance (Gm) of the differential amplifier according to the present embodiment is expressed by the following equation (4).
The mutual conductance (gm (TP1, TP2)) of the differential amplifier circuit composed of S (TP1, TP2) and NMO
It is represented by the sum with the mutual conductance (gm (TN1, TN2)) of the differential amplifier circuit composed of S (TN1, TN2).

[0036]

Gm = gm (TP1, TP2) + gm (TN1, TN2) (4) For example, in the differential amplifier of the present embodiment, it is assumed that the following equation (5) is satisfied.

[0037]

I (TN3) = 2 · I (TP3) Ve (TN1, TN2) = Ve (TP1, TP2) Ve = Vgs−Vth .. (5) where I (TP3) is a PMOS constituting a constant current source
The current value of the constant current supplied by (TP3), I (TN
3) is a current value of a constant current drawn into the NMOS (TN3) constituting the constant current source, Vgs is a gate-source voltage, and Vth is a threshold voltage. In this case, the transconductance (Gm) of the differential amplifier according to the present embodiment is expressed by the following equation (6).

[0038]

Gm (TN1, TN2) = 2 · gm (TP1, TP2) Gm = 3 · gm (TP1, TP2) (6) Amplification gain (G
a) is represented as in the following (7).

[0039]

Ga = Gm · RL = 3 · gm (TP1, TP2) · RL (7) As described above, the differential amplifier according to the present embodiment and the conventional folded amplifier In the cascode amplifier, the load resistance (R
Assuming that the resistance value of (1, R2) is constant, the differential amplifier of the present embodiment can obtain a voltage amplification gain that is about three times that of the conventional folded cascode amplifier. Therefore, in the differential amplifier of the present embodiment, the current consumption,
The voltage amplification gain can be improved without increasing the load impedance. In the differential amplifier according to the present embodiment, as shown in FIG.
1, R2) instead of PMOS (TP10, TP11)
May be used. Further, in the differential amplifier of the present embodiment, a single input signal may be used instead of the differential input signal,
In this case, a reference bias voltage may be applied to the second input terminal (INM). Further, in the differential amplifier according to the present embodiment, a configuration may be adopted in which a single output signal is output instead of outputting a differential output signal.

[0040]

Second Embodiment FIG. 4 is a circuit diagram showing a circuit configuration of a comparator according to a second embodiment of the present invention. The comparator of the present embodiment is different from the differential amplifier of the first embodiment in the configuration of the output stage (load circuit). Hereinafter, the comparator of the present embodiment will be described focusing on the differences. The comparator according to the present embodiment uses a PM instead of the load resistors (R1, R2) shown in FIG.
OS (TP4, TP5) is used. Where PMO
The gate electrode of S (TP4) is connected to the drain electrode of PMOS (TP5), and the gate electrode of PMOS (TP5) is connected to the drain electrode of PMOS (TP4). Further, a PMOS (TP6) is connected between the drain electrodes of the PMOSs (TP4, TP5). The clock signal (CP1) is applied to the gate electrode of the PMOS (TP6).

Hereinafter, the operation of the comparator according to the present embodiment will be described. When the clock signal (CP1) is at a low level (hereinafter, referred to as
It is called L level. )), When the preamplifier operates, P
The MOS (TP6) is on and the input terminals (INP, IP
NM) and the signal current (Δio,
Δip) flows through the PMOSs (TP4 to TP6). For example, as shown in FIG. 4, when the current flowing through the path (L1) is (I + Δio + Δip) and the current flowing through the path (L2) is (I−Δio−Δip) during the preamplifier operation, the PMOS (TP5) is Part of the flowing current is P
It flows through the MOS (TP6). In this case, the PMOS (T
P6), the output terminals (OUTP, OUTP)
M), a potential difference (Vout) occurs. Next, during a latch operation in which the clock signal (CP1) is at a high level (hereinafter, referred to as an H level), the PMOS (TP6) is turned off, and the signal current (Δio, Δip) is changed to the PMOS.
(TP4, TP5). In this case, the potential difference (Vout) between the output terminals (OUTP, OUTM) causes a positive feedback to the PMOSs (TP4, TP5), so that the potential difference (Vout) between the output terminals (OUTP, OUTM).
The amplitude of t) is enlarged. For example, assuming that the second output terminal (OUTM) is at a low voltage and the first output terminal (OUTP) is at a high voltage during the preamplifier operation, the voltage of the second output terminal (OUTM) is used for the latch operation. The PMOS (PT5) applied to the gate electrode operates to be more conductive, and the PMOS (PT4) applied to the gate electrode by the voltage of the first output terminal (OUTP) becomes more non-conductive. So that the first output terminal (OUTP) is at a higher voltage and the second output terminal (OU
TM) has a lower voltage.

FIG. 5 shows the operation of the comparator of this embodiment.
FIG. 9 is a waveform diagram for explaining in comparison with a conventional example. As can be seen from the waveform diagram of FIG. 5, in the comparator of the present embodiment, during the latch operation, the voltages of the first output terminal (OUTP) and the second output terminal (OUTM) quickly reach a predetermined voltage level. , Whereas in a conventional comparator,
Due to insufficient settling at the time of the preamplifier operation, a large amount of time is required until the voltages at the first output terminal (OUTP) and the second output terminal (OUTM) reach a predetermined voltage level during the latch operation. In some cases, an incorrect comparison result was output.

As described above, according to the comparator of the present embodiment, the voltage amplification gain of the differential amplifier can be increased without increasing the current consumption and the load impedance by using the differential amplifier of the first embodiment. Can be improved. As a result, in the comparator of the present embodiment, the operation speed of the comparator can be improved without increasing power consumption, and high speed and low power consumption can be achieved.

Third Embodiment FIG. 6 is a block diagram showing a schematic configuration of a flash A / D converter according to a third embodiment of the present invention. This embodiment is a flash type A / D converter using the comparator of the second embodiment. In the figure, reference numeral 1 denotes a T / H (Track and Hol).
d) circuit, 2 is a reference voltage generation circuit, 3 is a level shift circuit, 4 is a comparator, 5 is a latch circuit, 6 is an encoder, 7 is a bias circuit, and 8 is a timing generation circuit. FIG. 7 is a circuit diagram showing a circuit configuration of the level shift circuit 3, the comparator 4, and the latch circuit 5 shown in FIG.
FIG. 8 is a diagram showing a timing chart of each unit shown in FIG. Hereinafter, the operation of the A / D converter according to the present embodiment will be described with reference to FIGS. Note that n is the number of bits of the A / D converter. The differential analog input signals (AINP, AINM) are sampled by the T / H circuit 1 and commonly input to the input terminals (INP, INM) of the (2 ^{n -1} ) level shift circuits 3 (FIG. 8).

The reference voltage generating circuit 2 generates a voltage (VRT, VRT) whose difference corresponds to the full amplitude of the analog input signal.
VRB) is input, and a voltage is generated by equally dividing the voltage (VRT, VRB) by (2 ⁿ ). Each voltage generated by the reference voltage generation circuit 2 is supplied to a reference voltage input terminal (RP, RM) of the level shift circuit 3.
Is input to each of.

The level shift circuit 3 is composed of two differential amplifying circuits sharing a diode-connected NMOS (TN20, TN21) as a load circuit. here,
A positive-phase input signal input to the input terminal (INP) is applied to a gate electrode of an NMOS (TN22) that constitutes one differential amplifier circuit, and a reference voltage input terminal (RP) is applied to a gate electrode of the NMOS (TN23). ) Is applied. Similarly, a negative-phase reference voltage input to a reference voltage input terminal (RM) is applied to the gate electrode of the NMOS (TN24) that constitutes the other differential amplifier circuit, and the NMOS (TN25)
The negative-phase input signal input to the input terminal (INM) is applied to the gate electrode of the. The level shift circuit 3 converts the voltages input to the input terminals (INP, INM) and the reference voltage input terminals (RP, RM) from the following (8)
And outputs it to the output terminals (OUTP, OUTM).

[0047]

(8) OUTP = (IPv-RPv)-(IMv-RMv) OUTM =-((IPv-RPv)-(IMv-RMv)) (8) Here, IPv is a positive-phase input signal voltage input to the input terminal (INP), IMv is a negative-phase input signal voltage input to the input terminal (INM), and RPv is a reference voltage. The positive-phase reference voltage input to the input terminal (RP), RMv
Is a negative-phase reference voltage input to the reference voltage input terminal (RM).

The output of the level shift circuit 3 is input to the input terminals (INP, INM) of the comparator 4. This comparator 4 is the comparator of the second embodiment,
Compares the magnitudes of the voltages input to the input terminals (INP, INM) and outputs them (see FIG. 8). That is, the comparator 4 converts the level of the positive-phase input signal voltage (IPv) by the level of the positive-phase reference voltage (RPv) and the phase of the negative-phase input signal voltage (IMv) to the negative-phase reference voltage (RM).
v) Compare the magnitude relationship with the voltage level-shifted by the amount. The latch circuit 5 includes a cascode latch circuit 51, RT
The comparator 4 includes a Z latch circuit 52 and a NOR latch circuit 53. The comparator 4 receives the clock signal (CP2, CP3).
Are latched at certain timings, and the comparison result is amplified to the CMOS level. Here, the cascode latch circuit 51 includes a PMOS (TP30 to TP3).
3) and NMOSs (TN30, TN31, TN33). When the clock signal (CP2) is at the H level (during pre-operation), the NMOS (TN33) is turned on, and as described above, the cascode latch circuit 51 (NMOS (TN30) and NMOS (TN3
A potential difference occurs between (1) the drain electrodes). Next, when the clock signal (CP1) is at the L level (during latch operation).
Meanwhile, the NMOS (TN33) is turned off, and the NMOS (TN
N30) and the NMOS (TN31) receive positive feedback due to the potential difference between the output terminals.
0) and the NMOS (TN31) output a voltage in which the potential difference between the output terminals is enlarged to the output terminal (see FIG. 8).

The RTZ latch circuit 52 includes a PMOS (TP
34 to TP36) and NMOS (TN34 to TN3).
7), and when the clock signal (CP3) is at the H level (during the reset operation), the NMOS (TN36, TN36)
37) is on, the PMOS (TP34) is off, and P
The drain electrodes of the MOS (TP35) and the PMOS (TP35) are at the voltage of AGND2. Next, when the clock signal (CP3) is at L level (during latch operation), NM
OS (TN36, TN37) is off, PMOS (TP3
4) is turned on, and the PMOS (TP35) and PMO
S (TP35) is composed of NMOS (TN34) and NMO
The input signal voltage input to the gate electrode of S (TN35) is latched, amplified to the CMOS level, and output (see FIG. 8). The NOR latch circuit 53 includes a NOR circuit (NOR1, NOR2), and holds an output of the RTZ latch circuit 52.

The encoder 6 converts the (2 ^{n -1} ) latch outputs (thermal codes) into n-bit digital data (binary codes). The bias circuit 7 has T
/ H circuit 1, reference voltage generation circuit 2, level shift circuit 3, comparator 4 and other circuits generate necessary bias voltages. The timing generation circuit 8 includes clock timing signals (TH, CP1, CP2, and CP) necessary for circuits such as the T / H circuit 1, the comparator 4, the latch circuit 5, and the encoder 6.
3) is generated. The A / D converter according to the present embodiment can operate at high speed without increasing power consumption by using the comparator 4 according to the second embodiment. A D converter can be realized. In the A / D converter according to the present embodiment, a single input signal may be used instead of the differential input signal. In this case, the level shift circuit 3 is not required, and the comparator 4 Receives a single input signal and a reference voltage.

FIG. 9 is a block diagram showing a schematic configuration of a hard disk drive as an example of a device to which the A / D converter of the present embodiment is applied. As shown in the figure, the hard disk device 100 is connected to a host computer 200 via a disk controller 210. Write data from the host computer 200 is transmitted to the disk controller 210 and the hard disk controller 1
The input signal is input to the encoder / decoder circuit 102 via the “01”, and is converted into a recording code (for example, an 8-9 conversion code) by the encoder / decoder circuit 102. The recording code from the encoder / decoder circuit 102 is amplified by a read / write amplifier 103, and then amplified by a magnetic disk 113.
Is stored. A read signal from the magnetic disk is amplified by a read / write amplifier 103 and an AGC amplifier 104, noise-removed by an active filter 105, and input to an A / D converter 106. The data from the A / D converter 106 is waveform-equalized by a waveform equalizer 107, and then Viterbi decoded (maximum likelihood decoding) by a Viterbi detector 108, and is converted into an original data format by an encoder / decoder circuit 102. The data is output to the host computer 200 side. Here, the waveform equalizer 107 performs PR equalization by digital signal processing. Read / write PLL
The circuit 109 includes an A / D converter 106, a waveform equalizer 107
And a clock signal used in the encoder / decoder circuit 102. Here, the A / D converter 106
This is an A / D converter according to the third embodiment. The hard disk controller 101 controls the voice coil motor driver 110 and the spindle motor driver 111 to perform positioning of the magnetic head 112 at the time of writing and reading the data described above.
4 is controlled. Note that, in FIG.
Controls the entire hard disk device 100.

The hard disk device shown in FIG.
By using the A / D converter of the third embodiment as the converter 106, the speed of the A / D converter 106 can be increased.
Since low power consumption can be achieved, high speed and low power consumption of the entire hard disk drive can be achieved. Each circuit in a dotted frame 120 in FIG. 9 is configured by a single semiconductor integrated circuit device as a signal processing LSI, and similarly, each circuit in a dotted frame 130 in FIG. Is configured by a single semiconductor integrated circuit device. Also, the A / D of the third embodiment
The converter can be applied to a magnetic tape, an optical disk device, a digital video disk, and the like in addition to the hard disk device shown in FIG. Further, it goes without saying that the differential amplifier according to the first embodiment can be used as a general amplifier such as an operational amplifier other than the above-described comparator and A / D converter.

As described above, the invention made by the present inventor is:
Although a specific description has been given based on the above-described embodiment, the present invention is not limited to the above-described embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. (1) According to the present invention, in a differential amplifier, voltage amplification gain can be improved without increasing current consumption and load impedance. (2) According to the present invention, it is possible to increase the operation speed of the comparator without increasing power consumption. (3) According to the present invention, it is possible to improve the operation speed of the A / D converter without increasing power consumption. (4) According to the present invention, it is possible to improve the operation speed of a storage device without increasing power consumption.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a circuit configuration of a differential amplifier according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit configuration in which a conventional folded cascode type comparator is converted into an amplifier type.

FIG. 3 is a circuit diagram showing a circuit configuration of a modified example of the differential amplifier according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram showing a circuit configuration of a comparator according to a second embodiment of the present invention.

FIG. 5 is a waveform chart for explaining an operation of the comparator according to the second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a schematic configuration of a flash A / D converter according to a third embodiment of the present invention.

FIG. 7 is a circuit diagram showing a circuit configuration of a level shift circuit, a comparator, and a latch circuit shown in FIG. 6;

8 is a diagram showing a timing chart of each unit shown in FIG. 7;

FIG. 9 is a block diagram illustrating a schematic configuration of a hard disk device as an example of a device using an A / D converter according to a third embodiment of the present invention.

[Explanation of symbols]

1 ... T / H (Track and Hold) circuit, 2 ...
Reference voltage generation circuit, 3 ... level shift circuit, 4
... Comparator, 5 ... Latch circuit, 6 ... Encoder, 7 ... Bias circuit, 8 ... Timing generation circuit, 51 ... Cascode latch circuit, 52 ... RTZ latch circuit, 53 ... NOR
Latch circuit, 100: Hard disk drive, 101: Hard disk controller, 102: Encoder / decoder circuit, 103: Read / write amplifier, 104: A
GC amplifier, 105: Active filter, 106: A
/ D converter, 107: waveform equalizer, 108: Viterbi detector, 109: read / write PLL circuit, 110 ...
Voice coil motor driver, 111: spindle motor driver, 112: magnetic head, 113: magnetic disk, 114: spindle motor, 115: microcomputer, 1
20, 130 ... Semiconductor integrated circuit device (LSI), 200
... Host computer, 210 ... Disk controller, TP ... P-type MOS transistor, TN ... N-type MOS
Transistor, R: resistor, IN: input terminal, OUT: output terminal, NOR: NOR circuit.

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5J022 AA06 BA05 BA06 CA10 CF01 CF02 CF04 CG01 5J039 DA09 DA10 KK04 KK16 MM03 MM04 NN03 5J066 AA01 AA12 CA35 CA65 FA09 HA10 HA17 HA19 HA25 HA39 KA00 KA02 KA18 KA17 KA18 KA19 KA41 MA17 MA21 ND01 ND11 ND22 ND23 PD02 SA00 SA09 TA01 TA06 5J092 AA01 AA12 CA35 CA65 FA09 HA10 HA17 HA19 HA25 HA39 KA00 KA02 KA06 KA09 KA12 KA17 KA18 KA19 KA32 KA34 KA41 MA17 MA21 TA00 SA09 TA09

Claims (22)

[Claims] A first transistor of a first conductivity type having a control electrode connected to a first input terminal; a control electrode connected to a second input terminal; and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected between the first power supply line and the second power supply line to which the first voltage is applied;
A first load resistor connected to the electrode and the other terminal connected to the first power supply line; and a second terminal connected to the second terminal of the second and fourth transistors.
A second load resistor connected to the electrode and the other terminal connected to the first power supply line. 2. A first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected between a second power supply line to which a voltage of the first and third transistors is applied;
A seventh transistor of a second conductivity type connected to the electrode and having a constant first bias voltage applied to the control electrode; and a first electrode being a second transistor of the second and fourth transistors.
An eighth transistor of a second conductivity type, which is connected to the electrode and a constant first bias voltage is applied to the control electrode; and one terminal is connected to the second electrode of the seventh transistor, and the other is A first load resistor having a terminal connected to the first power supply line, one terminal connected to a second electrode of the eighth transistor, and the other terminal connected to the first power supply line; Second
And a load resistance. 3. The semiconductor device according to claim 1, further comprising an output terminal connected to one terminal of the first load resistor or one terminal of the second load resistor. Differential amplifier. 4. A semiconductor device comprising: a first output terminal connected to one terminal of the first load resistor; and a second output terminal connected to one terminal of the second load resistor. The differential amplifier according to claim 1 or 2, wherein 5. A first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected between the first power supply line and a second power supply line to which a second voltage is applied, a first electrode connected to the first power supply line, and a second electrode connected to the first and second power supply lines. A fifth transistor of the first conductivity type connected to the second electrode of the third transistor; a first electrode connected to the first power supply line; and a second electrode connected to the second and fourth electrodes. And a sixth transistor of a first conductivity type connected to a second electrode of the transistor. 6. A first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected between a second power supply line to which a voltage of the first and third transistors is applied;
A seventh transistor of a second conductivity type connected to the electrode and having a constant first bias voltage applied to the control electrode; and a first electrode being a second transistor of the second and fourth transistors.
An eighth transistor of a second conductivity type, which is connected to the electrode and has a constant first bias voltage applied to the control electrode; a first electrode connected to the first power supply line; and a second electrode connected to the first power supply line. A first transistor connected to a second electrode of the seventh transistor;
A sixth transistor of a first conductivity type, wherein a fifth transistor of a conductivity type and a first electrode are connected to the first power supply line and a second electrode is connected to a second electrode of the eighth transistor. And an active load circuit including a transistor. 7. A second electrode of the fifth transistor,
7. The differential amplifier according to claim 5, further comprising an output terminal connected to a second electrode of the sixth transistor. 8. A first output terminal connected to a second electrode of the fifth transistor, and a second output terminal connected to a second electrode of the sixth transistor.
7. The differential amplifier according to claim 5, further comprising: 9. The current value of the first constant current source is set to (I
1) The differential amplifier according to claim 1, wherein when the current value of the first constant current source is (I2), I1 <I2 is satisfied. . 10. The device according to claim 1, wherein each of the transistors is a MOS transistor.
The differential amplifier according to any one of the above items. 11. A first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected to a second power supply line to which a voltage is applied, a first output terminal connected to second electrodes of the first and third transistors, A second output terminal connected to the second electrodes of the second and fourth transistors; a first electrode connected to the first power supply line; and a second electrode connected to the first output terminal. A fifth transistor, a fifth transistor of a first conductivity type having a control electrode connected to a second output terminal; a first electrode connected to the first power supply line; and a second electrode connected to the first power supply line. A sixth transistor connected to a second output terminal, a sixth transistor of a first conductivity type having a control electrode connected to the first output terminal; a first transistor connected to the first output terminal; And a switching element connected between the output terminal of Comparator according to claim Rukoto. 12. A first transistor of a first conductivity type having a control electrode connected to a first input terminal, a control electrode connected to a second input terminal, and a first electrode connected to the first transistor. A second transistor of a first conductivity type connected to a first electrode of the first transistor, a control electrode connected to a first input terminal, and a second electrode connected to a second electrode of the first transistor A third transistor of a second conductivity type, a fourth transistor having a control electrode connected to a second input terminal and a second electrode connected to a second electrode of the second transistor, A fourth electrode of a second conductivity type, wherein one electrode is connected to a first electrode of the third transistor; a first electrode of the first and second transistors;
A first constant current source connected between the first power supply line to which a voltage is applied, a first electrode of the third and fourth transistors, and a second
A second constant current source connected between a second power supply line to which a voltage of the first and third transistors is applied;
A seventh transistor of a second conductivity type connected to the electrode and having a constant first bias voltage applied to the control electrode; and a first electrode being a second transistor of the second and fourth transistors.
An eighth transistor of a second conductivity type connected to the electrode and having a constant first bias voltage applied to the control electrode, a first output terminal connected to a second electrode of the seventh transistor, A second output terminal connected to a second electrode of the eighth transistor, a fifth electrode connected to the first power supply line, and a second electrode connected to the first output terminal. Wherein a control electrode is connected to a second output terminal, a fifth transistor of a first conductivity type; a first electrode is connected to the first power supply line; and a second electrode is connected to the second output terminal. A sixth transistor of a first conductivity type having a control electrode connected to the first output terminal; a sixth transistor of a first conductivity type having a control electrode connected to the first output terminal; Switching that is connected between terminals and turns on within a predetermined period Comparator, characterized in that it comprises a child. 13. The comparator according to claim 11, wherein the switching element is a transistor to which a clock signal is applied to a control electrode. 14. The current value of said first constant current source is (I
1) When the current value of the first constant current source is (I2), I1 <I2 is satisfied.
A comparator according to any one of claims 13 to 13. 15. The comparator according to claim 11, wherein each of the transistors is a MOS transistor. 16. A T / H circuit for sampling an analog input signal at a predetermined timing, a plurality of comparators for comparing an output voltage from the T / H circuit with a reference voltage, A latch circuit that latches a comparison output; an encoder that outputs a digital signal based on an output from the latch circuit; and a reference voltage generation circuit that supplies a plurality of different reference voltages to the plurality of comparators. , The T / H circuit, the comparator, and the latch circuit,
An A / D converter comprising a timing generation circuit for supplying a clock signal, wherein the comparator is the comparator according to any one of claims 11 to 15. converter. 17. A T / H circuit for sampling a differential analog input signal at a predetermined timing, a positive-phase output voltage from the T / H circuit for a positive-phase reference voltage, and a signal from the T / H circuit. A level shift circuit for level-shifting the negative-phase output voltage by the negative-phase reference voltage, a positive-phase output voltage level-shifted by the positive-phase reference voltage from the level shift circuit, and a negative-phase reference from the level shift circuit A plurality of comparators for comparing the inverted output voltage level-shifted by the voltage, a latch circuit for latching a comparison output from the comparator, and an encoder for outputting a digital signal based on an output from the latch circuit And supplying a plurality of different positive-phase reference voltages and different negative-phase reference voltages to the plurality of comparators. A reference voltage generating circuit for the T / H circuit for a comparator, and a latch circuit,
An A / D converter comprising a timing generation circuit for supplying a clock signal, wherein the comparator is the comparator according to any one of claims 10 to 15. converter. 18. The level shift circuit is a first and a second differential amplifier sharing a pair of diode-connected transistors as a load circuit, wherein a positive-phase output voltage is applied to a first input terminal. A first differential amplifier having a positive-phase reference voltage applied to a second input terminal, a negative-phase reference voltage applied to a first input terminal, and a negative-phase output voltage applied to a second input terminal. 18. The A / D converter according to claim 17, comprising a second differential amplifier. 19. The cascode latch circuit, an RTZ latch circuit, and a NOR circuit connected in cascade.
19. The A / D converter according to claim 16, comprising a latch circuit. 20. A semiconductor integrated circuit device provided with an A / D converter, wherein the A / D converter is the A / D converter according to any one of claims 16 to 19. A semiconductor integrated circuit device characterized by the above-mentioned. 21. A storage device comprising: a storage medium for recording a digital signal; writing means for storing the digital signal in the storage medium; and reading means for reading the digital signal from the recording medium, wherein the reading means 20. A storage device having an A / D converter for converting an analog signal read from the recording medium into a digital signal, wherein the A / D converter is any one of claims 16 to 19. A storage device characterized in that it is an A / D converter. 22. The storage device according to claim 21, wherein said reading means includes a PR system equalizer, an A / D converter, and a maximum likelihood decoding system decoder.