KR100201412B1 - A/d converter - Google Patents

Abstract

The present invention relates to a design technology of an analog / digital converter applied to a disk driver or a PRLM lead channel. In the case of a conventional A / D converter applied to a disk driver or a digital PRML lead channel, it is difficult to make one chip and is designed as a CMOS. The difficulty in doing so ultimately led to a deterioration of the product competitiveness of the applied products.

Accordingly, in order to solve the problem, the present invention receives a single equalized signal V1 that is reproduced and then processed on a recording medium, and outputs two differential signals outp and outn as single differential signal converter 301. )Wow; A first comparator 302 and a second comparator 303 for comparing the original signal and the inverted signal with respect to the difference signal outp and generating corresponding output signals out and outb; Amplifiers 304 and 305 for amplifying the output signals out and outb of the comparators 302 and 303, respectively; It is configured to include the IC-Or Logic Gate 305 for generating the output signal (DOUT) by summing the output signals (POUT), (NOUT) of the dampers (304, 305).

Description

Analog / digital converter

1 is a block diagram of a general disk driver.

2 is a lead channel block diagram of a general PA.

3 is an exemplary block diagram of an analog / digital converter according to the present invention.

4 is a detailed circuit diagram of one embodiment of a single / differential signal converter in FIG.

5 is a detailed circuit diagram of one embodiment of a post amplifier in FIG.

FIG. 6 is a detailed circuit diagram of one embodiment of an IC-LogicGate in FIG.

(A)-(f) of FIG. 7 are waveform diagrams of each part of FIG.

* Explanation of symbols for main parts of the drawings

300: A / D converter 301: single / differential signal converter

302: first comparator 303: second comparator

306: IC-O Logic Gate 307: Buffer

308: Timing recovery unit 309: Viterbi detector

The present invention relates to a design technology of an analog / digital converter applied to a disk driver or a PRLM (Partial Responsable Maximum Likeli-heod) lead channel. The present invention is particularly easy to integrate and designed to be implemented in CMOS. It is about a digital converter.

1 is a block diagram of a general disk driver (for example, IBM 0861).

The data DATAin to be recorded is pre-encoded in a proper manner for recording by the precoder 11 and then recorded in a recording medium 13 such as a magnetic through the write channel of the write driver 12.

In addition, the read channel 13 is read from the recording medium 13 through the lead channel, and then amplified to a predetermined level through the preamplifier 14, and then, through the variable amplifier (VGA) 15, the variable amplification to the level required by the system. do. The amplified signal is equalized through the analog equalizer 16 and then supplied to the A / D converter 17 and the timing recovery unit 18 to recover the clock signal and data.

Here, the A / D converter 17 requires a very high speed although the resolution is about 6 bits. Therefore, in general, one chip, that is, not manufactured as a single semiconductor device is used as an individual device or implemented in bipolar.

2 is a block diagram of a general digital PRML lead channel.

In general, the digital PRML lead channel also requires an A / D converter 26. The digital PRML lead channel has a larger area, more power consumption, and a complicated system configuration than the PRML lead channel implemented in an analog manner. It is defective. However, there is an advantage that it is easy to implement in CMOS and operates at high frequency.

The A / D converter 26 used in the PRML lead channel performs a role of sampling a signal corrected by an analog equalizer and transferring it to the next block by using a clock signal recovered from a PLL such as the timing recovery unit 28. do. Therefore, the A / D converter 26 and the PLL do not operate independently, which may cause a convergence problem in the PRML lead channel configuration.

In addition, the A / D converter 26 has been designed in CMOS so that no example has been implemented with the adaptive equalizer 27. The resolution of the A / D converter 26 is low but high-speed processing is possible. As it is required, it is common to use individual elements implemented in bipolar.

The PRML read channel is mainly used for hard disk drivers. However, in order to apply to a portable digital camcorder, it is necessary to reduce not only power consumption but also the number of devices and to make one chip, so from this point of view, the A / D converter used in the PRML lead channel must be integrated and implemented in CMOS.

As described above, in the case of an A / D converter applied to a conventional disk driver or digital PRML lead channel, it is difficult to form a chip and at the same time difficult to open a CMOS, which ultimately lowers the product competitiveness of the applied product.

Accordingly, an object of the present invention is to provide a new type of analog / digital converter designed to be easily implemented in CMOS and integrated with an equalizer and a timing recovery unit in a disk driver or digital PRML read channel.

3 is an exemplary block diagram of an analog / digital converter according to the present invention. As shown therein, two differential signals (outp) are received by receiving a single equalized signal V1 that has been reproduced on a recording medium and then equalized. and a single / differential signal converter 301 for outputting to (outn); The first comparator 302 for comparing the original signal with respect to the difference signal outp and generating a comparison output signal out and the inverted signal with respect to the difference signal outn are inverted. A second comparator 303 for generating an output signal outb; First and second post amplifiers 304 and 305 which amplify the output signals out and outb of the comparators 302 and 303, respectively; An IC-O logic gate 306 for generating the output signal DOUT by summing the output signals POUT and NOUT of the post amplifiers 304 and 305; A buffer 307 which performs a full scan process on the output signal DOUT of the IC-O logic gate 306; A timing restoring unit (308) for restoring a timing signal from the output signal of the buffer (307); The Viterbi detector 309 recovers user data from the output signal EQOUT of the buffer 307 by using the restored timing signal. When described in detail with reference to the accompanying 4 to 7 as follows.

A single-to-differential block 301 receives a single equalization signal V1 as shown in FIG. 7A output from an analog equalizer of the previous stage and outputs two differential signals outp. output, (outn) In general, a signal output from a PR4 equalizer is classified into subdivisions of -1,0,1. Therefore, in order to compare the signal corresponding to -1, the inverted signal of the original signal is required.

4 illustrates one embodiment of the single / differential signal converter 301.

Here, two NMOSs NM1 and NM2 are differentially coupled so that a DC bias signal DC Bias is supplied to the gate of the other NMOS 42, and the single equalization signal is supplied to the gate of one NMOS 41. (V1) is supplied to generate difference signals outp and outn corresponding to the single equalization signal V1.

Two differential signals outp and outn output from the single / differential signal converter 301 are respectively supplied as reference signals from the first comparator 302 and the second comparator 303 (d). Compared with the threshold voltages V _TH1 and V _TH2 , the comparison output signals out and outb are generated in the comparators 302 and 303, and the threshold voltage V is generated. _TH1 ) and (V _TH2 ) are the same voltage.

The reason why the two comparators 302 and 303 are used and the input signals are compared using the same threshold voltages V _TH1 and V _TH2 is because the first comparator 302 compares the original signal. The comparison output signal out is generated according to the comparison, and the second comparator 303 compares the inverted signal to generate the inverted output signal outb of the output signal out.

The first and second post amplifiers 304 and 305 are supplied with the comparison output signals out and outb to output output signals POUT and NOUT as shown in FIGS. 7B and 7C. Figure 5 shows one embodiment of this post amplifier 304,305.

Using the replica biasing technique, the low level of the transmitted signal is fixed to the reference voltage (V _ref ). For example, when the reference voltage (V _ref ) is 4V and the power supply terminal voltage (V _DD ) is 5V, the swing range of the signal is 4-5V, thereby performing 1V swing.

In general, the comparator applied to the A / D converter is provided with a latch for outputting the compared signal in synchronization with the system clock signal. If it is used as it is, the timing recovery unit generates an error and the speed is slow. D conversion cannot be performed. This is because a convergence problem occurs and an error is generated by using the clock signal output from the timing recovery unit as a clock signal of the comparator.

However, in the present invention, the first and second post amplifiers 304 and 305 detect the minute difference between the signals out and outb output from the comparators 302 and 303 so that the ECL logic By converting and outputting the digital signal at the level, high-speed operation is possible.

The number of amplifiers used in the first and second post amplifiers 304 and 305 may be about 3-5 stages, and the gain of each amplifier is set to about 6. As described in the above description, the swing width of the internal signal is about 1V, and thus only 3-5 stages of connection can swing enough.

The signals POUT, NOUT, which are output from the comparators 302 and 303 and then supplied through the post amplifiers 304 and 305, that is, four output signals a, b, and b ) and (ab) are combined in the ECL (or L) logic gate 306 configured as shown in FIG. 6 to generate an output signal DOUT as shown in FIG. The output swing level of the IC-O logic gate 306 is 1V, and its output signal DOUT is full-swinged as shown in (f) of FIG. Provided as input to PLL and Viterbi detector 309.

As described in detail above, the present invention implements an A / D converter for converting an analog signal equalized in a disk driver or a digital PRML read channel into a digital signal, so that the integration is easy, the number of parts is reduced, and the CMOS is easily implemented. By providing a new A / D converter, not only the area can be reduced but also the power consumption can be reduced.

Claims (3)

A PLM read channel, comprising: a single / differential signal converter 301 which receives the equalized single equalization signal Vl after being reproduced on a recording medium and outputs two differential signals outp and outn; A first comparator 302 and a second comparator 303 for comparing the original signal and the inverted signal with respect to the difference signal outp and generating corresponding output signals out and outb accordingly; First and second post amplifiers 304 and 305 which amplify the output signals out and outb of the comparators 302 and 303, respectively; Analogue, characterized in that it comprises an IC-O logic logic gate 306 for generating the output signal (DOUT) by summing the output signal (POUT), (NOUT) of the post amplifier 304, 305 Digital converter. 4. The single / differential signal converter 301 differentially couples the NMOSs NM4l and NM42 to supply a fixed DC bias to the gate of the NMOS42 and the NMOS NM4l. And the differential signal (outp) and (outn) are generated on the drain side of the NMOS (NM4l) and (NM42) by supplying the single equalization signal (V1) to the gate of the analogue / digital converter. The analog / digital converter according to claim 1, wherein the first and second post amplifiers (304, 305) are configured by varying the number of connected stages of the respective amplifiers according to the required gain.