JP3273887B2 - Parallel A / D converter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a technique effective when applied to a parallel A / D converter having a high speed conversion and a wide input band.

[0002]

2. Description of the Related Art Recently, a recording device such as a hard disk device, a digital VTR, an optical disk, etc.
tial response maximum like
Signal processing, which is referred to as “lihood”, has attracted attention. P
RML signal processing is a technique for increasing the recording density to 1.2 to 1.5 times by signal processing without significantly changing the existing recording / reproducing system. FIG. 6 is a diagram for explaining the outline of the PRML signal processing circuit. As shown in FIG.
The RML signal processing circuit converts the input information sequence from a hard disk controller (HDC) or the like into a recording encoder 6.
01, a precoder 602, and a write compensation circuit 603, to generate a write signal to a recording medium 610 such as a hard disk drive, and from a read signal from the recording medium 610, to generate an automatic gain control circuit (AGC) 604, Pass filter 605, A / D converter 606, PR (partial response) equalizer 607, Viterbi decoding circuit 60
8. It reproduces an output information sequence to a hard disk controller (HDC) or the like via the recording / decoding device 609. The low-pass filter 605 is an A / D converter 606
Eliminates high frequency noise at the output. The PR equalizer 607 causes intentional signal interference between adjacent signals to favor the Viterbi decoding circuit 608, and the Viterbi decoding circuit 608 operates to restore this signal interference. In FIG. 6, a servo signal decoding circuit for tracking,
The timing control circuit and the like of the A / D converter 606 are omitted.

One of the techniques for increasing the speed of the PRML signal processing is to increase the conversion speed of the A / D converter 606. As a method for increasing the conversion speed of the A / D converter, a parallel A / D converter is used as the most suitable conversion method.
The D system is known. When converting an input analog signal into an 8-bit digital signal, the parallel A / D conversion method generates 256 levels of reference voltages by connecting 256 resistors in series, and generates a certain level of analog input signals and The reference voltage is compared simultaneously with the clock by 256 comparators. For example, assuming that a full-scale analog input is 8 V and an analog input voltage is V1, in a state of V1 = 0, all outputs of each comparator are “L”.
ow level ". Here, when a step voltage of 5 V (V1 = 5 V) is applied as the analog input voltage V1, all outputs of the comparators corresponding to the reference voltage of 5 V or less become “High level”, and the comparison of the reference voltage beyond the reference voltage is performed. The output of all the devices becomes “Low level”. The parallel type A /
In the D conversion method, the “High level” is changed to the “Low level”.
Level change point is detected, and 2
Convert to evolutionary code.

The parallel A / D conversion method has a problem that when the number of bits increases, the circuit scale exponentially increases, thereby increasing power consumption. In order to solve the above-described problem, in a conventional parallel A / D converter, as described in the following document I, a differential superposition type logic circuit (Folded Differential L) is used.
ogic), an increase in circuit scale is prevented, and a high-speed parallel A / D converter with low power consumption is realized. I Hiroshi Kimura et al. “10b 300MHz interpolation parallel type AD
Converter ”(IEICE Technical Report ICD92)
-19, PP. 1-8, 1992). As a publication equivalent to the reference I, 1992 Symposium on VLS Circuits Digesto
f Technical Papers PP.94 ~ 95 "A 10b 300Mz Interpol
ated-Parallel A / D Conveter ", US Patent 5,307,067
And JP-A-6-29852. In the parallel A / D converter having the differential superposition type logic circuit described in the document I, the current outputs of a plurality of master comparator latches (MCL) are superimposed and received by one slave latch (SL). Generates Gray code directly. This allows
It is possible to reduce the number of slave latches (SL) and to eliminate all logic gates for detecting a transition of the comparator output.

FIG. 7 is a simplified version of the circuit disclosed in Document I and shows the circuit configuration of a parallel A / D converter having a differential superposition type logic circuit. Note that FIG.
Shows an A / D converter for converting an input analog signal into a 3-bit digital signal. In FIG. 7, 1 is
A series resistor circuit including eight resistors, 5 is a preamplifier, 10
0 to 106 are master comparator latches, 30 to 32
Is a slave latch, 40 to 45 are load resistors having a resistance value R,
50 and 51 are constant current sources having a current value Io, VRT and BRB are reference voltage application terminals, Vin is an input analog voltage, Vre
f1 to 7 are reference voltages generated by the series resistance circuit 1,
D0, D1, and D3 are outputs of the slave latch 30.
In FIG. 7, since a high-potential voltage is applied to the reference voltage application terminal (VRT) and a low-potential voltage is applied to the reference voltage application terminal (VRB), each reference voltage (Vref1) generated by the series resistance circuit 1 is applied. To 7) are Vref1 <Vref
2 <Vref3 Vref4 <Vref5 <Vref6 <
Vref7. Here, the master comparator latches (100 to 106) are connected to a series-connected ECL called an ECL series gate as disclosed in the above-mentioned Document I.
(Emitter Coupled Logic) circuit. As is well known, in the ECL series gate, a constant current source Io connected to a common emitter only to the collector of one of a pair of bipolar transistors having a differential output in accordance with a differential input is substantially provided. An equal current Io flows. Therefore, Vref is applied to each reference voltage (Vref) input to the master comparator latch (100 to 106).
1-7) as the master comparator latch (100
To 106) are defined as follows. One and the other of the differential outputs of the ECL series gate are defined by a positive-phase output and a negative-phase output, respectively. Vin <Vr
If ef, the positive-phase output sinks the current Io. Vin> V
If it is ref, the negative phase output sinks the current Io. Hereinafter, the operation of the A / D converter shown in FIG. 7 will be described. First, the operation when the input analog voltage (Vin) satisfies Vin <Vref1 will be described below. At this time, each positive-phase output of each master comparator latch (100 to 106) sinks the current of Io. Therefore, a total of 2 Io currents, that is, the Io current flowing into the positive-phase output of the master comparator latch 102 and the Io current flowing into the positive-phase output of the master comparator latch 106 flow through the load resistor 40. Is a total of 3I of the Io current flowing into the positive-phase output of the master comparator latch 100, the Io current flowing into the positive-phase output of the master comparator latch 104, and the Io current flowing through the constant current source 51.
The current o flows. Therefore, a voltage drop of (2Io × R) occurs in the load resistance 40, and the load resistance 4
1 has a voltage drop of (3Io × R), and the load resistance 4
The voltages (VD0N, VD0P) generated at 0, 41 are VD
When 0P <VD0N, the voltage difference is (Io × R).
Similarly, a current Io flowing into the positive-phase output of the master comparator latch 105 flows through the load resistor 42. The load resistor 43 has a master comparator latch 10
A total of 2 Io currents, ie, the Io current flowing into one positive-phase output and the Io current flowing into the constant current source 50 flow. Therefore, a voltage drop of (Io × R) occurs in the load resistor 42, and a voltage drop of (2Io × R) occurs in the load resistor 43, and the voltage (VD
1N, VD1P) is VD1P <VD1N, and the voltage difference is (Io × R). Similarly, no current flows through the load resistor 44, and a current of Io flowing into the positive-phase output of the master comparator latch 103 flows through the load resistor 45. Therefore, (Io ×
R), the voltages (VD2N, VD2P) generated at the load resistors 44, 45 are VD2P <VD2N,
The voltage difference is (Io × R). Next, the operation when the input analog voltage (Vin) satisfies Vref1 <Vin <Vref2 will be described below. At this time, the negative-phase output of the master comparator latch 100 sinks the current Io, and the positive-phase outputs of the other master comparator latches 101 to 106 sink the current Io. Therefore, the load resistance 40
The current of Io flowing into the positive-phase output of the master comparator latch 102 and the master comparator latch 10
6 flows into the positive-phase output of the master comparator latch 100, and a current of Io flows into the negative-phase output of the master comparator latch 100. A total of 2 Io of the flowing Io current and the current of the current source Io flowing through the constant current source 51 flows. Therefore, a voltage drop of (3Io × R) occurs in the load resistor 40, and
A voltage drop of (2Io × R) occurs in the load resistor 41, and voltages (VD0N, VD0P) generated in the load resistors 40 and 41.
Is VD0N <VD0P, and the voltage difference is (Io × R)
Becomes In this case, there is no change in the current flowing through the other load resistors (42 to 45) as compared with the case where Vin <Vref1. Next, the input analog voltage (Vin)
Will be described below when Vref2 <Vin <Vref3. At this time, the negative phase outputs of the master comparator latches 100 and 101 sink the current Io,
The positive phase outputs of the other master comparator latches 102 to 106 sink the current Io. Therefore, a total of 2 Io currents, that is, the Io current flowing into the positive-phase output of the master comparator latch 105 and the Io current flowing into the negative-phase output of the master comparator latch 101 flow through the load resistor 42. Is I flowing through the constant current source 50.
o Current will flow. Therefore, a voltage drop of (2Io × R) occurs in the load resistance 42, and the load resistance 43
Causes a voltage drop of (Io × R), and the load resistances 42, 4
3 (VD1N, VD1P) is VD1N <
At VD1P, the voltage difference is (Io × R). Also, in this case, there is no change in the current flowing through the other load resistors (40, 41, 44, 45) as compared with the previous case.

Next, the operation when the input analog voltage (Vin) further changes and Vref4 <Vin will be described below. At this time, the master comparator latch 1
The negative phase outputs of 00 to 102 sink the current Io, and the positive phase outputs of the other master comparator latches 103 to 106 sink the current Io. Therefore, Io flowing into the negative-phase output of the master comparator latch 103 is applied to the load resistor 44.
, And no current flows through the load resistor 45. Therefore, a voltage drop of (Io × R) occurs in the load resistor 45, and the voltage (VD2N,
VD2P) is VD2N <VD2P, and the voltage difference is (Io × R).

FIG. 8 is a diagram showing a voltage change occurring in each load resistor (40 to 45) according to the input analog voltage (Vin) in the A / D converter shown in FIG. FIG.
As is clear from FIG. 5, the voltage (VD
0P), the voltage (VD1P) generated in the load resistor 43, the voltage (VD2P) generated in the load resistor 45, and the gray code itself.

A parallel type A having this differential superposition type logic circuit
With the / D converter, it is possible to realize an A / D converter with high speed and reduced power consumption.

[0009]

However, the present inventor has clarified that the parallel A / D converter having the differential superposition type logic circuit has the following problems. . (1) Since the current output of the master comparator latch is directly applied to the load resistor, the DC operating voltage margin of the master comparator latch is narrowed, and the number of superimposed master comparator latches is limited. That is, as described above, the master comparator latch is configured by a series-connected ECL circuit called an ECL series gate. Therefore, a high DC operating voltage is required in proportion to the number of serially connected bipolar transistors of the ECL series gate. On the other hand, in a parallel A / D converter having a differential superposition type logic circuit, the least significant bit (D0)
Positive input VD0 of the slave comparator latch (30 in Fig. 7)
The outputs of the most master comparator latches are connected to the P and negative phase input VD0N, and the voltage drop at the load resistors 40 and 41 related to the least significant bit (D0) is maximized. Therefore, if the power supply voltage Vcc is 5 volts, in the worst case, the serially connected bipolar transistor of the master comparator latch of the least significant bit (D0) operates in the saturation region, and the signal delay due to the saturation operation or the substrate current causes The problem is the wasteful increase in power consumption. (2) The signal line connecting the current output of the master comparator latch will be long on the chip layout,
This causes an increase in the parasitic capacitance of the signal line, and impairs the high-speed operation of the superimposed logic signal.

That is, the output of the master comparator latch constituted by the ECL series gate is the collector of the bipolar transistor as described above. On the other hand, as shown in FIG. 7, the outputs of the plurality of master comparator latches must be connected to the inputs of the plurality of slave comparator latches via long signal lines. Therefore, a large parasitic capacitance of a long signal line exists in the collector outputs of the plurality of master comparator latches. The time constant of the product of the parasitic capacitance and the load resistance impairs the high-speed operation.

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the prior art, and an object of the present invention is to provide a parallel A / D converter without limiting the number of comparators that can be superimposed. It is an object of the present invention to provide a technology which can operate at high speed and further reduce power consumption. The above object and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows. (1) That is, the parallel A / D converter disclosed in the present application compares a plurality of reference voltages with an input analog signal, and outputs a constant value from a positive-phase output or a negative-phase output according to the magnitude relation. A plurality of master comparators for drawing current, and a plurality of slaves whose inputs are selectively connected to a positive-phase output or a negative-phase output of the plurality of master comparators via a plurality of signal lines to output a desired digital signal A comparator, a plurality of constant current sources connected to each of the plurality of signal lines, and a plurality of load resistors each having one end connected to each of the plurality of signal lines; A DC bias voltage is applied in common to the other end of the load resistor, and the constant current value of the constant current source of the signal line of the input of the slave comparator of the lower bit side of the plurality of constant current sources is set to the slave of the upper bit side. Comparator input signal line Characterized by comprising been set by the constant current value of the current source to a large value. (2) That is, another parallel type A / D converter disclosed in the present application compares a plurality of reference voltages with an input analog signal, and outputs a constant value from a positive-phase output or a negative-phase output in accordance with the magnitude relationship. A plurality of master comparators for sinking current of a value, a plurality of signal lines selectively connected to a positive-phase output or a negative-phase output of the plurality of master comparators, and an input thereof connected to the plurality of signal lines. A plurality of current mirror circuits, one ends of which are connected to the outputs of the plurality of current mirror circuits, the other ends of which are connected to a reference potential point, and a plurality of load resistors whose inputs are connected to the plurality of current mirror circuits. And a plurality of slave comparators connected to the output and the one ends of the plurality of load resistors and outputting a desired digital signal.

[0013]

According to the means of the above (1), a plurality of constant current source circuits and a plurality of load resistors are connected to a signal line connecting the positive-phase output or the negative-phase output of the master comparator to each other. The constant current value of the constant current source of the signal line of the slave comparator input on the lower bit side of the plurality of constant current sources is the same as the constant current source of the signal line of the input signal of the slave comparator on the upper bit side. It is set to a value larger than the constant current value. Therefore, an extremely large voltage drop does not occur even in the load resistance connected to the input of the slave comparator on the lower bit side. Thus, the problem that the DC operating voltage margin of the master comparator is narrow is solved. According to the means of (2), the positive-phase output or the negative-phase output of the plurality of master comparators is input to the plurality of load resistors and the plurality of slave comparators via the inputs and outputs of the plurality of current mirror circuits. Is transmitted to As is well known, the voltage fluctuation of the output of the current mirror circuit does not substantially affect the input side. Therefore, even if a large voltage drop occurs in the load resistance connected to the input of the slave comparator on the lower bit side,
The DC operating voltage margin of the master comparator on the input side of the current mirror circuit is not affected.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In all the drawings for explaining the embodiments, parts having identical functions are given same symbols and their repeated explanation is omitted.

Embodiment 1 FIG. 1 is a diagram showing a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit according to an embodiment (Embodiment 1) of the present invention. In addition, FIG.
An A / D converter for converting an input analog signal into a 3-bit digital signal is shown. FIG. 2 is a diagram showing a circuit configuration of only the least significant bit of the A / D converter shown in FIG. 1 for easy understanding. 1 and 2, 1 is a series resistor circuit, 5 is a preamplifier, 100 to 106 are master comparator latches, 30 to 32 are slave latches, 40 to 45 are load resistors having a resistance value R, and 50 and 51 are current resistors Io. A constant current source, 70 to 75 are constant current sources for the current Is,
80 is a fixed bias, VRT and BRB are reference voltage application terminals, Vin is an input analog voltage, Vref1 to 7 are reference voltages generated by the series resistance circuit 1, VCC is a power supply voltage, D0, D1 and D3 are slave latches 30. Output. Also, the master comparator latches 100 to 106
And the slave latches 30 to 32 are E
It is composed of series-connected ECL circuits called CL series gates. In FIG. 1, exactly the same as FIG.
Since a high-potential voltage is applied to the reference voltage application terminal (VRT) and a low-potential voltage is applied to the reference voltage application terminal (VRB), each reference voltage (Vr) generated by the series resistance circuit 1 is applied.
ef1-7), Vref1 <Vref2 <Vref3
Vref4 <Vref5 <Vref6 <Vref7. Accordingly, as in FIG. 7, the operation of the master comparator latch (100 to 106) is defined as follows, where Vref is each reference voltage (Vref1 to 7) input to the master comparator latch (100 to 106). . If Vin <Vref, the positive-phase output sinks the current Io. If Vin> Vref, the negative-phase output is the current Io
Inhale. Next, the operation of the A / D converter according to the first embodiment will be described. In the first embodiment, the least significant bit (D
0), the current value Is of the constant current source (70, 71) is Is = 4I
o, the current value Is of the middle bit (D1) constant current source (72, 73) is Is = 3Io, and the constant current source (7
(4, 75) is set to Is = 2Io. First, when the input analog voltage (Vin) is Vin <Vre
The operation at f1 will be described below. At this time, since each positive-phase output of each master comparator latch (100 to 106) sinks the current of Io, the constant current source 7
From 0, the current of Io flows into the positive-phase output of the master comparator latch 102, and the current of Io flows into the positive-phase output of the master comparator latch 106.
From the load resistor 40, the remaining 2Io (= 4Io−2I
The current of o) flows.

The current Io flows from the constant current source 71 to the positive-phase output of the master comparator latch 100, and the current Io flows to the positive-phase output of the master comparator latch 104, and the current Io flows into the constant current source 51. Flows into the load resistor 41 from the constant current source 71, so that the remaining current of Io (= 4Io-3Io) flows. Therefore, a voltage of (2Io × R) is generated in the load resistor 40, a voltage of (Io × R) is generated in the load resistor 41, and the voltages (VD0N, VD) generated in the load resistors 40, 41 are generated.
0P) is VD0P <VD0N, and the voltage difference is (Io
× R). Similarly, a current of Io flows from the constant current source 72 to the positive-phase output of the master comparator latch 105, and the remaining 2I flows from the constant current source 72 to the load resistor 42.
The current o (= 3Io-Io) flows. The constant current source 73 supplies the master comparator latch 10
Since the Io current flows into the positive-phase output 1 and the Io current further flows into the constant current source 50, the remaining Io (= 3Io-2Io) flows from the constant current source 73 to the load resistor 43. become. Therefore, the load resistance 42 has (2
Io × R), and the load resistor 43 has (Io × R).
oxR), and the voltages (VD1N, VD1P) generated at the load resistors 42 and 43 are VD1P <VD1N.
The voltage difference is (Io × R). Similarly, constant current source 7
5, the current Io flows into the positive-phase output of the master comparator latch 103, and the constant current source 75
, A current of the remaining Io (= 2Io−Io) flows. Further, from the constant current source 74 to the load resistor 44,
A current of 2Io flows. Therefore, load resistance 4
4 has a voltage difference of (2Io × R), and the load resistor 45 has a voltage difference of (Io × R).
The voltage (VD2N, VD2P) generated at 45 is VD2P
<VD2N, the voltage difference is (Io × R). Next, the input analog voltage (Vin) becomes Vref1 <Vi.
The operation when n <Vref2 is described below. At this time, the current Io flows from the constant current source 70 to the positive-phase output of the master comparator latch 102, and the current Io flows to the positive-phase output of the master comparator latch 106, and further flows to the negative-phase output of the master comparator latch 100. Since the current of Io flows, the remaining current of Io (= 4Io−3Io) flows from the constant current source 70 to the load resistor 40. Further, the current Io flows from the constant current source 71 to the positive-phase output of the master comparator latch 104, and furthermore, the current Io flows into the constant current source 51. Therefore, the remaining current flows from the constant current source 71 to the load resistor 41. A current of 2Io (= 4Io-2Io) flows. Therefore, a voltage of (Io × R) is generated in the load resistor 40, a voltage of (2Io × R) is generated in the load resistor 41, and the voltages (VD0N, VD) generated in the load resistors 40 and 41 are generated.
0P) is VD0N <VD0P, and the voltage difference is (Io ×
R). In this case, other load resistances (42 to
There is no change in the current flowing to 45).

Next, when the input analog voltage (Vin) is V
The operation when ref2 <Vin <Vref3 is described below. At this time, the current Io flows from the constant current source 72 to the positive-phase output of the master comparator latch 105, and furthermore, the current Io flows to the negative-phase output of the master comparator latch 101. Means that the current of the remaining Io (= 3Io-2Io) flows. Further, the current of Io flows from the constant current source 73 into the constant current source 50, and the remaining current of 2Io (= 3Io−Io) flows from the constant current source 73 to the load resistor 43. Therefore, (Io
× R), and the load resistor 43 has (2Io)
× R), and the voltages (VD1N, VD1P) generated in the load resistors 42 and 43 are VD1N <VD1P, and the voltage difference is (Io × R). In this case, there is no change in the current flowing through the other load resistors (40, 41, 44, 45). Next, when the input analog voltage (Vin) is V
The operation when ref4 <Vin will be described below.
At this time, the current Io flows from the constant current source 74 to the negative phase output of the master comparator latch 103, and the constant current source 7
4 to the load resistance 44, the remaining Io (= 2Io−I
The current of o) flows. Further, a current of 2Io flows from the constant current source 75 to the load resistor 45. Accordingly, a voltage of (Io × R) is generated in the load resistor 44, a voltage of (2Io × R) is generated in the load resistor 45, and the voltages (VD2N, VD) generated in the load resistors 44, 45 are generated.
2P) is VD2N <VD2P, and the voltage difference is (Io
× R). That is, according to the first embodiment, the voltage (VD0P) generated in the load resistor 41 and the voltage (VD1) generated in the load resistor 43 according to the input analog voltage (Vin).
P), the voltage (VD2P) generated in the load resistor 45 becomes a gray code as shown in FIG. In the above description, the current value Is of the constant current source (70, 71) is set to Is = 4I
o, the current value Is of the constant current sources (72, 73) is Is = 3I
o, the current value Is of the constant current source (74, 75) is Is = 2I
o, but the constant current source (7
(0, 71) with a constant current source (7
2, 73) is equal to Is = 2Io and the constant current source (7
It is apparent that the current value Is of (4, 75) may be set to Is = Io. As described above, in this embodiment, the current output superimposed when the logic voltage is generated does not directly apply to the load resistors (40 to 45) but flows to the master comparator latches (100 to 106). The difference current between the total current value and the constant current sources (70 to 75) is caused to flow through the load resistors (40 to 45). Since only the difference current flows through the load resistor, a large voltage drop unlike the conventional example does not occur.
106), there is room for a direct current (DC) bias, so that more master comparator latches can be superimposed, and a high-resolution A / D converter can be realized.

[Embodiment 2] FIG. 3 shows a circuit configuration of only a least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (Embodiment 2) of the present invention. FIG. FIG. 3 also shows an A / D converter for converting an input analog signal into a 3-bit digital signal. In the second embodiment, the potential of the signal line to be superimposed is set to (VBB) by the additional transistor 60 including the common base PNP transistors Qp0 and Qp1 to which the bias voltage VBB is applied to the base.
E + VBB).
Here, VBE is the base-emitter voltage of the additional transistor 60, and VBB is the base voltage of the additional transistor 60. In this embodiment of FIG. 3, the potential of the signal line is fixed at (VBE + VBB), but the difference current between the constant current source and the output current of the master comparator latch passes through the emitter-collector path of the additional transistor 60. Flows into the load resistors 40 and 41. Accordingly, the circuit of FIG. 3 basically operates in the same manner as in FIGS. However, in the second embodiment, since the additional transistor 60 is inserted and the potential of the signal line to be superimposed is fixed, the additional transistor 60 forms a time constant of the product of the parasitic capacitance of the signal line and the load resistance. By blocking, it becomes possible to prevent the high-speed property of the superimposed signal from being impaired. In the second embodiment,
It will be easily understood that a P-channel MOS transistor having a gate to which a bias voltage VBB is applied can be used as the additional transistor 60 instead of the PNP transistor.

[Embodiment 3] FIG. 4 shows a circuit configuration of only a least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (Embodiment 3) of the present invention. FIG. FIG. 4 also shows an A / D converter for converting an input analog signal into a 3-bit digital signal. FIG.
In the third embodiment, reference numeral 20 denotes a current mirror circuit, and in the third embodiment, the current output of the superimposed master comparator latches (100 to 106) is
All currents received by the current mirror circuit 20 and superimposed by the current mirror circuit 20 are turned back and applied to the resistive loads (40 to 45). That is, the current of the signal line connected to the output of the master comparator latch flows through the source / drain path of the diode-connected P-channel input MOS transistor with the gate and drain short-circuited, which is the input side of the current mirror circuit. A current proportional to this current flows through the source / drain path of the output P-channel output MOS transistor. For example, assuming that the input analog voltage (Vin) is Vin <Vref1, a total of 2Io of the Io current flowing into the positive-phase output of the master comparator latch 102 and the Io current flowing into the positive-phase output of the master comparator latch 106 is obtained. The current Io is turned back by the current mirror circuit 20 to flow through the load resistor 41, the Io current flowing into the positive output of the master comparator latch 100, the Io current flowing into the positive output of the master comparator latch 104, and the constant current. The current of Io flowing into the source 51 and the current of 3Io in total,
The current is reflected by the current mirror circuit 20 and flows to the load resistor 40. Therefore, the voltage generated at the load resistor 40 is (VD0N) equal to the voltage of (3Io × R), and the voltage generated at the load resistor 41 is (VDOP) equal to (2
Io × R), and the voltages (VD0N, VD0P) generated at the load resistors 40, 41 are VD0P <VD0N.
The voltage difference is (Io × R). The input side of the current mirror circuit 20 is composed of a diode-connected active element such as a gate-drain short-circuited diode-connected MOS transistor or a base-collector short-circuited diode-connected bipolar transistor. Since the diode-connected active element operates as a non-linear element, the voltage drop becomes non-linear rather than proportional to the current. As a result, since this diode-connected active element operates as a voltage clamp element, a large voltage drop unlike when directly driving a load resistor does not occur. On the other hand, a voltage drop occurs in the load resistors 40 and 41 on the output side of the current mirror circuit 20 in proportion to the current, or the output side of the current mirror circuit 20 does not substantially affect the input side. Therefore, also in the third embodiment, similarly to the case where only the difference current shown above is turned back, the master comparator latch (1
00 to 106) to allow for the DC bias.
More master comparator latches (100-10
6) can be superimposed.

[Embodiment 4] FIG. 5 is a diagram showing an example of a circuit configuration of a master comparator latch (100 to 106) used in the parallel A / D converter according to the above-described embodiment of the present invention. In the fourth embodiment, the master comparator latches (100 to 106) of the second embodiment are used as Bi-
The master comparator latches (100 to 106) using a CMOS process are used. In FIG. 5, the clock signal (CLK1) is “High level”.
, The transistor (Q5) is turned on, and based on the output signal from the preamplifier 5 and the inverted output signal, either the bipolar transistor (Q1) or the bipolar transistor (Q2) is turned on. When turned on, the current of Io is sucked. When the clock signal (CLK2) is at “High level”, the latch mode is set, and the transistor Q6 is turned on to latch the state of the bipolar transistor (Q1 or Q2) turned on in the amplifier mode.
Thus, the transistors (Q5, Q6) and the transistors (Q1, Q2) constitute an ECL series gate. In this case, the transistors (M1 and M2) activated in the latch mode are generally constituted by bipolar transistors.
It is composed of transistors. If the transistor activated in the latch mode is a bipolar transistor having a vertical structure, a large collector-substrate capacitance (C
The operation speed is reduced due to sub).

On the other hand, if the transistor activated in the latch mode is a MOS transistor having a lateral structure, the capacitance between the drain and the substrate becomes extremely small, and the operation speed is improved.

It is needless to say that the parallel A / D converter shown in each of the above embodiments is applicable to the PRML signal processing shown in FIG.

As described above, the present invention has been specifically described based on the embodiments. However, it is needless to say that the present invention is not limited to the above-described embodiments and can be variously modified without departing from the gist of the present invention.

[0024]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in a parallel A / D converter, power consumption can be reduced and more comparators can be superimposed.

(2) According to the present invention, in the parallel A / D converter, it is possible to eliminate the influence of the parasitic capacitance of the signal line, thereby preventing the superimposed signal from being performed at high speed. It becomes possible.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit according to an embodiment (embodiment 1) of the present invention.

FIG. 2 is a diagram showing a circuit configuration of only the least significant bit of the A / D converter shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of only a least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (Embodiment 2) of the present invention.

FIG. 4 is a diagram showing a circuit configuration of only a least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (Embodiment 3) of the present invention.

FIG. 5 is a master comparator latch (100 to 106) used in the parallel A / D converter of each embodiment of the present invention.
FIG. 3 is a diagram showing an example of the circuit configuration of FIG.

FIG. 6 is a diagram schematically illustrating a PRML signal processing circuit.

FIG. 7 is a diagram showing a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit.

8 is a diagram showing a voltage change occurring at each load resistor according to an input analog voltage (Vin) in the A / D converter shown in FIG.

[Explanation of symbols]

1: a series resistance circuit, 5: a preamplifier, 100 to 106 ...
Master comparator latch, 11 bipolar transistor, 12 MOS transistor, 20 current mirror circuit, 30-32 slave latch, 40-45
Load resistance, 50, 51, 70 to 75, I1 ... constant current source,
60: Cascode transistor, 80: Fixed bias,
Vin: input analog signal, Vref1 to Vref7 ...
Reference voltage, Q1 to Q6: bipolar transistor, M
1, M2... MOS transistors, CLK1 to CLK2.
Clock signals, D0, D1, D2... Output digital signals.

────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Sakae Imaizumi 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo Inside Hitachi Ultra-SII Engineering Co., Ltd. (72) Inventor Tatsuharu Matsuura Tokyo 5-20-1, Josuihonmachi, Kodaira-shi, Tokyo In the Semiconductor Division, Hitachi, Ltd. (72) Inventor Hisashi Tsukasa Okazawa 5-2-1, Josuihoncho, Kodaira-shi, Tokyo Hitachi ULSI Engineering (56) References JP-A-6-29852 (JP, A) JP-A-58-10922 (JP, A) JP-A-6-188735 (JP, A) (58) Fields studied (Int .Cl. ⁷ , DB name) H03M 1/00-1/88

Claims (6)

(57) [Claims] A plurality of master comparators for comparing a plurality of reference voltages with an input analog signal and sinking a constant value current from a positive-phase output or a negative-phase output in accordance with the magnitude relationship; An input is selectively connected to a positive-phase output or a negative-phase output of the comparator via a plurality of signal lines, and a plurality of slave comparators for outputting a desired digital signal are connected to each of the plurality of signal lines. A plurality of constant current sources, and a plurality of load resistors each having one end connected to each of the plurality of signal lines, wherein the plurality of slave comparators output the desired digital signal.
The plurality of signal lines are provided in a number corresponding to the number of bits, and the plurality of signal lines are each constituted by a pair of signal lines of a pair.
And the individual master comparators of the plurality of master comparators
Is the corresponding slave of the plurality of slave comparators.
And a DC bias voltage is commonly applied to the other ends of the plurality of load resistors, and a lower bit slave comparison of the plurality of constant current sources is performed. The constant current value of the constant current source of the signal line of the comparator input is set to a value larger than the constant current value of the constant current source of the signal line of the input signal of the slave comparator on the upper bit side. A / D converter. 2. The plurality of signal lines are connected to the one ends of the plurality of resistors and the inputs of the plurality of slave comparators via a plurality of additional transistors having a common base. 2. The parallel A / D converter according to 1. 3. The parallel A / D converter according to claim 1, wherein said plurality of master comparators and said plurality of slave comparators include an ECL series gate circuit. 4. A plurality of master comparators for comparing a plurality of reference voltages with an input analog signal and sinking a constant current from a positive-phase output or a negative-phase output in accordance with the magnitude relation between the plurality of reference voltages and the plurality of masters. A plurality of signal lines selectively connected to the positive-phase output or the negative-phase output of the comparator; a plurality of current mirror circuits whose inputs are connected to the plurality of signal lines; A plurality of load resistors connected to an output of the circuit, the other end of which is connected to a reference potential point; and an input connected to the output of the plurality of current mirror circuits and the one end of the plurality of load resistors. Karentomi of and a plurality of slave comparator for outputting a digital signal Ri Na, the plurality of slave comparators and the plurality
Each of the error circuits is a bit of the desired digital signal.
The signal lines are provided in a number corresponding to the number, and the plurality of signal lines are constituted by a pair of signal lines, each set of two.
And the individual master comparators of the plurality of master comparators
Corresponds to the corresponding one of the plurality of current mirror circuits.
Connected to the rent mirror circuit via each pair of signal lines described above.
Individual current mirrors of the plurality of current mirror circuits.
Error circuit corresponds to one of the plurality of slave comparators.
A parallel A / D converter, which is connected to a slave comparator . 5. The latch circuit according to claim 1, wherein in the ECL series gate circuit of the plurality of master comparators, positive feedback of the latch is performed by a pair of MOS transistors having a horizontal structure. 2. A parallel A / D converter described in 1. above. 6. A signal processing circuit for reading and processing a signal from a magnetic recording medium, wherein said signal processing circuit is an A / D converter for A / D converting said read signal. A signal processing circuit comprising the parallel A / D converter according to claim 1.