JPH08279751A - Parallel a/d converter - Google Patents

Abstract

PURPOSE: To provide a high-speed parallel A/D converter with power consumption reduced by setting the current value of a constant current source for the input signal line of a slave comparator on the low-order bit side among plural constant current sources at a value larger than that on the high-order bit side. CONSTITUTION: When an input analog voltage Vin is set on the condition of Vref<Vin<Vref2 , the current of I0 flows from a constant current source 70 into the positive phase output of a master comparator latch(ML) 102, the current of I0 flows into the positive phase output of an ML 106 and the current of I0 flows into the negative phase output of an ML 100 so that the remaining current of I0 (=4I0 -3I0 ) flows from the constant current source 70 to a load resistor 40. Besides, the current of I0 flows from a constant current source 71 into the positive phase output of an ML 104 and further, the current of I0 flows into a constant current force 51 so that the remaining current of 2I0 (=4I0 -2I0 ) flows from the constant current source 71 to a load resistor 41. Therefore, the voltage of I0 ×R is generated at the load resistor 40, the voltage of 2I0 ×R is generated at the load resistor 41, the voltage (VDON and VDOP) generated at the load resistors 40 and 41 are set on the condition of VDON<VDOP, and voltage difference becomes I0 ×R. In this case, the current to flow to other load resistors 42-45 is not changed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an A / D converter, and more particularly to a technique which is effective when applied to a parallel type A / D converter having a high input speed and a wide input band.

[0002]

2. Description of the Related Art Recently, recording devices such as hard disk devices, digital VTRs, and optical disks have been used for PRML (par)
tial response maximum like
Signal processing called "lihood" has been attracting attention. P
The RML signal processing is a technique for increasing the recording density by 1.2 to 1.5 times by the signal processing without largely changing the existing recording / reproducing system. FIG. 6 is a diagram for explaining the outline of the PRML signal processing circuit. As shown in FIG.
The RML signal processing circuit uses the recording encoder 6 from the input information sequence from the hard disk controller (HDC) or the like.
01, a precoder 602, and a write compensation circuit 603 to generate a write signal to a recording medium 610 such as a hard disk device, and an automatic gain control circuit (AGC) 604 to a low frequency range from a read signal from the recording medium 610. Pass filter 605, A / D converter 606, PR (partial response) equalizer 607, Viterbi decoding circuit 60
8. The output information sequence to the hard disk controller (HDC) or the like is reproduced via the recording / decoding device 609. The low pass filter 605 is an A / D converter 606.
Remove high frequency noise from the output of. The PR equalizer 607 causes the intentional signal interference between the adjacent signals, which is convenient for the Viterbi decoding circuit 608, and the Viterbi decoding circuit 608 operates to restore this signal interference. In FIG. 6, a servo signal decoding circuit for tracking,
The timing control circuit and the like of the A / D converter 606 are omitted.

As one of the methods for speeding up the PRML signal processing, speeding up of the conversion speed of the A / D converter 606 can be mentioned. As a method for increasing the conversion speed of the A / D converter, the parallel A / D converter is the most suitable conversion method.
The D method is known. When converting an input analog signal into an 8-bit digital signal, in the parallel A / D conversion method, 256 resistors are connected in series to generate a 256-level reference voltage, and an analog input signal of a certain level and The reference voltage of (1) is simultaneously compared with 256 comparators in synchronization with the clock. For example, assuming that the full-scale analog input is 8 V and the analog input voltage is V1, all outputs of the comparators are "L" when V1 = 0.
ow level ”. Here, when a step voltage of 5V (V1 = 5V) is applied as the analog input voltage V1, the outputs of the comparators corresponding to the reference voltage of 5V or less are all at “High level”, and the comparison of the reference voltage higher than that is performed. All instrument outputs are "Low level". The parallel type A /
In the D conversion method, from this “High level” to “Low level”
2) using the encoder circuit to detect the change point of "level"
Convert to evolution code.

The parallel type A / D conversion system has a problem that the circuit scale exponentially increases as the number of bits increases, thereby increasing power consumption. In order to solve the above-mentioned problems, in a conventional parallel A / D converter, as described in Document I below, a differential superposition type logic circuit (Folded Differential L) is used.
The realization of a high-speed parallel A / D converter with low power consumption by preventing the increase in circuit scale. I Hiroshi Kimura et al. "10b 300MHz interpolation parallel type AD
Converter "(IEICE Technical Committee Report ICD92
-19, PP.1-8, 1992). The same presentation as Reference I is given in 1992 Symposium on VLS Circuits Digesto
f Technical Papers PP.94 ~ 95 "A 10b 300Mz Interpol
ated-Parallel A / D Conveter ", US Pat. No. 5,307,067
And JP-A-6-29852. In the parallel type A / D converter having the differential superposition type logic circuit described in Document I, the current outputs of a plurality of master comparator latches (MCL) are superposed and received by one slave latch (SL). Generate gray code directly with. This allows
It is possible to reduce the number of slave latches (SL) and eliminate all the logic gates for detecting the transition of the comparator output.

FIG. 7 is a simplified version of the circuit disclosed in Document I and shows the circuit configuration of a parallel A / D converter having a differential superposition type logic circuit. Note that FIG.
Shows an A / D converter that converts an input analog signal into a 3-bit digital signal. In FIG. 7, 1 is
Series resistor circuit including 8 resistors, 5 preamplifier, 10
0 to 106 are master comparator latches, 30 to 32
Is a slave latch, 40 to 45 are load resistors having a resistance value R,
50 and 51 are constant current sources having a current value Io, VRT and BRB are reference voltage application terminals, Vin is an input analog voltage, and Vre.
f1 to 7 are reference voltages generated by the series resistance circuit 1,
D0, D1 and D3 are outputs of the slave latch 30.
In FIG. 7, since a high potential voltage is applied to the reference voltage applying terminal (VRT) and a low potential voltage is applied to the reference voltage applying terminal (VRB), each reference voltage (Vref1) generated by the series resistance circuit 1 is applied. ~ 7) is Vref1 <Vref
2 <Vref3 Vref4 <Vref5 <Vref6 <
It becomes Vref7. Here, the master comparator latches (100 to 106) are connected in series, called ECL series gates, as disclosed in the above-mentioned document I.
(Emitter Coupled Logic) circuit. As is well known, in the ECL series gate, a constant current source Io is connected to a common emitter only in the collector of one of a pair of differential output bipolar transistors according to a differential input. An equal current Io flows. Therefore, Vref is applied to each reference voltage (Vref) input to the master comparator latch (100 to 106).
1 to 7) as a master comparator latch (100
~ 106) operations are defined as follows. Note that one and the other of the differential outputs of the ECL series gate are defined by the positive phase output and the negative phase output, respectively. Vin <Vr
If ef, the positive phase output absorbs the current Io. Vin> V
If ref, the negative-phase output absorbs the current Io. The operation of the A / D converter shown in FIG. 7 will be described below. First, the operation when the input analog voltage (Vin) is Vin <Vref1 will be described below. At this time, the positive phase output of each master comparator latch (100 to 106) absorbs the current Io. Therefore, a total of 2Io of the current of Io flowing into the positive phase output of the master comparator latch 102 and the current of Io flowing into the positive phase output of the master comparator latch 106 flows through the load resistor 40, and the load resistor 41 also flows through the load resistor 41. Is a total of 3I of the current Io flowing into the positive phase output of the master comparator latch 100, the current Io flowing into the positive phase output of the master comparator latch 104, and the current Io flowing into the constant current source 51.
A current of o will flow. Therefore, a voltage drop of (2Io × R) occurs in the load resistance 40, and the load resistance 4
A voltage drop of (3Io × R) occurs at 1 and load resistance 4
The voltage (VD0N, VD0P) generated at 0, 41 is VD
When 0P <VD0N, the voltage difference is (Io × R).
Similarly, a current of Io flowing into the positive phase output of the master comparator latch 105 flows through the load resistor 42. In addition, the load resistor 43 has a master comparator latch 10
A total of 2 Io of the Io current flowing into the positive phase output of 1 and the Io current flowing through the constant current source 50 will flow. Therefore, a voltage drop of (Io × R) occurs in the load resistor 42, a voltage drop of (2Io × R) occurs in the load resistor 43, and a voltage (VD
1N, VD1P), VD1P <VD1N, and the voltage difference is (Io × R). Similarly, no current flows through the load resistor 44, and a current Io that flows into the positive phase output of the master comparator latch 103 flows through the load resistor 45. Therefore, (Io ×
R) voltage drop occurs, and the voltages (VD2N, VD2P) generated in the load resistors 44 and 45 are VD2P <VD2N,
The voltage difference is (Io × R). Next, the operation when the input analog voltage (Vin) is Vref1 <Vin <Vref2 will be described below. At this time, the negative phase output of the master comparator latch 100 absorbs the current Io, and the positive phase outputs of the other master comparator latches 101 to 106 absorb the current Io. Therefore, the load resistance 40
The current of Io flowing into the positive phase output of the master comparator latch 102 and the master comparator latch 10
A total of 3 Io of the Io current flowing into the positive phase output of 6 and the Io current flowing into the negative phase output of the master comparator latch 100 flows, and the load resistor 41 receives the positive phase output of the master comparator latch 104. A total of 2 Io of the flowing Io current and the current of the current source Io flowing through the constant current source 51 will flow. Therefore, a voltage drop of (3Io × R) occurs in the load resistor 40, and
A voltage drop of (2Io × R) occurs in the load resistance 41, and a voltage (VD0N, VD0P) generated in the load resistances 40 and 41.
Is VD0N <VD0P, and the voltage difference is (Io × R)
Becomes Further, in this case, there is no change in the current flowing through the other load resistors (42 to 45) as compared with the case of Vin <Vref1. Next, input analog voltage (Vin)
However, the operation when Vref2 <Vin <Vref3 is described below. At this time, the negative phase outputs of the master comparator latches 100 and 101 absorb the current Io,
The positive phase outputs of the other master comparator latches 102 to 106 absorb the current Io. Therefore, a total of 2 Io of the current Io flowing into the positive phase output of the master comparator latch 105 and the current Io flowing into the negative phase output of the master comparator latch 101 flows through the load resistor 42, and the load resistor 43 also flows through the load resistor 43. Is I flowing through the constant current source 50
o Current will flow. Therefore, a voltage drop of (2Io × R) occurs in the load resistance 42, and the load resistance 43
A voltage drop of (Io × R) occurs at the load resistors 42, 4
The voltage (VD1N, VD1P) generated at 3 is VD1N <
At VD1P, the voltage difference is (Io × R). Further, in this case, there is no change in the current flowing through the other load resistors (40, 41, 44, 45) as compared with the above case.

Next, the operation when the input analog voltage (Vin) further changes and Vref4 <Vin is satisfied will be described below. At this time, master comparator latch 1
The negative phase outputs of 00 to 102 absorb the current Io, and the positive phase outputs of the other master comparator latches 103 to 106 absorb the current Io. Therefore, Io that flows into the negative phase output of the master comparator latch 103 flows into the load resistor 44.
Current flows, and no current flows through the load resistor 45. Therefore, a voltage drop of (Io × R) occurs in the load resistance 45, and the voltage (VD2N,
VD2P) is VD2N <VD2P, and the voltage difference is (Io × R).

FIG. 8 is a diagram showing a voltage change occurring in each load resistance (40 to 45) in accordance with the input analog voltage (Vin) in the A / D converter shown in FIG. FIG.
As is clear from the figure, the voltage (VD
0P), the voltage generated in the load resistor 43 (VD1P), the voltage generated in the load resistor 45 (VD2P), and the gray code itself.

Parallel type A having this differential superposition type logic circuit
With the / D converter, it is possible to realize an A / D converter that is high-speed and has reduced power consumption.

[0009]

However, it was clarified by the study of the present inventor that the parallel type A / D converter having the differential superposition type logic circuit has the following problems. . (1) Since the current output of the master comparator latch is directly applied to the load resistor, the DC operating voltage margin of the master comparator latch is narrowed and the number of master comparator latches that can be superimposed is limited. That is, as described above, the master comparator latch is composed of ECL circuits connected in series called ECL series gates. Therefore, a high DC operating voltage is required in proportion to the number of ECL series gate bipolar transistors connected in series. On the other hand, in the parallel A / D converter having the differential superposition type logic circuit, the least significant bit (D0)
Slave comparator latch (30 in Figure 7) positive phase input VD0
The outputs of the most master comparator latches are connected to the P and negative-phase inputs VD0N, and the voltage drop at the load resistors 40 and 41 related to the least significant bit (D0) becomes the maximum. Therefore, if the power supply voltage Vcc is 5 V, in the worst case, the serial connection bipolar transistor of the master comparator latch of the least significant bit (D0) operates in the saturation region, and the signal delay or substrate current due to the saturation operation causes An unnecessary increase in power consumption is a problem. (2) The signal line connecting the current output of the master comparator latch will be laid out for a long time on the chip layout.
This causes an increase in the parasitic capacitance of the signal line and impairs the high speed of the superimposed logic signal.

That is, the output of the master comparator latch composed of the ECL series gate is the collector of the bipolar transistor as described above. On the other hand, as shown in FIG. 7, the outputs of the master comparator latches must be connected to the inputs of the slave comparator latches via long signal lines. Therefore, there is a large parasitic capacitance of the long signal line at the collector outputs of the plurality of master comparator latches. The time constant of the product of this parasitic capacitance and the load resistance impairs high speed operation.

The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to limit the number of comparators that can be superposed in a parallel type A / D converter. Another object of the present invention is to provide a technique capable of reducing power consumption at high speed. The above object and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0012]

Of the inventions disclosed in the present application, a representative one will be briefly described below.
It is as follows. (1) That is, the parallel A / D converter disclosed in the present application compares a plurality of reference voltages with an input analog signal, and outputs a constant value from a positive phase output or a negative phase output according to the magnitude relationship. A plurality of master comparators that absorb current, and a plurality of slaves that output desired digital signals by selectively connecting the inputs to the positive-phase output or negative-phase output of the plurality of master comparators through a plurality of signal lines A comparator, a plurality of constant current sources connected to each of the plurality of signal lines, and a plurality of load resistors having one end connected to each of the plurality of signal lines, A DC bias voltage is commonly applied to the other end of the load resistor, and the constant current value of the constant current source of the signal line of the slave comparator on the lower bit side of the plurality of constant current sources is the slave on the upper bit side. Of the signal line of the input of the comparator Characterized by comprising been set by the constant current value of the current source to a large value. (2) That is, another parallel A / D converter disclosed in the present application compares a plurality of reference voltages with an input analog signal, and outputs a constant value from a positive phase output or a negative phase output according to the magnitude relationship. A plurality of master comparators that absorb a current of a value, a plurality of signal lines that are selectively connected to the positive phase output or the negative phase output of the plurality of master comparators, and their inputs are connected to the plurality of signal lines. A plurality of current mirror circuits, a plurality of load resistors whose one end is connected to the outputs of the plurality of current mirror circuits, and the other end of which is connected to a reference potential point, and whose inputs are the above-mentioned plurality of current mirror circuits. A plurality of slave comparators connected to the output and the one ends of the plurality of load resistors and outputting a desired digital signal are provided.

[0013]

According to the above-mentioned means (1), a plurality of constant current source circuits and a plurality of load resistors are connected to a signal line connecting the positive phase output or the negative phase output of the master comparator to each other. The constant current value of the constant current source of the input signal line of the slave comparator on the lower bit side of the multiple constant current sources is the same as that of the constant current source of the input signal line of the slave comparator on the higher bit side. It is set to a value larger than the constant current value. Therefore, an extremely large voltage drop does not occur even in the load resistance connected to the input of the slave comparator on the lower bit side. Thus, the problem that the DC operating voltage margin of the master comparator is narrow is solved. According to the means of the above (2), the positive phase output or the negative phase output of the plurality of master comparators is input to the plurality of load resistors and the plurality of slave comparators via the inputs and outputs of the plurality of current mirror circuits. Be transmitted to. As is well known, the voltage fluctuation of the output of the current mirror circuit does not substantially affect the input side. Therefore, even if a large voltage drop occurs in the load resistance connected to the input of the slave comparator on the lower bit side,
The DC operating voltage margin of the master comparator on the input side of the current mirror circuit is not affected.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings. In all the drawings for explaining the embodiments, parts having the same function are designated by the same reference numerals, and repeated description thereof will be omitted.

[Embodiment 1] FIG. 1 is a diagram showing a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit which is an embodiment (Embodiment 1) of the present invention. In addition, FIG.
2 illustrates an A / D converter that converts an input analog signal into a 3-bit digital signal. In order to facilitate understanding, FIG. 2 is a diagram showing a circuit configuration of only the least significant bit of the A / D converter shown in FIG. In FIGS. 1 and 2, 1 is a series resistor circuit, 5 is a preamplifier, 100 to 106 are master comparator latches, 30 to 32 are slave latches, 40 to 45 are load resistors having a resistance value R, and 50 and 51 are current Io. Constant current source, 70 to 75 are constant current sources of current Is,
80 is a fixed bias, VRT and BRB are reference voltage application terminals, Vin is an input analog voltage, Vref1 to 7 are reference voltages generated by the series resistance circuit 1, VCC is a power supply voltage, and D0, D1 and D3 are slave latches 30. Is the output. Further, the master comparator latches 100 to 106
And the slave latches 30 to 32 are the same as E in the document I.
It consists of ECL circuits connected in series called CL series gates. In FIG. 1, exactly the same as in FIG.
Since a high potential voltage is applied to the reference voltage application terminal (VRT) and a low potential voltage is applied to the reference voltage application terminal (VRB), each reference voltage (Vr generated by the series resistance circuit 1
ef1 to 7) are Vref1 <Vref2 <Vref3.
Vref4 <Vref5 <Vref6 <Vref7. Therefore, as in the case of FIG. 7, the operation of the master comparator latch (100 to 106) is defined as follows with Vref being each reference voltage (Vref1 to 7) input to the master comparator latch (100 to 106). . If Vin <Vref, the positive phase output absorbs the current Io. If Vin> Vref, the negative phase output is the current Io.
Inhale. Next, the operation of the A / D converter of the first embodiment will be described. In the first embodiment, the least significant bit (D
The current value Is of the constant current source (70, 71) of (0) is Is = 4I.
o, the current value Is of the constant current source (72, 73) of the middle bit (D1) is Is = 3Io, the constant current source (7) of the upper bit (D2)
4, 75) current value Is is set to Is = 2Io. First, the input analog voltage (Vin) is Vin <Vre
The operation when it is f1 will be described below. At this time, the positive phase output of each master comparator latch (100 to 106) absorbs the current Io, so that the constant current source 7
From 0, the current of Io flows into the positive phase output of the master comparator latch 102, and the current of Io flows into the positive phase output of the master comparator latch 106, and the constant current source 70
To the load resistor 40, the remaining 2Io (= 4Io-2I
The current of o) will flow.

Further, the current Io flows from the constant current source 71 to the positive phase output of the master comparator latch 100, the current Io flows to the positive phase output of the master comparator latch 104, and the current Io flows to the constant current source 51. Flows into the load resistor 41 from the constant current source 71, the remaining current of Io (= 4Io−3Io) flows. Therefore, a voltage of (2Io × R) is generated in the load resistor 40, a voltage of (Io × R) is generated in the load resistor 41, and a voltage (VD0N, VD) is generated in the load resistors 40 and 41.
0P) is VD0P <VD0N, and the voltage difference is (Io
XR). Similarly, a current of Io flows from the constant current source 72 to the positive phase output of the master comparator latch 105, and the remaining 2I flows from the constant current source 72 to the load resistor 42.
A current of o (= 3Io-Io) will flow. In addition, the constant current source 73 to the master comparator latch 10
Since the Io current flows into the positive phase output of No. 1 and the Io current further flows into the constant current source 50, the remaining current Io (= 3Io-2Io) flows from the constant current source 73 to the load resistor 43. become. Therefore, (2
A voltage of (Io × R) is generated, and (I
The voltage (VD1N, VD1P) generated in the load resistors 42 and 43 is VD1P <VD1N,
The voltage difference is (Io × R). Similarly, constant current source 7
5, the current of Io flows into the positive phase output of the master comparator latch 103, and the constant current source 75 loads the load resistor 45.
The remaining current of Io (= 2Io-Io) will flow through. Further, from the constant current source 74 to the load resistor 44,
A current of 2 Io will flow. Therefore, load resistance 4
4 has a voltage difference of (2Io × R), and the load resistor 45 has a voltage difference of (Io × R).
The voltage (VD2N, VD2P) generated at 45 is VD2P
<VD2N, the voltage difference is (Io × R). Next, when the input analog voltage (Vin) is Vref1 <Vi
The operation when n <Vref2 is described below. At this time, the current Io flows from the constant current source 70 to the positive phase output of the master comparator latch 102, the current Io flows to the positive phase output of the master comparator latch 106, and further to the negative phase output of the master comparator latch 100. Since the current of Io flows in, the remaining current of Io (= 4Io−3Io) flows from the constant current source 70 to the load resistor 40. Further, since the current Io flows from the constant current source 71 to the positive phase output of the master comparator latch 104, and further the current Io flows into the constant current source 51, the remaining current from the constant current source 71 to the load resistor 41 remains. A current of 2Io (= 4Io-2Io) will flow. Therefore, a voltage of (Io × R) is generated in the load resistor 40, a voltage of (2Io × R) is generated in the load resistor 41, and a voltage (VD0N, VD) is generated in the load resistors 40 and 41.
0P) is VD0N <VD0P, and the voltage difference is (Io ×
R). Further, in this case, other load resistances (42 to
There is no change in the current flowing through 45).

Next, if the input analog voltage (Vin) is V
The operation when ref2 <Vin <Vref3 is described below. At this time, a current of Io flows from the constant current source 72 to the positive phase output of the master comparator latch 105, and a current of Io flows further to the negative phase output of the master comparator latch 101, so the constant current source 72 flows to the load resistor 42. Causes the remaining current Io (= 3Io-2Io) to flow. Further, a current of Io flows from the constant current source 73 to the constant current source 50, and a remaining current of 2Io (= 3Io-Io) flows from the constant current source 73 to the load resistor 43. Therefore, (Io
XR) voltage is generated, and the load resistance 43 is (2 Io).
The voltage (VD1N, VD1P) generated in the load resistors 42 and 43 is VD1N <VD1P, and the voltage difference is (Io × R). Further, in this case, there is no change in the current flowing through the other load resistors (40, 41, 44, 45). Next, the input analog voltage (Vin) is V
The operation when ref4 <Vin is described below.
At this time, the current Io flows from the constant current source 74 to the negative phase output of the master comparator latch 103, and the constant current source 7
4 to the load resistor 44, the remaining Io (= 2Io-I
The current of o) will flow. Further, a current of 2 Io flows from the constant current source 75 to the load resistor 45. Therefore, a voltage (Io × R) is generated in the load resistor 44, a voltage (2Io × R) is generated in the load resistor 45, and a voltage (VD2N, VD) is generated in the load resistors 44 and 45.
2P), VD2N <VD2P, and the voltage difference is (Io
XR). That is, according to the first embodiment, the voltage (VD0P) generated in the load resistor 41 and the voltage (VD1) generated in the load resistor 43 according to the input analog voltage (Vin).
P), and the voltage (VD2P) generated in the load resistor 45 becomes a gray code as shown in FIG. In the above description, the current value Is of the constant current source (70, 71) is Is = 4I.
o, the current value Is of the constant current source (72, 73) is Is = 3I
o, the current value Is of the constant current source (74, 75) is Is = 2I
Although the case where it is set to o has been described, the constant current source (7
0,71), the current value Is is Is = 3Io, the constant current source (7
2, 73) is Is = 2Io, the constant current source (7
It is clear that the current value Is of (4, 75) may be Is = Io. As described above, in the present embodiment, the current output superimposed when the logic voltage is generated is not directly applied to the load resistances (40 to 45) but flows to the master comparator latches (100 to 106). The difference current between the total current value and the constant current sources (70 to 75) is made to flow through the load resistors (40 to 45). Since only the difference current flows through the load resistor, a large voltage drop unlike the conventional example does not occur, and therefore, the master comparator latch (100 to 100
The direct current (DC) bias of 106) has a margin, more master comparator latches can be superposed, and a high resolution A / D converter can be realized.

[Embodiment 2] FIG. 3 shows a circuit configuration of only the least significant bit of a parallel A / D converter having a differential superposition type logic circuit which is another embodiment (Embodiment 2) of the present invention. FIG. Note that FIG. 3 also shows an A / D converter that converts an input analog signal into a 3-bit digital signal. In the second embodiment, the potential of the signal line to be superimposed is set to (VB) by the additional transistor 60 including the grounded base PNP transistors Qp0 and Qp1 to which the bias voltage VBB is applied to the base.
The voltage is fixed to (E + VBB).
Here, VBE is a base-emitter voltage of the additional transistor 60, and VBB is a base voltage of the additional transistor 60. In this embodiment of FIG. 3, the potential of the signal line is fixed to the voltage of (VBE + VBB), but the difference current between the constant current source and the output current of the master comparator latch is passed through the emitter / collector path of the additional transistor 60. Flow into the load resistors 40 and 41. Therefore, basically, the circuit of FIG. 3 operates in the same manner as that of FIGS. 1 and 2. However, in the second embodiment, since the additional transistor 60 is inserted to fix the potential of the overlapping signal line, the additional transistor 60 forms the time constant of the product of the parasitic capacitance of the signal line and the load resistance. It is possible to prevent this from impairing the high speed performance of the superimposed signal. In the second embodiment,
It will be easily understood that, as the additional transistor 60, a P-channel MOS transistor having a gate to which the bias voltage VBB is applied can be used instead of the PNP transistor.

[Third Embodiment] FIG. 4 shows a circuit configuration of only the least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (third embodiment) of the present invention. FIG. Note that FIG. 4 also shows an A / D converter that converts an input analog signal into a 3-bit digital signal. FIG.
20 is a current mirror circuit, and in the third embodiment, the current output of the superimposed master comparator latches (100 to 106) is the current mirror circuit 2.
All currents received by the current mirror circuit 20 and superposed by the current mirror circuit 20 are folded back and applied to the resistance loads (40 to 45). That is, the current of the signal line connected to the output of the master comparator latch flows through the source / drain path of the gate-drain short-circuited diode-connected P-channel input MOS transistor on the input side of the current mirror circuit. A current proportional to this current flows through the source / drain path of the output P-channel output MOS transistor. For example, if the input analog voltage (Vin) is Vin <Vref1, a total of 2Io of the current Io flowing into the positive phase output of the master comparator latch 102 and the current Io flowing into the positive phase output of the master comparator latch 106. Current flowing back into the load resistor 41 by the current mirror circuit 20 and flowing into the positive phase output of the master comparator latch 100, Io current flowing into the positive phase output of the master comparator latch 104, and the constant current. The total current of 3 Io and the current of Io flowing into the source 51,
The current mirror circuit 20 folds it back to flow to the load resistor 40. Therefore, the voltage generated in the load resistance 40 is (VD0N) is (3Io × R), and the voltage generated in the load resistance 41 is (VDOP) is (2
Io × R), and the voltages (VD0N, VD0P) generated in the load resistors 40 and 41 are VD0P <VD0N
Then, the voltage difference becomes (Io × R). The input side of the current mirror circuit 20 is composed of a diode-connected active element such as a gate-drain shorted diode-connected MOS transistor or a base-collector shorted diode-connected bipolar transistor. Since the diode-connected active element operates as a non-linear element, the voltage drop is not proportional to the current but is non-linear. As a result, since the diode-connected active element operates as a voltage clamp element, a large voltage drop as when directly driving the load resistance does not occur. On the other hand, a voltage drop proportional to the current occurs in the load resistors 40 and 41 on the output side of the current mirror circuit 20, or the output side of the current mirror circuit 20 does not substantially affect the input side. Therefore, also in the third embodiment, as in the case of folding back only the differential current, the master comparator latch (1
There is a margin in direct current (DC) bias of 00 to 106),
More master comparator latches (100-10
6) can be superimposed.

[Embodiment 4] FIG. 5 is a diagram showing an example of a circuit configuration of a master comparator latch (100 to 106) used in the parallel type A / D converter of the embodiment of the present invention described above. In the fourth embodiment, as the master comparator latch (100 to 106) of the second embodiment, Bi-
A master comparator latch (100 to 106) using a CMOS process is used. In FIG. 5, the clock signal (CLK1) is "High level".
At the time of, the amplifier mode is set, the transistor (Q5) is turned on, and either the bipolar transistor (Q1) or the bipolar transistor (Q2) is turned on based on the output signal and the inverted output signal from the preamplifier 5. When turned on, the current of Io is absorbed. When the clock signal (CLK2) is "High level", the latch mode is set, the transistor Q6 is turned on, and the state of the bipolar transistor (Q1 or Q2) turned on in the amplifier mode is latched.
Thus, the transistors (Q5, Q6) and the transistors (Q1, Q2) form an ECL series gate. In this case, the transistors (M1, M2) that become active in the latch mode are generally bipolar transistors, but in the present embodiment, especially MOS transistors are used.
It is composed of transistors. When the transistor that becomes active in the latch mode is a vertical bipolar transistor, a large collector-substrate capacitance (C
Sub) causes the operation speed to decrease.

On the other hand, if the transistor that becomes active in the latch mode is a lateral type MOS transistor, the drain-substrate capacitance becomes extremely small and the operating speed is improved.

Needless to say, the parallel type A / D converter shown in each of the embodiments can be applied to the PRML signal processing shown in FIG.

Although the present invention has been specifically described based on the embodiments, it is needless to say that the present invention is not limited to the above embodiments and various modifications can be made without departing from the scope of the invention.

[0024]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

(1) According to the present invention, in the parallel type A / D converter, the power consumption can be reduced, and more comparators can be superposed.

(2) According to the present invention, in the parallel type A / D converter, it is possible to eliminate the influence of the parasitic capacitance of the signal line, thereby preventing the superposed signal from being operated at high speed. It becomes possible.

[Brief description of drawings]

FIG. 1 is a diagram showing a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit according to an embodiment (Embodiment 1) of the present invention.

2 is a diagram showing a circuit configuration of only the least significant bit of the A / D converter shown in FIG.

FIG. 3 is a diagram showing a circuit configuration of only the least significant bit of a parallel A / D converter having a differential superposition type logic circuit which is another embodiment (embodiment 2) of the present invention.

FIG. 4 is a diagram showing a circuit configuration of only the least significant bit of a parallel A / D converter having a differential superposition type logic circuit according to another embodiment (third embodiment) of the present invention.

FIG. 5 is a master comparator latch (100 to 106) used in the parallel A / D converter according to each embodiment of the present invention.
3 is a diagram showing an example of a circuit configuration of FIG.

FIG. 6 is a diagram for explaining an outline of a PRML signal processing circuit.

FIG. 7 is a diagram showing a circuit configuration of a parallel A / D converter having a differential superposition type logic circuit.

8 is a diagram showing a voltage change occurring in each load resistance according to an input analog voltage (Vin) in the A / D converter shown in FIG. 7.

[Explanation of symbols]

1 ... Series resistance circuit, 5 ... Preamplifier, 100-106 ...
Master comparator latch, 11 ... Bipolar transistor, 12 ... MOS transistor, 20 ... Current mirror circuit, 30 to 32 ... Slave latch, 40 to 45 ...
Load resistance, 50, 51, 70 to 75, I1 ... constant current source,
60 ... Cascode transistor, 80 ... Fixed bias,
Vin ... Input analog signal, Vref1 to Vref7 ...
Reference voltage, Q1 to Q6 ... Bipolar transistor, M
1, M2 ... MOS transistors, CLK1 to CLK2 ...
Clock signals, D0, D1, D2 ... Output digital signals.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masumi Kasahara 5-20-1, Josuihoncho, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. (72) Inventor Eigame Imaizumi Komizura, Kodaira-shi, Tokyo 5-20-1 Hitate Super LSI Engineering Co., Ltd. (72) Inventor Tatsuharu Matsuura 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division (72) Inventor Hisashi Okazawa 5-20-1 Kamimizumoto-cho, Kodaira-shi, Tokyo Hiritsu Cho-LS Engineering Co., Ltd.

Claims (6)

[Claims] 1. A plurality of master comparators for comparing a plurality of reference voltages with an input analog signal and sucking a current of a constant value from a positive phase output or a negative phase output according to the magnitude relationship, and the plurality of masters. Inputs are selectively connected to the positive-phase output or negative-phase output of the comparator through a plurality of signal lines, and a plurality of slave comparators that output a desired digital signal are connected to each of the plurality of signal lines. A plurality of constant current sources and a plurality of load resistors whose one end is connected to each of the plurality of signal lines, and a DC bias voltage is commonly applied to the other ends of the plurality of load resistors. The constant current value of the constant current source of the input signal line of the slave comparator on the lower bit side of the plurality of constant current sources is the constant current of the constant current source of the input signal line of the slave comparator on the higher bit side. Set to a value greater than Parallel A / D converter characterized by comprising Te. 2. The plurality of signal lines are connected to the one ends of the plurality of resistors and the inputs of the plurality of slave comparators through a plurality of grounded base additional transistors. 1. A parallel type A / D converter described in 1. 3. The parallel A / D converter according to claim 1, wherein the plurality of master comparators and the plurality of slave comparators include an ECL series gate circuit. 4. A plurality of master comparators for comparing a plurality of reference voltages with an input analog signal and sucking a current of a constant value from a positive phase output or a negative phase output in accordance with the magnitude relationship, and the plurality of masters. A plurality of signal lines selectively connected to the positive-phase output or negative-phase output of the comparator, a plurality of current mirror circuits whose inputs are connected to the plurality of signal lines, and one end of which is the plurality of current mirror circuits. A plurality of load resistors connected to the output of the circuit and the other ends of which are connected to the reference potential point, and their inputs connected to the outputs of the plurality of current mirror circuits and the one end of the plurality of load resistors, and And a plurality of slave comparators that output the digital signal of 1. in parallel type A / D converter. 5. The positive feedback of the latch is performed by a pair of lateral MOS transistors in the ECL series gate circuit of the plurality of master comparators. The parallel type A / D converter described in 1. 6. A signal processing circuit for reading and processing a signal from a magnetic recording medium, wherein the signal processing circuit is an A / D converter for A / D converting the read signal. A signal processing circuit comprising the parallel type A / D converter described in item 1.