JPH0563573A - Electronic type comparator with multiple selectable preamplifying stage and method of operating said comparator - Google Patents

Abstract

PURPOSE: To reduce the power consumption, to obtain comparator array architecture of small molding size, and to improve the operating speed by enabling a multiple input signal to selectively process a circuit in the same comparator array. CONSTITUTION: The operations of transistors(TR) 315 and 345 are determined by voltages applied to nodes 317 and 347. When the control voltage V1(Sel) applied to the node 317 is much higher than the voltage V2(Sel) of a node 347, the n-p-n bipolar TR 315 is biased forward to raise the voltage of a node 332, and then a current I from a constant current source 330 all leaves the TR 345, so that it flows by passing through the TR 315. Thus, an operation circuit is reduced. The output voltage of the node 312 rises and falls according to whether Va(In) is higher or lower than Va(Ref) and then a more negative or positive differential output is supplied, so the difference output can be converted into a digital signal by an existing method.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention is in the general field of electronic comparators of the type used in range-division type AD converters. In particular, the present invention provides a new and improved comparator arrangement featuring a selectable multiple preamplifier that provides multiple comparator function without duplication of all active elements of each comparator.

[0002]

2. Description of the Prior Art Comparators have wide application in electronic design for comparing an input voltage to a reference voltage and producing a binary word output. Therefore, a comparator is essentially a system such as an AD converter (hereinafter abbreviated as ADC) for converting a sampling analog input signal from a varying analog voltage source into a digital signal of a binary bit signal coded array representation. It becomes a component. A single comparator connection is used in the conversion process, and the analog input is correspondingly compared with a single reference voltage, which typically uses the same resistor single connection tap drawer that connects between reference and ground.

The n-bit digital output is the (2 n-1) parallel comparators (flash AD).
It is possible to create it once by C), or in an extreme method, in successive n steps (successive approximation ADC) by a single comparator. This one-stage flash approach offers apparently faster conversion, but is characterized by stringent device yield constraints due to high input capacitance, high power consumption, and the large number of comparators required in the circuit. .. Thus, different solutions may be optimal for other applications, as speed vs. power consumption, resolution vs. molding size, and other characteristic demarcations play an important role in AD converter design.

In order to reduce the total number of comparators in the circuit,
The designer has one or more low resolution ADC and high resolution AD
DA with feedback for C (range division type ADC) formation
We have developed an architecture that utilizes a converter (hereinafter abbreviated as DAC). This type of architecture first performs a flash conversion of the input signal in the coarse range (higher significant bits) and then a second conversion in the finer range (lower significant bits). For example, in the first stage of the 2 m-bit ADC operation, the analog input voltage signal from the output of the sample and hold amplifier is used for conversion into a higher effective m-bit digital value of the analog signal ((2 m -1)).
M-bit flash ADC with two comparators)
Is supplied to. The m-bit digital value of the first stage is
It is then routed to the DAC and reconverted to an analog value for feedback and subtraction from the analog input voltage for analog residual voltage value generation. 2-step range split type A
In the second stage of DC operation, this residual voltage is lower effective m
It is transmitted through another m-bit flash ADC for digital value generation of bits. The second stage output is then combined with the first stage digital output in a logic network to produce a 2m bit digital output. Therefore, the total number of comparators required to generate an output with a 2m-bit division capability is from (2 2 m −1) to (2 m −1) due to the operation range division of the overall AD conversion. It is reduced to twice.

There are various variations of the range division type architecture used for obtaining higher resolution with smaller power consumption and smaller molding size, and for changing the required characteristics for special applications. All of the variations have the common point that they require two or more flash conversions. Therefore, much effort has been devoted to design development that contributes to continuous flash conversion overall speed and efficiency improvements.

FIG. 1 illustrates the basic architecture of a conventional comparator in the most general arrangement, in which two npn bipolar transistors 11 are shown.
4 and 124 and a differential preamplifier stage including two identical load resistors 110 and 120, and a digital output circuit 160 that provides digital outputs to nodes 162 and 164 (shown as differential outputs in all figures). And are included. Timing logic 170 may also be used to latch the preamplifier output according to a predetermined timing sequence. The constant current source 130 supplies all of the preamplifier bias current between the positive (+ V) power rail 100 and the negative (-V) power rail 102. The input voltage V (In) and the reference voltage V (Ref) are supplied to the base terminals of the transistors 114 and 124, respectively, and this supplies two sets of resistors (110, 120) and a transistor (11).
4,124) affects the relative currents in the two paths defined by the pair, which in turn determines the output voltage at nodes 112 and 122. Those skilled in the art will appreciate that the positive and negative differential outputs depend on whether V (In) is greater or less than V (Ref), which provides a means of comparing the two.

As illustrated in FIG. 2, for example, flash A
The n conventional array comparators used for DC are n transistor pairs P driven by an input voltage V (In) and another reference voltage generated via a resistor ladder R (Ref).
It includes n differential preamplifier stages consisting of 1 to Pn.
This ladder is for applying a reference constant voltage set by the reference voltage V (Ref) and the constant current source I (Ref) (or by an equivalent circuit apparent to those skilled in the art) to each of the nodes N1 to Nn. A series resistor group R1 (Ref) to Rn (Ref) is included. Each preamplifier pair is connected to the positive power rail 200 via the same load resistor pair R1 to Rn, and via its respective constant current source I1 to In as in the single comparator diagram of FIG. It is connected to the negative power rail 202. The output of each preamplifier is latched in the appropriate circuitry within latch array 260 according to a predetermined timing logic and clock circuit 270 and encoded in standard signalization circuit 280 for downstream digital applications. The wiring diagrams of FIGS. 1 and 2 are presented in simplified form for purposes of illustration of the prior art, where the prior art typically adds signal stabilization through a comparator path (eg, a buffer stage) to both the input and output. Please note that it has a circuit.

[0008]

From a review of the prior art, it has been found that there is no evidence of efforts to improve the design of comparators used to form range division sequences for flash conversion. Thus, there is still a need for an electronic comparator architecture that accommodates the power consumption, speed and molding size requirements required for flexible and efficient design.

Therefore, it is an object of the present invention to provide a comparator array architecture that consumes less power and has a smaller molding size than that achieved by modern conventional designs. This is achieved by the use of a selectable preamplifier type comparator array, which can be used in the same way as two sets of comparator arrays are used without mutual duplication of the entire circuit.

Another object of the present invention is to make the result of this comparator array faster than its corresponding pair of comparator arrays.

A further object of the invention is to make the new comparator design suitable for implementation on a semiconductor substrate without additional processing.

Another object of the present invention is to adapt the same general architectural application to a variety of designs and physical implementations to accommodate the various packaging processes currently known in the art. It is a thing. To that end, the apparatus described herein uses bipolar transistors or other equivalent devices, such as junction field effect transistors, metal oxide semiconductor field effect transistors, GaAs devices, or other semiconductors, for those skilled in the art. It can be achieved by making explicit circuit choices.

Yet another object of the present invention is to obtain a comparator design that is flexible and versatile for any application of sequential comparator array requirements or multiple input single output comparator requirements. ..

Finally, another goal is to achieve the above objectives in a way that is both economically and commercially viable. This is achieved by utilizing manufacturing methods that are already available in the open market or can be developed at competitive prices.

[0015]

To achieve these and other objectives, the electronic comparator of the present invention provides a multiple selectable differential preamplifier stage connected to a common load resistor and digital output stage. Equipped with. The inputs to the comparator array are switchable to selected ones of the differential preamplifiers available in each comparator, the resulting differential outputs feeding the common latch output stage of the comparators. In one embodiment of the invention, the switching between preamplifiers is performed by manipulating the bias current between the preamplifiers according to a select signal that affects the bias current path. This can be accomplished without increasing the required bias current by moving the same current to the active preamplifier stage. In another embodiment of the invention, each of the multiple preamplifier stages is supplied with its own bias current and performs switching at the output of the preamplifier. This arrangement gives a faster switching result, because all the preamplifiers selected are always activated.

[0016]

The function of the present invention lies in the novel method adopted for multiple operation in the electronic comparator. Instead of using multiple sets of comparators or arrays of comparators, each feeding one input signal separately, a single comparator or array of comparators with multiple selectable preamplifier stages and a common load resistor and latch As a result, a large number of input signals can be processed by selecting a circuit passing through the same comparator array.

Various other objects and advantages of the present invention will be made apparent by the embodiments described below, and by the novel features particularly pointed out in the appended claims. Therefore, in order to achieve the above-mentioned object, the present invention comprises the features pointed out in the following description of the drawings, detailed description of the preferred embodiments and particularly the claims.
However, these drawings and description merely disclose some of the various ways in which the invention may be practiced.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT One embodiment of the present invention having two selectable differential preamplifiers is shown in FIG. 3, which is a length diagram with the addition of a preamplification stage and a bias current steering circuit. It has the same architecture as described in 1. The load resistors 310 and 320 are connected to the positive power rail 300 and the first pair of npn bipolar transistors 314 and 32.
4 collectors, the emitters of which are in turn connected to the collectors of other bipolar transistors 315. The load resistors 310 and 320 are
It is also connected in parallel to the collectors of a second pair of npn bipolar transistors 340 and 350, respectively, the emitter of which is connected to yet another npn bipolar transistor 345. The emitters of transistors 315 and 345 are connected to a constant current source 330, which is connected to the negative power rail 302. In this way, each transistor pair (314, 32
4 and 340, 350) constitute a selectable differential preamplifier in a comparator, which includes transistors 315 and 345.
Provide switching means between the transistors by operating a current to one or the other of the pair of transistors. As described in the prior art system diagram of FIG. 1, digital output circuit 360 is required to provide digital outputs at nodes 362 and 364. Similarly, timing logic 370 may be used to latch either preamplifier output according to a predetermined timing sequence as required by the particular application.

In operation, the dual preamplifier type comparator of FIG. 3 has two input voltages Va (In) and Vb (In) which may be the same value and two reference voltages which may also be the same value. It is used to compare the voltages Va (Ref) and Vb (Ref).
The operation of transistors 315 and 345 is determined by the voltage applied to nodes 317 and 347. As is apparent to those skilled in the art, when the control voltage V1 (Sel) applied to the node 317 is sufficiently higher than the voltage V2 (Sel) of the node 347, the npn bipolar transistor 31 is used.
5 becomes a forward bias to raise the voltage of the node 332, which turns off the bipolar transistor 345,
This causes all of the current I from constant current source 330 to leave transistor 345 and flow through transistor 315. The operating circuit is thus reduced to the same extent as shown in FIG. Depending on whether Va (In) is larger or smaller than Va (Ref), the output voltage of the node 312 is
The output voltage may be lower or higher than the output voltage of the node 322, and the negative or positive differential output is thus supplied, respectively, so that the differential output can be converted into a digital signal by a conventional method. Will.

When the control signal V1 (Sel) is sufficiently low, the total current I from the current source 330 will flow through the transistor 345. Therefore, transistors 340 and 3
A second differential preamplifier containing 50 includes Vb (In) and Vb (R
ef) will be activated to compare with. Depending on whether Vb (In) is larger or smaller than Vb (Ref), the node 342
Output voltage of node 352 may be lower or higher than the output voltage of node 352 and may provide negative or positive differential output, respectively, so that the differential output may be converted to a digital signal by a conventional method. It will be possible.

FIG. 4 illustrates the use of the first embodiment of the invention in an array of n comparators as shown in the conventional topology of FIG. This array includes n sets of comparators with two selectable differential preamplifiers, indexed a and b for clarity of description. Thus, the array of comparator preamplifiers C1 to Cn includes two sets of arrays (a and b) of differential preamplifier stages, which differential preamplifier stages include transistor pairs P1a to Pna.
And P1b to Pnb, and each of the transistor pairs has an input voltage (Va (In) and Vb (I) for the arrays a and b, respectively.
n)) and a corresponding resistor ladder (Ra (Ref) and Rb (Ref) that may make up the same ladder) and a set of reference voltages generated through each. Each one of this reference voltage ladder is a series of resistors R1a (Ref) to Rna (Ref) and R1.
1b (Ref) to Rnb (Ref), and the single resistor supplies the reference constant voltage to each of the nodes N1a to Nna and N1b to Nnb. The reference constant voltages are the reference voltages Va (Ref) and It is determined by Vb (Ref) and the corresponding constant current sources Ia (Ref) and Ib (Ref). The respective collectors of the preamplifier device pairs are connected to the positive power supply rail 400 via equal load resistor pairs R1 to Rn, the emitters of which are the collectors of the switching transistors forming the current steering device pairs S1 to Sn. Connected to.
The current operating device pair is connected to the negative power supply rail 402 through the corresponding constant current sources I1 to In by connecting the emitters thereof, and is the same as the single double preamplifier type comparator described in FIG. It is a method. The output of each preamplifier set is output by a predetermined timing logic circuit 47.
0 in the appropriate arrangement in the latch array 460 and encoded in the standard encoding circuit 480 for downstream digital applications. As with FIG. 2, the flow diagram of FIG. 4 represents a simplified schematic diagram of a flash ADC using a selectable preamplifier type comparator array. Dual input AD
In the case of C, a single reference voltage resistor ladder (ie Ra
It is hoped that further simplification will be achieved by using (Ref) and Rb (Ref) are realized by the same series connected resistors).

In operation, the dual preamplifier type comparator array of FIG. 4 provides two input voltages Va (In) and Vb (In), which may be the same value, which may also be the same value, Va.
(Ref) and Vb (Ref) and standard ladder Ra (Ref) and Rb (Ref)
It is used to compare two series voltage references set by the specific value of each resistor in the.

The operation of each set of the switching transistors S1 to Sn is performed by driving digital control voltages V1 (Sel) and V2 (Se).
l). For proper circuit operation,
Prepare an external circuit (not shown) to V1 (Sel)
Is high, V2 (Sel) is low, and V1 (Sel) is low, V
Please note that it is necessary to guarantee that 2 (Sel) becomes high. As will be apparent to those skilled in the art, when the control signal V1 (Sel) is high and V2 (Sel) is low, V1 (Sel) is high.
The npn bipolar transistor driven by will be forward biased and all current from the corresponding constant current source I1-In will flow through that transistor. In this way, the driving circuit is reduced to that shown in Fig. 2, and Va (I
It will produce an output proportional to n). Depending on whether Va (In) is greater than or less than the reference voltage at nodes N1a-Nna, the differential output voltage of each preamplifier in the array will be negative or positive, respectively, and can be converted to digital signals by conventional means. Provides a series of outputs. Similarly, when the control signal V1 (Sel) is low and V2 (Sel) is high, the total current from the constant current source flows through the second differential preamplifier array, producing an output proportional to Vb (In). Supply. Again, Vb
Depending on whether (In) is greater than or less than the reference voltage at nodes N1b-Nnb, the differential output voltage of each preamplifier in the array will be negative or positive, respectively, and a series of signals that can be converted to digital signals by conventional techniques. Provide output.

From the schematic diagram of FIG. 4, it can be seen that the single array of comparators illustrated therein can be used in exactly the same way as two separate comparator arrays, avoiding duplication of the entire circuit double array. it is obvious. As a practical matter, only the differential preamplifier stage is of overlapping length, and the same load resistance, buffer (not shown), and latch stage are utilized in both operating modes. Of course, this produces an effective saving in power consumption and molding size, and moreover, because the same bias current selectively flows between the two preamplifiers, an additional bias current is also provided for this preamplifier double-placed operation. Is never required. Also, since switching between two preamplifiers is a unique feature of the present invention, the
The two alternative input switching means are already built into the architecture.

In terms of flash conversion applications, such as those used in ADCs, this new comparator is also equipped with a single flash converter and uses the external transmission controller to make known bidirectional conversions. Very efficient compared to the architecture. The characteristics of the selectable preamplifier are that the switching is extremely fast and the analog ADC input (first conversion) and the residual signal (second conversion)
Yields a comparator that does not require a bandwidth limiting multiplexer for switching flash conversion inputs between and. The switching of the preamplifier stage may occur as soon as the preamplifier output in the first conversion cycle is latched. Another advantage over prior art cycling architectures is the fact that the comparator according to the invention can be more easily implemented using high speed bipolar transistor technology rather than voltage transfer controllers. The signal inputs to the comparators may or may not be the same depending on the application, and similarly the reference voltage series connection to each selectable preamplifier pair may or may not be the same. May. Moreover, the invention is not limited to two selectable preamplifiers. Obviously the same technique can easily be implemented in a similar way for more than two parallel preamplifiers. This degree of flexibility makes the invention extremely versatile and useful for many different applications.

Changes to the embodiment of the invention described above are shown in FIG.
Is illustrated in the second specific example shown in FIG. Among them, the same principle is implemented by supplying different bias currents to each selectable preamplification stage. Since the switches are switched on the output side of the differential preamplifier device, all the preamplifier transistors are always biased. Although this consumes a little more power, it provides the advantage of faster switch switching speed because it eliminates the manipulation of the current required to activate the selected preamplifier. For some applications,
The switch arrangement on the output side of the preamplifier has also produced results consistent with improved power supply. Total power consumption and molding size are still reduced compared to the use of two sets of completely separate converters, and the switching means between the inputs are still unique to the architecture of this embodiment of the invention. Living as a thing.

Referring to FIG. 5, the second embodiment of the present invention has a switch circuit operating in the same manner as the first embodiment illustrated in FIG. 3 but operating at the output of the preamplifier, It is composed of two differential preamplifiers connected in parallel with a common load resistor. Load resistor 510
And 520 are connected to the positive power rail 500 and to the collectors of the first npn bipolar transistor pair 514 and 524, respectively, via a switch network 529 and are also in parallel arrangement in the same switch network. Also connected to the second npn bipolar transistor pair 540 and 550 via 529, respectively.
The emitters of transistors 514 and 524 are connected to a constant current source 532 which is connected to the negative power rail 502. Similarly, the emitters of transistors 540 and 550 are connected to a constant current source 534, which is also linked to the negative power rail 502. Switch network 5
29 is the respective preamplifier transistor 514, 52
An npn bipolar transistor pair (516, 51) with emitters connected to the collectors of 4, 540 and 550.
8; 526, 528; 544, 546; and 554, 5
56) is included. In each of these transistor pairs, the collector of one transistor is connected to a load resistor to form a path for the preamplifier output signal, while the collector of the other transistor is directly positive power supply rail 500. Connected to form a bypass for the preamplifier output signal. The operation of each transistor in this transistor pair is similar to that of transistor 3 in the schematic diagram of FIG.
In the same manner as described above for 15 and 345, it is determined by the relative values of the drive voltage V1 (Sel) and V2 (Sel) of the transistor pair. In this way, each transistor pair (5
14, 524 and 540, 550) constitute a selectable preamplifier in the comparator, and also transistor pairs (516, 518; 5 in switch network 529).
26,528; 544,546; and 554,556).
Provides switching means between these selectable preamplifiers by opening one or the other output path.

More specifically, the switch network 52
Nine transistors 516 and 526 connect two load resistors each to respective transistors 514 and 524 to form both sides of the first differential preamplifier. When transistors 516 and 526 are conducting, the output of the first differential preamplifier is transferred to nodes 512 and 522. On the other hand, transistors 518 and 528 connect transistors 514 and 524, respectively, directly to positive power rail 500. Therefore, when transistors 518 and 528 are conducting (and transistors 516 and 526 are correspondingly open), the first preamplifier output will be output from nodes 512 and 522 even when it is active. To be separated. Transistors 540 and 550 have the same switch arrangement
Also exists for the second differential preamplifier including Transistors 544 and 554 connect two load resistors 510 and 520, respectively, to respective transistors 540 and 550, such that when transistors 544 and 554 are conductive, the output of the second preamplifier is connected to node 542. 552
Be transmitted to. Transistors 546 and 556 connect transistors 540 and 550 directly to the positive power rail 500.
, So that when transistors 546 and 556 are conductive (and transistors 544 and 554 are correspondingly open), the second preamplifier output is connected to node 542 even when it is active. Disconnected from 552. Since the same control signals V1 (Sel) and V2 (Sel) drive each transistor pair of the switch network 529, the output path of either the first or the second preamplifier is always connected. However, there is no simultaneous connection of both paths. As a result, both preamplifiers are always active, but only one output is available at any time, selected by the relative voltage of V1 (Sel) and V2 (Sel). As illustrated in the schematic diagram of the first embodiment of the present invention of FIG. 3, a comparable digital output circuit 560 is required for the differential output supply at nodes 562 and 564. Similarly, timing logic circuit 570
May be used to latch either preamplifier output according to a predetermined timing sequence as may be required in a particular application.

As in the first embodiment, the dual preamplifier type comparator of FIG. 5 may also have two input voltages Va (In) and Vb (In) which may be equal. It is used to compare with two reference voltages Va (Ref) and Vb (Ref) which are not present. Transistor pairs 516 and 518, 526 and 5
28, 544 and 546, and 554 and 556,
Determined by the voltage applied to nodes 517 and 547. When the control voltage V1 (Sel) applied to the node 517 is higher than the voltage V2 (Sel) of the node 547, np
-N bipolar transistors 516, 526, 546,
And 556 are forward biased and nodes 531 and 53 are
The voltage at 3, 535 and 537 is increased to turn off the bipolar transistors 518, 528, 544 and 554, opening the output path of the second preamplifier. In this way, the operating circuit is again reduced to that shown in FIG. 1, and the first differential preamplifier plays the role of transmitting the output signal. Depending on whether Va (In) is larger or smaller than Va (Ref), the output voltage of the node 512 is the node 52.
It is determined whether it is lower or higher than the output voltage of 2 and thus provides a respective negative or positive differential output that can be converted by the network 560 into a digital signal.

The control voltage V1 (Se
l) is lower than the voltage V2 (Sel) of the node 547,
npn bipolar transistors 516, 526, 5
46 and 556 open the output path connection of the first preamplifier. At the same time, the bipolar transistors 518, 52
8, 544 and 554 are turned on to form the output signal path to nodes 542 and 552 of the second differential preamplifier. Whether Vb (In) is greater than or less than Vb (Ref) determines whether the output voltage at node 542 is less than or greater than the output voltage at node 552, thus providing a negative or positive differential, respectively, which can be converted to a digital signal by network 560. Will supply the output.

Obviously, both embodiments of the present invention can be used in other applications in multiple preamplifier arrangements (only two arrangements are illustrated in the schematic drawing). In fact, the present invention can be used in a manner apparent to those skilled in the art for applications that benefit from ADCs with multiplexed inputs. As shown for the dual-placement architecture, the advantage is that the functionality of the isolated flash converter is achieved without the overlap of bias currents for the latch circuit, load resistor, and each comparator. This saves power and reduces molding size, while at the same time this can be achieved without speed penalties as it allows for pre-amplifier switch switching during data transmission through the latch circuit. Further, in the implementation of the second specific example, the switch changeover becomes particularly fast. The reason is that all preamplifier devices are always activated and the settling time between switches is greatly reduced.

Within the scope of the present invention, it is speculated that a detailed circuit modification design for handling many equivalent current levels and parameter matching requirements to maintain the normal functioning of the circuit is possible. The electronic circuit architecture realized by the bipolar transistors described here is suitable for monolithic manufacturing. On the other hand, any person skilled in the art can choose between alternative components such as field effect transistors, metal oxide semiconductor field effect transistors, or Ga.
Equivalent devices such as transistors commonly referred to in the industry as As devices could be used to facilitate the practical circuit design of the present invention.

Various changes in detailed circuit design, steps and materials as described above may be made by any person skilled in the art within the principles and scope of the invention as illustrated herein and defined in the appended claims. Absent. While the present invention has been shown and described in what is believed to be the most practical and preferred embodiments, it is recognized that there may be deviations from it within the scope of the present invention, and therefore the present invention comprises: It should not be limited to the details disclosed herein, but should be consistent with the full scope of the claims to include any equivalent apparatus and methods.

[0034]

The essence of the present invention lies in the novel method adopted for multiple operation in an electronic comparator, in which multiple selectable preamplifier stages and a common load resistor and latch circuit are provided in the comparator or comparator array. In preparation, a large number of input signals can be processed by selecting a circuit passing through the same comparator array. This allows the functionality of the discrete flash converter to be realized without the overlap of bias currents for the latch circuit, load resistors and comparators, which saves power and reduces molding size while at the same time implementing data transmission through the latch circuit. By adopting the switch switching method between the preamplifiers inside, it was possible to achieve no speed penalty.

The present invention is also suitable for implementing a new comparator design on a semiconductor substrate without additional processing.

[Brief description of drawings]

FIG. 1 is a schematic diagram showing a typical arrangement of conventional differential preamplifier stages of an electronic comparator.

FIG. 2 is a schematic diagram showing a typical arrangement of a conventional comparator array for flash AD conversion.

FIG. 3 is a schematic diagram of one embodiment of a selectable preamplifier comparator architecture according to the present invention in which the input signal to the comparator is switched between two differential amplifiers by current steering.

FIG. 4 is a schematic diagram of a comparator array layout diagram for flash AD conversion using a selectable preamplifier type architecture in accordance with the present invention.

FIG. 5 is a schematic diagram of a second embodiment according to the present invention in which the switching between selectable differential preamplifiers is by switching at the preamplifier device output rather than by current steering. Be implemented. In the drawings, parts having the same last two digits of a part numbered with a three-digit integer indicate that they are the same kind of parts throughout all the drawings showing various concrete examples.

[Explanation of symbols]

 100 positive power rail 102 negative power rail 110 load resistor 112 node 114 npn bipolar transistor 120 load resistor 122 node 124 npn bipolar transistor 130 constant current source 160 digital output circuit 162 output node 164 Output node 170 Timing logic circuit 200 Positive power supply rail 202 Negative power supply rail 260 Latch arrangement 270 Timing logic clock circuit 280 Standard encoding circuit 300 Positive power supply rail 302 Negative power supply rail 310 Load resistance 312 node 314 npn Bipolar transistor 315 npn bipolar transistor 317 node 320 Load resistance 322 node 324 npn bipolar transistor 330 Constant current source 33 2 node 340 npn bipolar transistor 342 node 345 npn bipolar transistor 347 node 350 npn bipolar transistor 352 node 360 digital output circuit 362 node 364 node 370 timing logic circuit 400 plus power supply rail 402 Negative power supply rail 460 Latch arrangement 470 Timing logic circuit 480 Standard coding circuit 500 Positive power supply rail 502 Negative power supply rail 510 Load resistor 512 node 514 npn bipolar transistor 516 npn bipolar transistor 517 node 518 npn bipolar transistor 520 load resistor 522 node 524 npn bipolar transistor 526 npn bipolar transistor Transistor 528 npn bipolar transistor 529 switch network 531 node 532 constant current source 533 node 534 constant current source 535 node 537 node 540 npn bipolar transistor 542 node 544 npn bipolar transistor 546 np -N bipolar transistor 547 node 550 npn bipolar transistor 552 node 554 npn bipolar transistor 556 npn bipolar transistor 560 (comparable) digital output circuit 562 node 564 node 570 timing logic circuit C1 comparator Preamplifier C2 Comparator Preamplifier Cn Comparator Preamplifier I (Ref) Constant current source I1 Constant current source I2 Constant current source Ia (Ref) Constant current source Ib (Ref) Current source In Constant current source N1 node (reference voltage ladder) N1a node (reference voltage ladder) N1b node (reference voltage ladder) N2 node (reference voltage ladder) N2a node (reference voltage ladder) N2b node (reference) Voltage ladder) Nn node (reference voltage ladder) Nna node (reference voltage ladder) Nnb node (reference voltage ladder) P1 transistor pair P1a transistor pair P1b transistor pair P2 transistor pair P2a transistor pair P2b transistor pair Pn transistor pair Pna Transistor pair Pnb Transistor pair R (Ref) Resistor ladder R1 Load resistor pair R1 (Ref) (For resistor ladder configuration) Series resistor R1a (Ref) (For resistor ladder configuration) Series resistor R1b (Ref) ( Series resistor (for resistor ladder configuration) R2 Load resistor pair R2 (Ref) (For resistor ladder configuration) Series resistance R2a (Ref) (For resistor ladder configuration) Series resistor R2b (Ref) (For resistor ladder configuration) Series resistor Ra (Ref) Resistor ladder Rb (Ref) Resistor ladder Rn Load resistor pair Rn (Ref ) (For resistor ladder configuration) Series resistor Rna (Ref) (For resistor ladder configuration) Series resistor Rnb (Ref) (For resistor ladder configuration) Series resistor S1 Current operating device pair S2 Current operating device pair Sn Current operating device pair

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Jerry L. Bulletsed Saw 85748, Arizona, USA North Conteussion Drive, Towson 714 (72) Inventor, Myron J.A. Cohen 85749, Arizona, United States East Logicer Road, Towson 10900

Claims (20)

[Claims] 1. A selectable preamplifier electronic comparator comprising: (a) multiple differential preamplifier stages connected to a common load resistor and a digital output stage; and (b). Means for selectively activating any one of said multiple differential preamplifier stages. 2. The selectable preamplifier electronic system of claim 1, wherein said means for selectively activating any one of said multiple differential preamplifier stages comprises a bias current steering circuit. comparator. 3. The bias current steering circuit according to claim 2, wherein the bias current steering circuit includes multiple transistors, each of which is connected to a corresponding differential preamplifier, and the multiple transistors are at the same time one of the transistors. Selectable preamplifier electronic comparator that is selectively driven by a control voltage to activate only the corresponding preamplifier by passing a bias current in the differential preamplifier stage. 4. The selectable preamplifier electronic comparator of claim 3, wherein the multiplex transistor comprises a bipolar transistor junction driven by a control signal. 5. The selectable preamplifier electronic comparator of claim 3, wherein the multiplex transistor comprises a junction field effect transistor driven by a control signal. 6. The selectable preamplifier electronic comparator of claim 3, wherein the multiplex transistor comprises a metal oxide semiconductor field effect transistor driven by a control signal. 7. The selectable preamplifier electronic comparator of claim 3, wherein the multiplex transistor comprises a GaAs transistor driven by a control signal. 8. The method according to claim 3, wherein the multiple differential preamplification stage is composed of bipolar transistor junctions.
Selectable preamplifier electronic comparator. 9. The selectable preamplifier electronic comparator of claim 3, wherein the multiple differential preamplifier stage comprises a junction field effect transistor. 10. The selectable preamplifier electronic comparator of claim 3, wherein the multiple differential preamplifier stage comprises a metal oxide semiconductor field effect transistor. 11. The selectable preamplifier electronic comparator of claim 3, wherein the multiple differential preamplifier stage comprises GaAs transistors. 12. The two transistors of claim 3, wherein the multiple differential preamplifier stage includes two differential preamplifiers and the multiple transistors are selectively driven by two control voltages. Selectable preamplifier electronic comparator including. 13. The multiple differential preamplifier stage of claim 3, wherein said multiple differential preamplifier stage comprises two differential preamplifiers connected to a single reference voltage resistor ladder, said multiple transistors having two control voltages. A selectable preamplifier electronic comparator including two transistors selectively driven by. 14. The device according to claim 1, wherein the means for selectively activating any one of the multiple differential preamplifier stages is constituted by an output side switch circuit of the multiple differential preamplifier stages. Selectable preamplifier electronic comparator. 15. The switch circuit of claim 14, wherein the switch circuit includes multiple transistor pairs connected to corresponding transistors in the multiple differential preamplification stage, and one of each transistor pair is included. A transistor is connected to the load resistor and the digital output stage, while a companion transistor forms a bypass circuit for the load resistor and the digital output stage, and also said in each said transistor pair. A selectable preamplifier electronic comparator in which a transistor is selectively applied with a control voltage to activate one output node length of said multiple differential preamplifier stage at a certain time. 16. The preselectable transistor of claim 15, wherein the multiple transistor pair is selected from the group consisting of bipolar transistor junctions, junction field effect transistors, metal oxide semiconductor field effect transistors, and GaAs transistors. On-amplifier electronic comparator. 17. The transistor according to claim 15, wherein the multiple differential preamplification stage is selected from the group consisting of a bipolar transistor junction, a junction field effect transistor, a metal oxide semiconductor field effect transistor, and a GaAs transistor. Is realized by
Selectable preamplifier electronic comparator. 18. The multiple differential preamplifier stage of claim 15, wherein said multiple differential preamplifier stage includes two differential preamplifiers, and said multiple transistor pairs are selectively driven by two control voltages. Selectable preamplifier electronic comparator including a pair of transistors. 19. The differential differential preamplifier stage of claim 15, wherein said multiple differential preamplifier stage comprises two differential preamplifiers connected to a single reference voltage resistor ladder, said multiple transistor pair being two.
A selectable preamplifier electronic comparator including four transistor pairs selectively driven by a plurality of control voltages. 20. A method of implementing multiple comparator operability with reduced duplication of load currents and bias currents, including a digital output stage, comprising the steps of: (a) being connected to a common load resistor and a digital output stage. Providing a multiple differential preamplification stage, (b) providing means for selectively activating any one of said multiple differential preamplification stages, and (c) said multiple differential preamplification stage. Apply an input signal to any one of the preamplifier stages,
And selectively activating the amplification stage.