JPS6028249A - Mask substrate with mask alignment chip - Google Patents

Abstract

PURPOSE:To align marks easily by forming the marks to at least two chips without forming mask alignment marks corresponding to all chips to a mask substrate when a bump electrode for a semiconductor device is shaped through a photoetching method. CONSTITUTION:When preparing a mask substrate 21, a repeater device, etc., are used, and a chip (a') with a mask pattern and a chip (b') with a mask alignment mark are formed separated by grid lines (c) as chip borders. In the constitution, a mask alignment mark is not formed to the chip (a') with the mask pattern, and the position of an electrode bump is determined by using the mask alignment mark shaped to the chip (b'). Accordingly, chips 23 and 23' consisting of the chips (b') are formed only in regions, in which mask pattern sections 22 are extremely few, in the mask substrate 21, and the marks are aligned simply and workability is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a substrate used in manufacturing a semiconductor device.

(Prior Art) On a mask substrate for photolithography used in the manufacture of semiconductor devices, mask alignment marks used during mask alignment work are provided at the ends of individual semiconductor device chips.

Generally, mask alignment is performed by matching the mask alignment marks formed on the base wafer and the mask alignment marks on the mask substrate based on the size relationship between the mask alignment marks formed on the individual chips on the wafer in the previous process. Align the mask substrate with the mask alignment mark on any chip.

Before the formation of bump electrodes in a semiconductor device, if mask alignment marks are present on individual chips, the following various problems will occur. This case will be explained according to each manufacturing process.

FIGS. 1A to 1G are cross-sectional views illustrating each step of a conventional manufacturing method. Figure A shows the state before bump electrode formation, and O
is a wafer of a substrate of a semiconductor device. Reference numeral 1 denotes a base metal of a portion where a bump electrode is to be formed, and is made of aluminum or the like. 3 is a surface protection film (PSG or 5i02).

In FIG. B, a window is opened in the surface protection film 3 by photolithography, a base metal 1 is formed in a portion where a bump electrode is to be formed, and a mask alignment mark 2 is formed on the wafer. Mask alignment marks 2 are provided at the ends of each chip.

FIG. C shows a state in which bonding metal 4 is deposited on surface protection film 3, base metal 1, and mask alignment mark 2, as shown in the figure.

The diagram represents mask alignment in a photolithographic process for forming a metal pattern for forming bump electrodes.

5A is the mask substrate, 6A is the mask alignment mark, 7A is the main pattern of the mask substrate, 8A is the positive photoresist,
6' is a mask alignment mark formed in the previous step. The mask alignment mark 6' is used for alignment in mask alignment work. When mask matching the mask substrate 5A, since the mask matching mark 6A is a transparent part (referred to as a white pattern), a microscope of the mask matching device is used to see the mask matching marks on the base wafer through the mask matching mark 6A. Look at turn 6'. In this case, the mask alignment mark 6A is small and the underlying mask alignment mark 6' is difficult to see. This is because the ie turn mark on the mask substrate 6A becomes a white pattern due to the photorenost used in photolithography. The reason for using positive photoresist is that metals (aluminum, gold, tin, etc.) are used in the bump electrode formation process, so sulfuric acid + hydrogen peroxide, which is used as a negative photoresist stripper, damages the metal. Further, plasma ashing equipment cannot be used because the metal forming the bump electrodes will change color. Therefore, it is preferable to use a positive photoresist and to remove the resist with an organic solvent (acetone) that will not damage or discolor the metal. In this way, the mask substrate 5A has no choice but to adopt a white pattern for the pattern having a semiconductor function. The same applies to the mask alignment mark. Therefore, the mask alignment mark 6A is a white pattern and is small (30 to 50 microns), making it difficult to see the mask alignment mark 6' on the underlying wafer, resulting in poor workability. Making the mask alignment mark 6' particularly large makes it easier to see, but it is not economical as it increases the area it occupies within the chip. That is, as the chip area increases, the cost per chip increases.

Figure E shows the state of photolithography of a plating pattern for forming bump electrodes. 5B is the mask substrate, 6B is the mask alignment mark, and 7B is the main layer (bump electrode type layer).
), 9 is a photo-etching method using a metal for preventing diffusion of the bump electrode material (metal). Turn-formed, 8B
is a positive photoresist. 6 A' is a pattern of mask alignment marks formed in the previous process, and the mask of the mask substrate 5B is aligned with this pattern. In this case as well, the mask alignment mark is a white pattern and is small (30 to 50 microns) and similarly difficult to see, resulting in poor workability.

Figure F shows a state in which bump electrodes are formed.

Reference numeral 10 indicates a main pattern portion, and 14- indicates a mask alignment mark portion on which a bang electrode is formed on the wafer.

4 is a joining metal.

Figure G shows the completed state in which unnecessary portions of the bonding metal 4 are etched with an etching solution (if the metal is At, a mixed acid of phosphoric acid and nitric acid).

From what has been described above, if mask alignment marks are present on individual chips as in the past, there are various drawbacks described below.

1) Since the mask alignment mark set around the tenon is a white ξ turn, it is difficult to see through the small pattern and see the mask alignment mark on the underlying wafer, resulting in poor workability.

2) In the process of mounting a semiconductor device chip on which bump electrodes are formed, when lead bonding is performed on each bump electrode on the chip, the leads are set on the bump electrodes and electrically welded (bonded). If there is a bump electrode with a mask alignment mark near the electrode, the leads will come into contact and a welding current will flow, essentially resulting in lead bonding or poor bonding strength on the bump electrode.Also, due to the location of the mark on the bump electrode It gets in the way.

3) The material of the puncture electrode is gold, half metal, tin, etc.
In the case of solder bump electrodes, if the bump electrodes are exposed during the etching process of the bonding metal film in Figure G, they will be etched. To prevent this, photolithography is used to cover the pants electrode (10 in Figure F) in the main pattern part with photoresist, but the bump electrode of the mask alignment mark used for mask alignment cannot be covered with photoresist. This uses positive photorenost, and the mask substrate for photolithography is a black pattern, and the bang electrode for the mask alignment mark is white for checking the alignment mark and performing alignment work.
It's an o-turn. In the case of white/NO turn, the photoresist is exposed and developed to dissolve the photoresist and expose the L bump electrode portion. If the bump electrode at the mask alignment mark is exposed in this way, it will be damaged by the etching solution, resulting in poor appearance. In addition, the adhesive strength of the bump electrode may deteriorate and it may come off. If the package is removed, an electrical short circuit will occur in the semiconductor device.

In addition, the relationship between the white and black of the positive photoresist and the pattern of the mask substrate in photolithography is the same as the white and black of the mask substrate.
In the case of a photoresist or a turn, the photoresist is exposed, and when developed, the photoresist dissolves and disappears. The black pattern is the opposite, and the photoresist remains.

4) The bump electrode of the mask alignment mark is small or thin. In this case, if the bonding metal film is etched in the process shown in Figure G, the bump electrodes will be easily removed, especially if the diffusion prevention metal is peeled off in the form of whiskers. If such a condition occurs around the chip, it may cause an electrical short circuit at the edge of the chip when the chip is mounted and used as a semiconductor device.

FIG. 2 is an explanatory diagram of a conventional mask substrate, and A is a plan view;
B is a partially enlarged view. 11 is a mask substrate, 12 is a mask pattern portion, a is a mask pattern, and b is a mask alignment mark, which is present on each chip. C is the grid line (boundary of individual chips).

(Object of the Invention) The object of the present invention was to eliminate these drawbacks, and the mask alignment marks of the mask substrate are not placed in individual chips, but are inserted and arranged in specific parts of the mask substrate. This feature is described in detail below.

(Structure of the Invention) A mask substrate used in photolithography for forming bump electrodes of a semiconductor device has at least two chips for mask alignment marks without providing mask alignment marks on all chips. This is a mask substrate.

(Embodiment) FIG. 3 is an explanatory diagram of a mask substrate according to the first embodiment of the present invention, in which A is a plan view and B is a partially enlarged view.

In the figure, 21 is a mask substrate, 22 is a mask or turn part, 23.23' is a chip with a mask alignment mark installed, a/ is a chip with a mask pattern, b' is a chip with a mask alignment mark, and C is a chip with a mask alignment mark. This is the boundary of the chip. Mask alignment marks for individual chips are not provided on the mask substrate 21. The mask alignment marks used in the mask alignment work are produced by arranging and patterning chips with patterns having semiconductor functions on the mask substrate in the form of "substrate eyes" using a device called a repeater at the stage of manufacturing the mask substrate 21. The place where the mask alignment mark chip is to be inserted is left blank, and finally the specially made mask alignment mark chips are inserted and arranged in the blank area to produce the mask as shown in the figure. This method is not shown, but is performed using conventional mask fabrication methods.

FIG. 4 is an explanatory enlarged view in which a quality control function is added to the first embodiment.

a' is a chip with a mask pattern, d is a specific chip with a mask alignment mark and is also equipped with an e that can be added later, C is a grid line, f is a mask alignment mark, and e is a basic electrical characteristic measurement pattern. . As shown in the figure, the specific chips are inserted and arranged on a di-mask substrate with mask alignment marks and basic electrical characteristics /- and 6 turns. What are the basic electrical characteristics of MOS) transistors?
``FB I'' This is a pattern that can measure the current amplification factor, resistance value, etc. of a bipolar transistor, which are basic characteristics required for quality control of the semiconductor device.

By doing so, one chip has the function of a mask alignment mark and the function of quality control of semiconductor devices.

(Effects of the Invention) As explained above, in the first embodiment, the chips 23 and 23' having mask alignment marks are inserted and arranged at predetermined positions on the mask substrate 21, which has the following advantages. .

1) The size of the mask alignment mark on the mask substrate for photo-etching for bump electrode formation, which does not appear uneven unless a positive photoresist is used, can be made large even if it is a white pattern, so the mask alignment workability due to the mask alignment shift is improved. It's not inferior.

2) The shape and size of the mask alignment mark can be appropriately selected, and peeling of the metal material for the bump electrode can be prevented.

3) Bump electrodes for mask alignment marks are not formed on individual chips, which hinders bonding during the mounting stage.
Problems such as deterioration are eliminated.

4) Since there are no mask alignment marks on each chip, there is no damage to the bump electrodes of the mask alignment marks that occur when etching the bonding metal (4 in Figure 1 F), and there is no risk of poor external appearance or peeling of the chips. There is no electrical short circuit.

As shown in Fig. 4, by adding a quality control function, conventionally the chip for measuring basic electrical characteristics was installed alone on the mask substrate, but with the present invention, the chip for measuring the basic electrical characteristics has been installed on the mask substrate alone, but the present invention has added a function for quality control. By combining the chips, there is no need to insert and arrange new chips with mask alignment marks on the mask substrate, so the number of effective chips of the semiconductor device does not decrease.

In the present invention, a chip on which a mask alignment mark is installed or a specific chip in which a mask alignment mark and a pattern for measuring basic electrical characteristics of a semiconductor device are placed in the same chip is inserted and arranged at a predetermined position on a mask substrate, so that each chip is Since no mask alignment marks are required, the size can be reduced. It has many advantages as described above, and since it does not reduce the number of effective chips and has sufficient functionality, it can be used particularly as a mask substrate for manufacturing semiconductor devices that require the formation of bump electrodes.

[Brief explanation of drawings]

FIG. 1 is a sectional view explaining each step of a conventional manufacturing method, FIG. 2 is an explanatory diagram of a conventional mask substrate, A is a plan view, B is a partially enlarged view, and FIG. 3 is a first embodiment of the present invention. An explanatory diagram of a mask substrate of an example of
A is a plan view, B is a partially enlarged view, and FIG. 4 is an explanatory enlarged view in which a quality control function is added to the first embodiment. 5A...Mask substrate, 5B...Mask substrate, 6A...
...Mask alignment mark, dB...Mask alignment mark,
6'...Mask alignment mark formed in the previous process, 6A'.
・・Turn of the mask alignment mark formed in the previous process,
DESCRIPTION OF SYMBOLS 14...Mask alignment mark part, 11...Mask substrate, 12...Mask cut or turn part, a...Mask cut turn, b...Mask alignment mark, C...Grid line, 21... ...Mask substrate, 22...Mask turn portion, 23, 23'...Chip with mask alignment mark installed, a'...Chip with mask and turns, b'...Mask alignment Chip with mark, f
...Mask alignment mark, e...Basic electrical specific measurement e-turn, d...Chip with f + e installed. Figure 1 Figure 2 Figure 3 Figure 4

Claims (1)

[Claims] A mask substrate used in a photolithography method for forming banzo electrodes of a semiconductor device, characterized in that it has at least two chips for mask alignment marks without providing mask alignment marks on all chips.