JPS6028183B2 - Image reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides photodiodes arranged in an array, M
A group of photoelectric conversion elements such as OS capacitors and a CCD (CHARGE COUPLED DEVICE) that transfers signal charges input in parallel from these photoelectric conversion element groups to the output side.
A CCD comprising an analog shift register consisting of
The present invention relates to an image reading device using an image sensor.

In general, CCD image sensors have the advantage that they can be manufactured with a large number of bits due to their structure, and are therefore often used in image reading devices such as facsimile transmitters that require high resolution.

However, in an image capture device using a conventional CCD image sensor, when the image sensor and its output amplification section are DC coupled, the temperature characteristic of the CCD causes the DC output level to fluctuate in proportion to the temperature. The reference level of the image signal obtained from the output of the amplification section also fluctuates, resulting in a disadvantage that the S/N ratio of the output image signal deteriorates.

Therefore, when a document is transmitted by a facsimile transmitter equipped with a conventional image reading device of this type, the image quality of the received image deteriorates on the receiving side. The present invention has been made in order to eliminate the above-mentioned conventional drawbacks, and in an image capturing device using a CCD image sensor, it eliminates the influence of the temperature characteristics of the CCD shift register, and
An object of the present invention is to provide an image processing device that can improve the N ratio.

The present invention will be explained below based on embodiments shown in the drawings.

FIG. 1 is a block diagram showing the main parts of an embodiment of the image capture device according to the present invention, FIG. 2 is a block diagram showing the main parts of the CCD image sensor in FIG. 1, and FIGS. 3 and 4 are FIG. 2 is a waveform diagram illustrating the operation of each part in FIGS. 1 and 2. FIG.

1 is a CCD image sensor, which includes a photodiode group 2, a charge transfer element group 3a, 3b using FETs, an analog shift register 4a, 4b, a gate circuit 5,
It is composed of a reset circuit 6.

One end (the anode side in FIG. 2) of each photodiode in the photodiode group 2 is grounded.

Furthermore, the electrode ends (cathode side) of the odd-numbered photodiodes in the photodiode group 2 are grounded to the input side of the charge transfer element group 3a, and the electrode ends of the even-numbered photodiodes in the photodiode group 2 are connected to the input side of the charge transfer element group 3b. It is connected. The charge transfer element groups 3a and 3b
The output sides of are connected to the input sides of shift registers 4a and 4b, respectively. The outputs of the shift registers 4a and 4b are input to a gate circuit 5 which converts these outputs into serial signals, and the output of this gate circuit 5 is input to a reset circuit 6.

In this embodiment, as an example, the number of read bits of the image sensor 1 is set to 2048, and these read bits (
In the figure, dummy bits DA (indicated by P in the figure) are provided, four each, for a total of eight dummy bits DA, so the total number of photodiodes in photodiode group 2 is 206 pins.

Further, the number of FETs in each of the charge transfer element groups 3a and 3b is half of the total number of photodiodes in the photodiode group 2, that is, 1028. In addition, in shift registers 4a and 4b, before and after dummy bit DA,
Since dummy bits DB, which are not directly connected to the charge transfer element groups 3a and 3b, are provided, 4 each, for a total of 8, the number of bits of the shift registers 4a and 4b is 103 bits each.

Note that 7a is an output terminal of the shift registers 4a and 4b. 8 is a sensor drive circuit, which receives a gate pulse signal c
, mutually inverted shift pulse signals d, e, and reset pulse signal f are output to the image sensor 1. Here, the gate pulse signal c is applied to the gate pulse input terminal 9.
The shift pulse signal d is input to the shift register 4Aa via the shift pulse input terminal 10a, and the shift pulse signal e
is input to the shift register 4b via the shift pulse input terminal 10b, and the reset pulse signal f is input to the reset circuit 6. Reference numeral 11 denotes a first-stage amplification section that amplifies the output of the image sensor 1, and includes an operational amplifier 12, a resistor 13,
14 and 15.

The operational amplifier 12 has an inverting input terminal connected to the output terminal of the reset circuit 6 via a resistor 13, a resistor 14 provided between the inverting input terminal and the output terminal, and a non-inverting input terminal connected to ground via a resistor 15. has been done. Note that the resistance value of the resistor 13 and the resistance value of the resistor 15 are approximately equal, and the resistance value of the resistor 14 is approximately 10 to 2 stitches higher than the resistance value of the resistor 13. 16 is an image signal processing circuit, and the first stage amplifier 1 1
The output signal h of is inputted, amplification and binarization are performed in consideration of the background as necessary, and the resultant signal is output to the output terminal 17.

18 is a voltage holding circuit, which includes a resistor 19 and a capacitor 20.
It is composed of an integrating circuit consisting of.

Here, the resistance value of the resistor 19 is small, and conversely, the resistance value of the capacitor 20 is small.
Since the capacitance of is increased, the response speed of this voltage holding circuit to input signals is excellent. 21 is the first stage amplifier section 1
1 and the input side of the voltage holding circuit 18, and is controlled by a switching signal i generated by a counter 22, a flip-flop 23, and an AND circuit 24.

The counter 22 receives the gate pulse signal c and the reset pulse signal i from the sensor drive circuit 8, and the flip-flop 23 receives the shift pulse signal e from the sensor drive circuit 8.
and a reset pulse signal f are input. The AND circuit 24 receives the output signal i of the counter 22 and the output signal k of the flip-flop 23, and outputs the switching signal i as its output signal. Reference numeral 25 denotes an inverting circuit, which is composed of an operational amplifier 26 and resistors 27, 28, and 29.

The operational amplifier 26 connects the output of the voltage holding circuit 14 to a resistor 27.
A resistor 28 is provided between the inverting input terminal and the output terminal, and a non-inverting input terminal is grounded through a resistor 29. Here, the resistance value of the resistor 27 is approximately one diagonal of the resistance value of the resistor 19;
It is equal to the resistance value of resistor 8 and twice the resistance value of resistor 29. The output terminal of the operational amplifier 26 is connected to the non-inverting input terminal of the operational amplifier 12 via a resistor 30.

Next, the operation of this image reading device will be explained using the waveform diagrams of FIGS. 3 and 4.

When optical information from an image to be read is incident on the photodiode group 2, each photodiode of the photodiode group 2 accumulates charges obtained by photoelectrically converting the optical information.

When the gate pulse signal c from the sensor drive circuit 8 is applied to each FET of the charge transfer element groups 3a and 3b through the gate pulse input terminal 9, the charges accumulated in each of the photodiodes are transferred through these FETs. The data is transferred to the corresponding bits of shift registers 4a and 4b. As a result, the signal charges of the odd-numbered photodiodes are transferred to each bit of the shift register 4a, and the signal charges of the even-numbered photodiodes are transferred to each bit of the shift register 4b. Next, when the shift pulse signals d and e from the sensor drive circuit 8 are input to the shift pulse input terminals 10a and 10b of the shift registers 4a and 4b, the shift registers 4a and 4b respectively receive the transferred signal charges. In FIG. 2, it is sequentially shifted in the directions of arrows Ya and Yb.

Then, this shifted signal charge is transferred to the output terminals 7a and 7.
The signals are sequentially output from b to the gate circuit 5. Here, since the shift pulse signals d and e are mutually inverted signals, the output of signal charges from the shift registers 4a and 4b is performed alternately.

Therefore, the signal charges output in parallel from both shift registers 4 a and 4 b are converted into serial signals by the gate circuit 5 and input to the reset circuit 6 . Then, the reset circuit 6 converts the input signal into an output signal g by resetting the input signal bit by bit using the reset pulse signal f supplied from the sensor drive circuit 8. Output to. The above-described operation of the image sensor 1 is similar to that in a conventional image processing apparatus, and the output signal g of the image sensor is ideally as shown in FIG. 3g.

That is, ideally, no signal component occurs in the dummy bit DB portion of the output signal g of the image sensor.
However, in reality, when the temperature rises due to the temperature characteristics of the CCD, the DC level of the signal g changes, so the signal g becomes as shown in FIG. 4g.

Next, the signal g is inverted and amplified by the first stage amplifier 11. Here, this inversion amplification is performed based on the voltage yo applied to the non-inverting input terminal of the operational amplifier 12, but conventionally, the reference voltage Vo has been fixed to a constant value. Therefore, conventionally, when the DC level of the signal g fluctuates due to the temperature characteristics of the CCD, the DC level of the output signal h of the first stage amplifier 11 also fluctuates, resulting in a noise component in the read bit part, as shown in h' in Figure 4. This caused the S/N ratio of the image signal to deteriorate as described above. However, in this image reading device, the dummy bit portion DB of the output signal h of the first stage amplifying section 11
By controlling the voltage Vo according to the voltage level (indicated by the broken line A in FIG.
It is possible to compensate for the deterioration of the N ratio.

This will be further explained below. As shown in FIG. 3, the output signal j of the counter 22 is the gate pulse signal c
It becomes "1" at the falling edge of f, and then becomes "0" when nine reset pulse signals f are counted.

Further, the output signal k (not shown) of the flip-flop 23 becomes "1" at the rising and falling edges of the shift pulse signal e, and "1" at the rising edge of the reset pulse signal f.
0''. Therefore, the AND circuit 24 outputs the signal j
The switching signal i created by ANDing k and k becomes "1" when the signal of the dummy bit DB portion is output from the image sensor 1, and becomes "0" in other cases.

Here, since the analog switch 21 is closed when it is ``1'' and opened when it is ``0'', only the signal of the dummy bit DB portion of the output signal h of the first stage amplifier 11 is analog. The other part of the signal h cannot pass through the analog switch 21.

Therefore, the output signal 1 of the analog switch 21 becomes as shown in FIG. 41. Next, the signal 1 is transmitted to the voltage holding circuit 25.
It is integrated by

Once the capacitor 20 is charged to a certain voltage level B as shown in FIG. 4m, the output signal m of the voltage holding circuit 18 will hold that voltage level B thereafter. Next, the inverting circuit 25 inverts the signal m to obtain a signal n.

Then, this signal n is appropriately divided by resistors 30 and 15 and input to the non-inverting input terminal of operational amplifier 12. Therefore, the reference voltage Vo applied to the non-inverting input terminal of operational amplifier 12 drops to level B', which is indicated by a broken line in FIG. 4n.

Therefore, the voltage Vo drops in FIG. 4g and rises in FIG. 4h'. When such feedback control is performed over several lines, the charging voltage of the capacitor 20 becomes a steady state, and the output signal h of the first stage amplifier section 11 becomes as shown in FIG. 4h.

As is clear from the figure, when the steady state is reached, noise caused by the temperature characteristics of the CCD and operational amplifier 12 is no longer included above the reference voltage Vo. therefore,
The S/N ratio of the output signal h of the first stage amplifier section 11 is improved.
Further, the output signal h of the first stage amplifying section 11 is input to the image signal processing circuit 16, and the image signal processing circuit 16 extracts only the signal above the reference voltage Vo from the signal h and processes the signal. Therefore, this signal processing becomes easy, and a signal with less noise components is outputted from the output mode 17. Note that in the embodiment described above, the output signal m of the voltage holding circuit 18 is inverted by the inverting circuit 25 and inputted to the non-inverting input terminal of the operational amplifier 12; g
Needless to say, it may be added to

As described above, in the image processing device of the present invention, dummy bits to which signal charges are not inputted in parallel from the photoelectric conversion element group are provided in the analog shift register consisting of a CCD, and the dummy bits of the output signal of the image sensor are By controlling the reference level of the amplifying section that amplifies the output signal of the image sensor based on the level of the signal of the corresponding bit, the influence of the temperature characteristics of the CCD and the amplifying section is compensated for, and the output from the amplifying section is This provides an excellent effect of improving the S/N ratio of the image signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of an embodiment of the image reading device of the present invention, FIG. 2 is a block diagram showing the main parts of the CCD image sensor in this embodiment, and FIGS. FIG. 3 is a waveform diagram illustrating an example operation. 1... Image sensor, 2... Photoelectric conversion element group, 4a,
4b...Analog shift register, 11...Switching amplifier section, 18...Voltage holding circuit, 21...Analog switch, 22...Counter, 23...Flip-flop, 24...・AND circuit. Figure 4 of the ship's rudder diagram

Claims (1)

[Claims] 1. An image reading device using an image sensor including a photoelectric conversion element group and a shift register that transfers signal charges input in parallel from the photoelectric conversion element group to an output side, provided in the shift register, dummy bits to which signal charges are not input in parallel from the photoelectric conversion element group;
an amplification section that is DC coupled to the image sensor and amplifies the output signal of the sensor; a voltage holding means; a switch means interposed between the output side of the amplification section and the input side of the voltage holding means; control means for closing the switch means only when the output signal of the bit corresponding to the dummy bit is output from the amplification section; and control means for closing the switch means based on the output voltage of the voltage holding means. An image reading device characterized in that it is controlled by