JPS5945761A - Picture information reader - Google Patents

Abstract

PURPOSE:To eliminate a DC comonent, by detecting a DC level of an output of an image pickup device while a gate-on signal exists and gate-off signal does not exists so as to obtain a signal eliminated for the DC level from the output of the pickup device. CONSTITUTION:An output of an AND gate 45 is applied to a base of a transistor (TR) 43 of an output processing circuit 40, and a pulse generating circuit 50 generating a gate signal G2 being a low level while a reset clock phir is at a high level H is connected to a timing circuit 20, and gate signals G1, G2 are applied to an AND gate 45. The TR 43 of the output processing circuit 40 is conductive only when a scanning output of a CCD image pickup device 1 is within a dummy diode 21 and the CCD pickup device 1 is not reset. Thus, the TR 43 of the circuit 40 is turned off during the reset period, the charging voltage of a capacitor 42 depends on the DC voltage component at all times and the DC voltage component is eliminated correctly.

Description

[Detailed description of the invention] The present invention relates to read information processing of an imaging device.

An imaging device, for example, a CCD (
Charge Coupled 1)
In an imaging device, the output includes a DC component. In order to eliminate this, an output processing circuit is connected to the imaging device.

FIG. 1 shows an example of a combination of a conventional output processing circuit, an imaging device, and a timing circuit, and FIG. 2 shows input/output signals of each part.

In this case, the 1-transistor 43 of the output processing circuit 40
, there is a switching I/transistor for DC regeneration, and it determines the timing when only the DC component is output from the CCD imaging device 1 (Gummy photoelectric conversion elements 21 + 22).
Goo 1 to Output G are set so that they are turned on during the period in which information (black) is being scanned and output. When the gate output G is at a high level 11, the transistor 43 is turned on, and the capacitor 42 is charged with [DC output voltage of CCD 1 = (base-emitter voltage Vbe)]. When the G output is at a low level L, the l-transistor 43 is turned off, and the non-inverting input voltage of the operational amplifier 44 is the voltage obtained by subtracting the charging voltage of the capacitor 42 from the emitter voltage of the transistor 4I, that is, the cancellation of the DC voltage. It is only the AC component that was Therefore, the amplifier 44 outputs only the AC component of the video signal.

However, if the imaging device has a sample and hold circuit 10
However, in CCD imaging devices used for ultra-high-speed facsimile scanning, which require a high scanning speed and high shift clock frequency, it is necessary to increase the response speed of the sample and hold circuit. is difficult, subject to speed limitations, and sample bold pulses (
■) The disadvantages are greater, such as being affected by noise from 9.

The present invention aims to eliminate the need for a sample-and-hold circuit and remove DC components.

FIG. 3 shows an embodiment of the present invention, and FIG. 4 shows input and output of each part.

CCD imaging device 1 roughly includes a photoelectric conversion element (photodiode) array 2. It is equipped with an analog shift 1 register 4 and an output circuit 5 of 1-gate, 3° parallel-in, and serial array 1-. The array 2 is an arrangement of a dummy element 1-2t, an image reading element 1-22, and a dummy element 23. The dummy elements 1-21 and 22 are covered with a light-shielding mask.

Charges corresponding to the photocurrent accumulated in array 2 are transferred to group 1
- Transferred to shift register 4 by clock ΦL. The shift register 4 has shift tarlocks Φ1 and Φ2.
One bit is output at the falling edge of . Reset l - clock Φr is output 1 - transistor 8 immediately before shift clock
During the reset period, the CCD output shows a DC level, and a signal corresponding to the amount of light is output at the next shift tarlock. At this time, when the transistor 43 of the output processing circuit 40 is turned on with the conventional DC regeneration gate signal G1, the charging voltage of the capacitor 42 changes greatly while Φr is at the high level H, and corresponds to the correct DC level. do not.

Therefore, in this embodiment, the output of Antoge 1.45 is applied to the base of the transistor 43 of the output processing circuit 40,
On the other hand, a pulse generator 50 that generates a gate signal G2 which is at a low level L while Φr is at a high level H is connected to the timing circuit 20, and the gate signals G1 and 02 are connected to the timing circuit 20.
1 to 45 were applied.

In the timing circuit 20, the counter 21 counts up the clock pulse Cp, and the third pip]-output(
cp divided by 178 pulse) is shift 1 to clock pulse Φ
1, and an inverted signal of Φ1 is given to the CCD imaging device 1 as shift 1-clock pulse Φ2. When the count value reaches a predetermined value, the output of the ant game 1-29 becomes H, the counter 21 is cleared, and the counting from 1 to 1 is started again. While the current value is 1 to 3, the output of the exclusive NOR gate 24 becomes H, and at its fall, the flip-flop 30 is set to the cell 1, and the output of the exclusive NOR gate 24 becomes H.
Since h25 is closed, also flip-flop 3
0 can be reset by the output (clear output) of the ant game 1-29, and the AND gate 25 is opened only during this reset, so the output I of the ant game 1-25, that is, the transfer gate clock ΦL, is the output of the counter 21. From one clear to the next clear (one serial data output), it appears once immediately after clearing.

With this transfer clock 1-clock ΦL, gates 1-4 are opened and the information of photodiode array 2 is transferred to shift 1-register 4. From the start of this transfer until just before the fifth shift clock pulse (■) 1 appears,
Φ1. In synchronization with Φ2, the CCD imaging device 1 detects the first bit d1 of the first dummy diode 21 covered with a light-shielding coating.
The information of the eighth bin 1-d8 (completely black) is output.

The first goo 1-signal G1 is at timing times j! 820, Antoge-1-26-28. It is generated by flip-flops 31 and 32 and counter 33.

When the fourth bit output (3) of the counter 21 rises, the flip-flop 31 opens the AND gate 27, and the counter 33 outputs the second bit I-(1) of the counter 21.
) is counted up by the counter 33, and when the count value of the counter 33 reaches 5, the output of the anime game 1-28 becomes 1.
4, the flip-flop 31 is set to reset 1, and since this operation is performed only once in the flip-flop 32 from one clearing of the counter 21 to the next clearing, the first Gl-signal Gl As shown in FIG.
- The high level Ll is only during the period when the information (complete heat) of diodes d2 to d6 is output.

The second goo 1-signal G2 is ant game-1-51 to 53
and a pulse generator 50 composed of orgames 1 to 54
occurs in As shown in FIG. 4, this Goo1-signal G2 has a reset pulse Φr at a high level. It is.

Since these first and second gate signals Gl and G2 are applied to the AND gate 45 of the output processing circuit 40,
The transistor 43 of the output processing circuit 40 is conductive only when the scanning output of the CCD imaging device 1 is within the range of the dummy diode 21 and the CCD imaging device 1 is not reset.

As a result, the transistor 43 of the output processing circuit vfS40 is turned off during the reset 1 period, and the charging voltage of the capacitor 42 is always determined by the DC voltage component, so that the DC voltage component is correctly removed.

Note that since the first dummy diode 21 is covered with a light-shielding coating, the dark current component of the CCO imaging "1Afiff,1" is also removed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an outline of a conventional output processing circuit, a CCI image pickup device, and a timing circuit, and FIG. 2 is a time chart showing input and output of each part. FIG. 3 is a block diagram showing one embodiment of the present invention, and FIG. 4 is a time chart without showing the input/output of each part. 1: CCD imaging device 2: Photodiode array 21+22: Dummy diode 22: Image reading diode 3: Photogame 1~4: Shift 1~Register 5: Output circuit 6~8: 1~Ran register 9: Diode 10: Sample hold circuit 20: Timing circuit 40: Output processing circuit 50: Pulse generator (second goo 1 - signal generation means) 2
6-28.31-33: First gate signal generation means

Claims (1)

[Claims] In an image information reading device comprising an imaging device, a timing device for energizing the imaging device for reading and scanning, and an output processing device for processing output image information of the imaging device, the scanning output period outside the image area of the imaging device is provided. a first gate-off signal that produces a gate-off signal for a predetermined width of
and a second signal generating means for generating a gate-off signal while a reset signal pulse for resetting the output 1 of the imaging device and the potential of the transistor appears. The output processing device detects the DC level of the output of the imaging device while the gate-on signal is present and the gate-off signal is not present, and then outputs a signal obtained by removing the DC level from the output of the imaging device. An image information reading device comprising: