JPS60145773A - Clamping circuit - Google Patents

Abstract

PURPOSE:To make stable clamping action by clamping signals corresponding to a shaded part to remove noise and detecting optical black reference signal in the period. CONSTITUTION:A signal 3a, after passing through a coupling capacitor C1, is clamped to a potential charged to a capacitor C2 through a clamper 44 driven by clamping pulse 6c-1 as the first gate signal. The clamped signal becomes an input signal 4a of a signal processing circuit 5 consisting of an encoder circuit through a DC amplifier 41. Out of signal 4a, part of the signal of black level period corresponding to a shaded part OS is held by a sample holding circuit 42 driven by sample holding pulse 6c-2 as the second gate signal. An optical reference signal thus detected is compared with a reference voltage E and amplified by an error amplifier 43. Clamp error is supplied to a clamper 44 to cancel the error.

Description

TECHNICAL FIELD The present invention relates to a clamp circuit suitable for obtaining an accurate black level.

(Prior Art) Conventionally, when clamping a read signal in a video camera using a solid-state image sensor, for example, in order to obtain a stable optical black reference signal in each horizontal retrace period, In many cases, a light shielding section is provided on the imaging cell corresponding to the back porch. This is because the dark current, which is a factor in black level fluctuations in solid-state image sensors, approximately doubles when the element temperature rises by 8°C, and also because the general operating conditions of video cameras range from 11°C to +40°C. This is understandable considering that it extends to

For the above purpose, in general, several to several tens of imaging cells corresponding to the back porch during the horizontal retrace period of a solid-state imaging device are shielded from light to form only a dark stream, and the signal level of this portion is reduced. is clamped to a reference black level. In this case, to perform stable clamping operation,
It is desirable that a large number of imaging cells be allocated to the light shielding section.

However, if a large number of cells are used in the light-shielding portion, the number of imaging cells becomes insufficient due to the horizontal packing, and this has the disadvantage that the resolution further deteriorates.

On the other hand, increasing the number of imaging cells within a limited size means increasing the area and increasing the integration of the device, which is a difficult problem unless there is significant improvement in process technology.

As a solution to this problem, video cameras that use an image pickup tube generally use a feedback clamp method, that is, a clamp circuit that clamps the level during the beam blanking period to a reference level using the black level, and this clamped signal. Consider a system consisting of a process circuit that performs γ correction after amplifying the output of Her Crank”
A method of applying feedback to the level is being considered.

However, when this method is applied especially to solid-state imaging devices, noise tends to enter during the blanking period because the output amplifier of the solid-state imaging device has a floating structure. , clock noise is generated (approximately % of the saturation signal level) due to the signal readout transfer pulse. Therefore, if the light shielding part potential containing this clock noise is detected, compared with a certain reference level, and clamped as in the conventional method, there is a problem that the video signal cannot be reproduced with sufficient precision.

As a means to solve this problem, sample and hold means for removing the above-mentioned clock noise may be provided before the feedback clamp. However, when considering lower voltage and lower power consumption, even the sample and hold means generates clock noise of several tens of mV of command pulses.

-The force signal level is 8l-IJ of the solid-state image sensor.
Approximately % to % of the signal output level is used as the standard operating level, but normally the saturated signal output level of a solid-state image sensor is several hundred meters.
V, the signal level will be about 5 rn V. Therefore, the ratio of this signal level to each clock noise is approximately 20 dB, and the imaging device is required to maintain black level stability (or low frequency conversion noise of clock noise) of approximately -! In order to make j Od 13 or less, the performance of the feedback clamp circuit needs to be about -30 dB or less.

Further, when the above-described solid-state imaging device is used as a still camera for capturing still images, low power consumption and power start-up characteristics are required. That is, when the release switch (power switch) is turned on, the electric circuit must have the ability to quickly process the signal from the solid-state image sensor. For this reason, it is desirable to avoid capacitive Fit coupling as much as possible in the 4-Il electric circuit and to connect it directly.

However, when trying to connect directly, the output amplifier of the solid-state image sensor consists of an MO8 amplifier, and because of the variations in the MOS threshold voltage, a sample-and-hold device with a small dynamic range must be installed immediately after the solid-state image sensor. The signal must then be amplified and input to the clamp circuit. At this time, clock noise is also amplified, so the clamp circuit is required to have even greater potential stability. This is what I did.

In particular, the purpose is to provide a clamp circuit that can provide a stable black level.

(Example) The present invention will be described in detail below based on examples.

In the embodiment of the present invention, in order to eliminate the drawbacks of the prior art as described above, the light-transmitting part signal is clamped by a clamp pulse as the first gate signal having a wide pulse width, and the black level detection circuit By detecting the potential using a pulse as a second gate signal with a narrow pulse width,
This is an attempt to reduce the influence of clock noise.

DESCRIPTION OF THE PREFERRED EMBODIMENTS A detailed description of embodiments of the present invention will be given below with reference to the drawings.

@t+7 shows an example of the configuration of a solid-state image sensor applicable to the present invention, FIG. 2 is a block diagram showing an example of the signal processing system of the present invention, and FIG. 3 is a diagram showing waveforms of each part of FIG. 2. , FIG. 4 is a specific configuration diagram of the clamp circuit 4. As shown in FIG.

As is well known, solid-state image sensing devices can be roughly divided into MOS type and CCD type, but as an embodiment of the present invention, the case of frame transfer type COD will be explained, and such CCD type will be explained.
The OD is shown in FIG. As shown in Fig. 1, the frame transfer type CCD consists of an imaging section PD, a storage section 8D% readout register l (l), and an on-chip preamplifier AD. A light shielding portion O8 corresponding to a reference signal during clamping is provided.

In FIG. 2, l is a solid-state image sensor, 2 is a sample/hold circuit as a holding means of the present invention, 3 is an amplifier, 4 is a clamp circuit, 5 is a signal processing circuit, and 6 is a synchronization signal generation circuit as a signal generation means. It is. Also, in Figure 4, 4
1 is a DC amplifier, 42 is a sample and hold circuit, 43 is an error amplifier, 44 is a clamper as a clamping means, C
,, C2 is a capacitor, E is a reference power supply, and 45 is a clamp level forming circuit as a clamp level forming means.

The operation of the embodiment having the above configuration will be explained.

In FIG. 2, photoelectrons are generated by the incident light in the imaging section PD of the solid-state imaging device 1 driven by the drive pulse 6a from the synchronization signal generation circuit 6 as the imaging device driving means of the present invention, and a well-known potential well is formed. As a result, for example, 1 load of l field period is accumulated. Then, the four accumulated signal charges are transferred in parallel to the storage section 8D at intervals of vertical blanking, and in the next field period, the remaining charges for the next field are accumulated in the imaging section PDIC.

On the other hand, the signal charges in the storage section SD are transferred horizontally one row at a time to eight readout registers, and within one horizontal period, the signal in the black level period corresponding to the cell in the light shielding section O8 is first read out, and then the image pickup section The image signal 'charges accumulated in the PDK are sequentially read out in time series.

Moreover, in the present invention, even after reading one line of signals from the image pickup section FD, a blank read signal is obtained by supplying a drive pulse to the read register l.

Although the dark and current components in this empty read signal are relatively small,
It can be regarded as approximately the same as the dark peeking current level of the light shielding part O8.

The P A M (Pulse
The AmplitudeModulation) signal is schematically shown by the solid line 1a in FIG.

That is, in the PAM signal 1a, the portion 101 corresponds to the light shielding portion O8, the portion 102 corresponds to the continuous blanking period, and the portion 103 corresponds to the horizontal blanking period. These signals become signals 2a shown in the third diagram by a sample/hold pulse 6b (6b, sample, 6b, hold) shown in the third diagram in the subsequent sample/hold circuit 2.

That is, the clock noise 2a' of the sample and hold device is superimposed on the signal 2a. The signal 2a is amplified to an appropriate signal level by an amplifier 3, and DC reproduction is performed in a clamp circuit 4. Here, the above-mentioned clamp circuit 4 has a configuration as shown in FIG.
C) Clamp pulse 6cm as the first gate signal
1 through the clamper 44 driven by the capacitor C.
It is clamped to a certain potential charged to 2. This clamped signal passes through a DC amplifier 41 and becomes an input signal 4a to a signal processing circuit 5 consisting of an encoder circuit, etc. However, the signal portion of the signal 4a during the black level period corresponding to the light-shielding portion O8 is shown in FIG. ) is sampled and held by a sample and hold circuit 42 driven by a sample and hold pulse of 6 cm2 as a second gate signal. As a result, an optical reference signal is detected, and the error amplifier 43 compares and amplifies the detected signal and the reference voltage E to obtain a new lamp reference potential including the clamp error, and this signal is sent to the clamper 44. By supplying the signal, the error amount is canceled or the video signal 3a is clamped at the same time.

Incidentally, the clamp pulse 6C-1 shown in FIG.
This pulse is used to clamp the signal, but in this case, since the clock twist 2a' is superimposed on the video signal 2a, the clock noise 2a is also detected when the sample and hold circuit 42 detects the optical reference signal, resulting in stable stability. It becomes impossible to perform the clamping operation.

Therefore, in the embodiment of the present invention, as described above, the pulse 6C-1 having the timing as shown in FIG. 3(C) is used as a crank pulse. That is, the feature is that the clock noise of the light shielding section is removed by clamping the light shielding section 101 during the black level period. Stable clamping operation can be achieved by removing clock noise in the light-shielding portion, detecting the black level by the sample-and-hold circuit 42, and performing feedback clamping. If clamp pulse 6 c -1,!
: If the sample-and-hold pulse of 6 cm 2 is the same and has the same phase, for example, as shown in (B), the clamping operation will still not be stable. Because Clamper 44
This is because the trailing end Bl of the pulse is the most important in both cases. In other words, if the rear end is in phase with the clock noise,
In addition, since the ramp is performed at the first level of the clock noise, the clock noise remains without being removed even in the portion where the clock noise and the clamp pulse do not match in phase. There is a possibility that the remaining clock noise will be detected by the sample and hold circuit 42. Also in the sample and hold circuit 42, the trailing edge B2 of the pulse
Since this is important, the clamping capacitor CI and the clamper 440 are directly connected in the clamp circuit, and therefore the crank time constant is small. Therefore, a resistor may be inserted here to increase the crank time constant to create a soft clamp-like feedback clamp circuit. This is effective when the clock twist level is particularly large.

Also, clamp bar /L/ of the feedback clamp circuit,
The sample hold pulse for black reference detection of 6 cm2 may be appropriately delayed as X 6 c -1.

(Effects) As explained above, if the signal corresponding to the light shielding part is clamped to remove clock noise and the optical black reference signal is detected within that period, stable lamp operation is possible.

Also, since the clock noise removal circuit is not placed in front of the clamp circuit as in the past, but is placed next to it, there is no problem with the pulse noise of the removal circuit, and it is simply the trailing edge of the clamp pulse. The configuration is extremely simple because it is only necessary to delay the trailing edge of the black level detection sample and hold pulse a little in time.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the COD of the frame transfer method. FIG. 2 is a diagram showing an example of a block of a signal processing system, FIG. 3 is a waveform diagram of each part of FIG. 2, and FIG. 4 is a configuration diagram of -ψ1 of a feedback type clamp circuit according to the present invention. l is solid-state sensor, 2Fi, sample bold circuit%
3 is an amplifier, 4 is a clamp circuit, 5 is a signal processing circuit, 6
41 is a DC amplifier, 42 is a sample/hold circuit, 43 is an error amplifier, 44 is a clamper as a clamping means, and 45 is a clamp level forming circuit as a clamp level forming circuit. , 6c]L3 Clamp pulse 56cm2+ as the first gate signal and sample hold pulse as the second gate signal.

Claims (2)

[Claims] (1) Clamp means for clamping an input signal to a predetermined clamp level for a period corresponding to a first gate signal, and a clamp level for extracting the clamped signal for a period corresponding to a second gate signal to form the clamp level. A clamp circuit comprising a forming means and a signal generating means for outputting the first and second gate signals during a black level period of the signal. (2) The clamp according to claim 1, wherein the signal generating means outputs the trailing edge of the first gate signal temporally preceding the trailing edge of the second gate signal. circuit.