JPH04140985A - Output potential clamping device for solid-state image pickup element - Google Patents

Abstract

PURPOSE:To prevent yield from lowering and to suppress the occurrence of a vertical stripe fixed noise by providing the output potential clamping device of a solid-state image pickup element. CONSTITUTION:The signal of an optical black part is always inputted to clamping circuits 105, 106, and 107 in a horizontal blanking period by controlling the clocking of a sample-and-hold pulse. A clamping pulse is supplied as a first clamping pulse with width and a second clamping pulse with width after sample and hold in the latter half of the horizontal blanking period is restarted from a clock circuit 122 to the signal of the optical black part held in the first half of the horizontal blanking period. By performing such operation, the same effect that the number of picture elements of the optical black part is increased and a wide clamping pulse is supplied can be obtained even when the signal amplitude of input is changed steeply. Also, even when a defect exists in the picture element at a held part, it is hard to change potential only by one line because the final potential can be decided by the mean level of plural picture elements in the last half of the clamping pulse.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output potential clamping device for a solid-state imaging element in a solid-state imaging device.

(Conventional technology) FIG. 3 is a block diagram of the solid-state imaging device.

In the figure, 122 is a clock circuit that supplies necessary timing pulses to each part of the system.

Reference numeral 101 is a solid-state image sensor that converts an optical image guided by an optical system (not shown) into an electrical signal.
) and blue (B) are output with a phase difference of 120 degrees. 114 is a drive circuit that converts the pulse of the clock circuit 122 into a drive voltage for the solid-state image sensor 101. 102, 103, 10
4 is a sample hold (S/H) circuit for removing clock noise from the output of the solid-state image sensor 101.

105, 106, 107 are sample and hold circuits 10
This is a clamp circuit that fixes the potential so that the signal potential of the light shielding part (referred to as an optical black part) among the signals obtained from No. 2, 103, and 104 becomes the reference potential. 108
The outputs of the clamp circuits 105, 106, 107 are 12
This is a switching circuit that switches with a phase difference of 0 degrees, and its output is used as a luminance signal (Y). 109 is a luminance low-pass filter (YLPF) that removes unnecessary lock noise and limits the band of the luminance signal, 110.111.112
is a color low-pass filter (CLPF) that limits the band of the color signal.
).

115, 116, 117, and 118 are comma correction circuits that perform gamma correction on the luminance signal and color signal. 119
is a matrix calculation circuit that generates a luminance signal and a color difference signal from a comma-corrected luminance signal and R, G, and B signals. 120 is N from the output of the matrix calculation circuit 119
This is an encoder circuit that creates composite video signals based on systems such as TSC and PAL. 121 is an adder that adds the synchronization signal from the clock circuit 122.

FIG. 4 shows an example of the configuration of the solid-state image sensor 101 used in the solid-state image sensor shown in FIG. Here, a virtual phase type three-output frame transfer type CCD will be described. However, such a solid-state image sensor is already known and is described in other documents (IEE Trans, EIect
ron Devices, VoJ ED-32, Aug
UST 1985), so only a brief explanation will be given here. In FIG. 4, 201 is a light receiving section that also serves as a vertical transfer CCD, and a vertical transfer pulse φ
Driven by PI.

202 is a vertical transfer CCD which is shielded from light, is called a memory section, and is driven by a vertical transfer pulse φPS. 203
, 204, 205 are the first . Second. This is a third horizontal transfer CCD, and each horizontal transfer pulse φS1. φ
S2. Driven by φS3. 206,207,2
08 are the 1st. Second. This is the third output amplifier.

209 a to 209 c are the third
horizontal transfer CCD 205, third horizontal transfer CCD 205
to the second horizontal transfer CCD 204, the second horizontal transfer CC
This is a transfer gate that intervenes when transferring charges from D204 to the first horizontal transfer CCD 203, and is driven by a transfer gate pulse φd. FIG. 5 is an arrangement diagram of color filters for using the solid-state image sensor of FIG. 4 as a single-plate color solid-state image sensor, and one element of the color filter corresponds to one element of the light receiving section 201 of FIG. 4. It is pasted together to make it look like this. In the example of Figure 5, R,
It is composed of G and B vertical stripe filters. FIG. 6 shows the driving timing of the solid-state image sensor of FIG. 4, and the period from time t1 to tl is a vertical blanking period, during which the vertical transfer pulse φPI is generated.

φPS and transfer gate pulse φT are driven at high speed in the same phase, and all charges accumulated in the light receiving section 201 by tl are transferred to the memory section 202. Next time t2
to t3, charges for one line are transferred from the memory section 202 to the first horizontal transfer CCD 203 during the horizontal blanking period of one horizontal scanning period, and charges corresponding to the R filter are transferred to the first horizontal transfer CCD 203 via the transfer gates 209a to 209c. Charges corresponding to the G filter are transferred to the second horizontal transfer CCD 204.
The charges corresponding to the B filters are transferred to the third horizontal transfer CCD 205 so as to be distributed, and when the distribution is completed, the charges corresponding to R, G, and H are transferred to the first... Second. It is transferred horizontally at high speed by the third horizontal transfer CCD 203, 204, 205, and the output amplifier 206, 207°2
08, it is converted into a voltage and output.

FIG. 7 is an explanatory diagram of an optical black section provided in the light receiving section 201 of the solid-state image sensor 101 used in the conventional example, in which several lines are displayed during the vertical blanking period prior to scanning during the vertical scanning period, and horizontal blanking is performed prior to the horizontal scanning period. A light-shielding section called an optical black section is provided so that outputs of several light-shielded pixels can be obtained during a period. FIG. 8 shows the drive timing and clamp pulse timing during the horizontal scanning period of the solid-state image sensor 101 in the conventional example.
A horizontal blanking period begins after one line of charge is output at time t1. Horizontal blanking period t1 to t
We will explain that important operations are performed during 5. From tl to transfer gate pulse φT and vertical transfer pulse φ
s1 is driven with three pulses in opposite phase. Vertical transfer pulse φ
S2°φS3 is also driven in the same phase as the vertical transfer pulse φs1. By this operation, charges for one line in the final stage of the memory section 202 are distributed to the horizontal transfer CCDs 203, 204, and 205. After this operation is completed, the vertical transfer pulse φps is driven by one pulse, and the charges of the next line are transferred to the final stage of the memory section 202. Next, horizontal transfer of the distributed charges is performed. Several clocks after the start of horizontal transfer are idle transfers, and no charge from the light receiving section 201 is output. This is usually a horizontal transfer CCD, output amplifier 206~
This is because the number of transfer stages is greater than the number of horizontal pixels of the light receiving section 201 in order to guide the charge up to 208 . Next, from t4 to t5, the electric charge of the optical black portion described above is output. The above operations from tl to t5 must be performed within the horizontal blanking period.

The output of the first output amplifier 206 becomes Vol.

An output proportional to the amount of irradiation light is output in the negative direction. From t4 to t5, the dark charge output is interrupted. φSH is a pulse given to the sample bold circuit 102, and by sampling and holding it at a phase corresponding to the output of the solid-state image sensor 101, an output like S/Hout is obtained.

The polarity of S/Hout is inverted by an inverting amplifier built in the sample and hold circuit 102.

φCLP is a clamp pulse given to the clamp circuit 105, and has a width corresponding to the optical black portion. FIG. 9 is a circuit example of a clamp circuit used in a conventional example. 301 is a capacitor, 302 is a clamp switch, and 303 is a reference voltage source. Clamp switch 302 is turned on and off by clamp pulse φCLP.

Clamp pulse φCLP is turned on at high level. In normal operation, the capacitor 301 is charged and discharged by turning on the clamp pulse φCLP for a predetermined period during which the pixel output of the optical black portion is undulating.
The output potential of the optical black section is fixed to the reference potential VCLP of the reference voltage source 303. FIG. 10 is a diagram showing the waveforms of the input Vin and output Vout of the clamp circuit shown in FIG. 9 when the width of the clamp pulse φCLP is changed in the conventional example. FIG. 10(a) shows the input Vin of the clamp circuit, and FIG. 10(b) shows the output Vout when the width of the clamp pulse φCLP is narrow as shown in FIG. 10(C). (d) shows the output waveform Vout when the clamp pulse φCLP has a wide width as shown in (e) of the figure. When the clamp pulse width is narrow as in (C), the output potential of the optical black section can be stably fixed to the reference potential VCLP when the human power signal amplitude is constant, but if the human power signal amplitude suddenly increases. , the time constant for charging and discharging the capacitor 301 is constant, so when using a narrow clamp pulse, the output potential of the optical black section is set to the reference potential VC.
It takes time to make it into an LP. Clamp pulse is the first
When the voltage is wide as shown in FIG. 0 (e), it quickly reaches the reference potential VCLP as shown in FIG. 0 (d).

(Problem to be Solved by the Invention) In order to widen the clamp pulse width, it is necessary to increase the number of pixels in the optical black part.However, increasing the number of pixels in the optical black part is the first problem.
This means that the number of pixels in the solid-state image sensor increases, resulting in a decrease in yield. Second, since all signals in the optical black area must be output during the horizontal blanking period, in a solid-state image sensor with a multi-line readout structure, the distribution that should be added between t2 and t3 in Figure 8 is a pulse. , and the time allocated to the vertical transfer pulse becomes known. This causes fixed vertical stripe noise in a solid-state image pickup device that performs multi-line readout.

The present invention has been made to solve such problems, namely, the decrease in yield due to the above-mentioned reasons.

It is an object of the present invention to provide an output potential clamping device for a solid-state image sensor that can suppress the occurrence of fixed vertical stripe noise.

[Means to solve the problem]

In order to achieve the above object, the present invention configures an output potential clamping device for a solid-state image sensor as described in (1) above.

(1) A solid-state image sensor having one or more light-shielded pixels that are output at the beginning of a horizontal blanking period and a plurality of light-shielded pixels that are output at the end of the horizontal blanking period;
sample-and-hold pulse output means for inhibiting the output of a sample-and-hold pulse from the time when the outputs of the one or more light-shielded pixels are held until the signal of the first pixel among the plurality of light-shielded pixels is output; A first output potential clamp is performed during a period in which the output of the light-shielded pixel is held, and a second output potential clamp is performed during a period in which each output of the plurality of light-shielded pixels is sampled and held. An output potential clamping device for a solid-state image sensor, comprising a clamping means.

[Effect]

With the configuration (1) above, the output potential of the solid-state image sensor is
First, the output level of the shaded pixel that is being held is fixed to the reference potential, and then the output level of each of the plurality of shaded pixels is fixed to the reference potential.

(Example) The present invention will be explained in detail below with reference to Examples.

FIG. 1 is a timing chart showing the operation of the "output potential clamping device for a solid-state image sensor" which is a first embodiment of the present invention, and FIG. It is a figure showing a position.

As shown in FIG. 2, an optical black section of one or more pixels is also provided at the right end of the light receiving section 201 so that at least one pixel of the output of the optical black section can be obtained for each channel output even at the beginning of the horizontal blanking period. It is set up.

The operation of this embodiment will be explained below with reference to FIG.

The output of the optical black section provided at the right end of the light receiving section 201 is output at time t1 at the beginning of the horizontal blanking period. When the output of this pixel is held, the sample and hold pulse φSH from the clock circuit 122 (sample and hold pulse output means) is prohibited. Next, from time t4, when pixel output from the optical black section provided at the left end of the light receiving section 201 starts, clocking of the sample hold φSH is started again. As a result of this operation, the signal of the optical black portion is input to the clamp circuits 105, 106, and 107 during the horizontal blanking period. The clamp pulse φCLP is generated by the clock circuit 122 (
As shown in FIG. 1, a first clamp pulse with a width τ1 is applied to the optical black part signal held in the first half of the horizontal blanking period from the output potential clamping means), and A second clamp pulse with a width τ2 is applied after restarting the sample hold. As a result, even if the input signal amplitude changes rapidly, the same effect can be obtained as when increasing the number of pixels in the optical black portion and applying a wider clamp pulse. Furthermore, even if there is a defect in the pixels in the halted portion, the final potential is determined by the average level of a plurality of pixels in the second half of the clamp pulse, so it is unlikely that the potential will change by one line.

FIG. 11 is a timing chart explaining the operation of the second embodiment of the present invention. In this embodiment, the clamp pulse φCLP is one pulse per horizontal period, but as shown in the figure, the width is 1 for the signal of the optical black portion held in the first half of the horizontal blanking period, and the width is 1 at time t.
After 4, one pulse is applied every horizontal scanning period so that the width is multiplied by 2 after the sample hold is restarted in the latter half of the horizontal blanking period. This makes it possible to obtain the same effects as in the first embodiment.

It is also possible to obtain the same output as using the solid-state image sensor shown in Figure 2 by providing all the optical black parts at the right end of the light receiving part and making the horizontal transfer pulse timing intermittent. It goes without saying that the present invention can be carried out in any case.

〔Effect of the invention〕

As explained above, according to the present invention, the number of pixels in the optical book section is hardly increased, so the yield of solid-state image sensors is not reduced, and the clamping operation can be performed at high speed in response to sudden changes in signal amplitude. It becomes possible to follow
Moreover, since the time necessary for operating the multi-line readout solid-state image pickup device is not reduced, generation of vertical stripe fixed noise and the like can be prevented.

[Brief explanation of the drawing]

FIG. 1 is a timing chart showing the operation of the first embodiment of the present invention. FIG. 2 is a diagram showing the position of the optical black part of the solid-state imaging device used in the same embodiment. FIG. 3 is a block diagram of the solid-state imaging device. , FIG. 4 is a block diagram of the solid-state image sensor used in the solid-state image sensor shown in FIG. 3, FIG. 5 is a diagram showing the arrangement of color filters, FIG. Figure 7 is a diagram showing the optical black part of the solid-state image sensor used in the conventional example, Figure 8 is a timing chart showing the operation of the conventional example, Figure 9 is a circuit diagram of the clamp circuit, and Figure 10 is the clamp circuit in the conventional example. FIG. 11 is a timing chart showing the operation of the second embodiment of the present invention. 01...Solid-state image sensor 22-----Clock circuit

Claims (1)

[Claims] (1) A solid-state image sensor having one or more light-shielded pixels that are output at the beginning of a horizontal blanking period and a plurality of light-shielded pixels that are output at the end of the horizontal blanking period;
sample-and-hold pulse output means for inhibiting the output of a sample-and-hold pulse from the time when the outputs of the one or more light-shielded pixels are held until the signal of the first pixel among the plurality of light-shielded pixels is output; A first output potential clamp is performed during a period in which the output of the light-shielded pixel is held, and a second output potential clamp is performed during a period in which each output of the plurality of light-shielded pixels is sampled and held. 1. An output potential clamping device for a solid-state image sensor, comprising: clamping means.