JPS6010500A - Noise preventing circuit of ccd sensor output - Google Patents

Abstract

PURPOSE:To eliminate clock noises and imbalance by providing a DC regenerative circuit that performs DC regeneration by a pulse having width expanded over rising time of CCD sensor output and a sampling and holding circuit that samples and holds it. CONSTITUTION:A reset pulse RS and shift pulse SF are supplied from a transfer pulse generating circuit 12 to a discharge pulse sampling and resetting signal generating circuit 21. A delay circuit 22 delays SF by DELTAT and outputs the shift pulse SF'. An AND circuit 23 outputs a discharge pulse DC' having width expanded by DELTAT from rising time of picture element signals VS1, VS2 by RS and SF'. When a transistor 19 is turned on and a capacitor 20 is reset, clock noises N1, N2 etc. existing in the rise parts of VS1, VS2 etc. are reset to zero level, and picture signals P'' consisting of the same waveform CVs are generated on both ends of the capacitor 20. Outputs of the sampling holding circuit 15 are made to picture signals Q' free from imbalance by sampling pulses SA1, SA2 etc.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to a noise removal circuit for removing noise present in the output from a CCD (charge-coupled device) sensor, and more particularly to a noise removal circuit for removing noise present in the output from a CCD (charge-coupled device) sensor. The present invention relates to a CCD sensor output noise removal circuit that removes clock noise present in the CCD sensor and outputs a high quality image signal without imbalance.

Background of the Technology With the development of solid-state devices centered on integrated circuits, the use of solid-state image sensors that capture optical image information has progressed rapidly, and various solid-state image sensors have been proposed.

A CCD (Charge Couple) has both the function of accumulating signal charges excited by light and the function of transferring those charges
dDevice (charge-coupled device) is a fixed image sensor element using a charge transfer method.BBD (Bu
It is commonly used with a bucket brigade device (bucket brigade device). COD
Since it is an element that essentially performs charge transfer in one-dimensional direction, it is often used as a line sensor in a facsimile as a -dimensional line sensor in addition to a two-dimensional image sensor.

Prior Art and Problems FIG. 1 shows a conventional image sensor circuit using COD, and FIG. 2 shows its output waveform diagram. CCD
Transfer pulse generation circuit 12 drive pulse φ to sensor 11
1, φ2, shift pulse SF1, and reset pulse R3 are supplied, the CCD sensor 11 outputs both signals P as shown in FIG. In the image signal P, Vs
,,Vs2,... are pixel signals detected by the pixel sensor element in the CCD, Vrs is the cent signal generated by the reset pulse R3, N1, N2,...
. . . are clock noises generated by the drive pulses φl and φ2.

Both signals P are amplified by a preamplifier 13 and then subjected to DC regeneration by a DC regeneration circuit 14.

The 0 level of the image signal P is not accurate due to the drift of the CCD sensor 11 and the preamplifier 13. Therefore, this is accurately set to 0 level by the reset signal DC. This signal is supplied to sample and hold circuit 15. The sample/hold circuit 15 receives a DC reproduction signal and a sampling pulse SA from the sample/reset signal generation circuit 16.
The pixel signal Vsl is sampled by I.

Hereinafter, in the same manner, each pixel signal Vs2, VS of the image signal P
2.・Old... is sampling pulse S A 2, SA
3. . . . and held at the pixel signal level q2tq3y . As a result, the sample-and-hold circuit 15 extracts an image signal Q as shown in the second column.

The extracted image signal Q is amplified by both signals in the AGC circuit 17 and then binarized in the A/D converter 18.

By the way, in such a conventional circuit system, each pixel signal Vs, , V of the image signal P output from the CCD sensor 11 is
Although the levels of s2, . . .
, q2, ...... fluctuate alternately, and Sq I g
q39 """ is lower than q2 y q4 ?... by Δq.

The cause is that the DC regeneration circuit 14 does not perform accurate DC regeneration (signal P' in the figure), so a difference in ΔV occurs even when v2 = v3.

This phenomenon is caused by clock noise and is called imbalance, and has been a major cause of deteriorating the quality of image signals.

OBJECTS OF THE INVENTION An object of the present invention is to accurately extract the pixel signal part from the image signal output from the CCD sensor using a simple 1/8 circuit configuration, and to produce a high-quality image signal without imbalance due to clock noise. An object of the present invention is to provide a noise prevention circuit for the output of a CCD sensor that transmits information.

Structure of the Invention In order to achieve the above-mentioned object, the present invention provides a DC regenerating DC with a pulse having a width extended beyond the rising point of the CCD sensor output in order to match the 0 level of the output from the CCD sensor. It is characterized by having a reproduction circuit and a sample/hold circuit for sampling and holding the reproduction circuit, and removing clock noise and imbalance from the CCD sensor output.

Embodiments of the Invention The present invention focuses on the fact that there is a close relationship between clock noise and imbalance, and by sampling after removing clock noise from the CCD sensor output, it is possible to eliminate imbalance as well as clock noise. This is based on the knowledge that it can be removed. This point will be further explained with reference to FIGS. 3 and 4.

FIG. 3 shows an extracted portion of the DC regeneration circuit 14 shown in FIG. 1, in which 19 is a field effect transistor for discharging, and 2o is a capacitor. Figure 4 is a waveform diagram of each part, in which both signals P, Q, and discharge pulse D
C. The sampling pulse SA is the same as in FIG.

When the picture signal P from the preamplifier 13 (not shown) is applied to the DC reproduction circuit 14, each pixel signal V 91 ! of the picture signal P is output. An image signal I)' consisting of DC reproduction waveforms CV+, CV2, . . . of V S2 t, . . . is generated.

When the capacitor 20 is reset or discharged to zero level with the discharge pulses DCI and DC3, the charging start levels b1' and b3 fall below the zero level due to the clock noises Nl and N3 occurring in the negative direction, and this Pixel signals VSI, VS3 from negative charging start level b+, t13
Charging is started (P' in FIG. 4).

On the other hand, transistor 1 is discharged by discharge pulses DC2 and DC4.
9 is turned on and the capacitor 20 is reset, it is reset to zero level, and this zero level is charged.
However, in this case, charging due to clock noises N2 and N4 occurring in the positive direction is added, so that the waveform CV2. The voltage of CV4 is CVI, CV
3 (Fig. 4 p'>).

Therefore, the sampling level qItQ3 of the waveforms CVI, CV3 sampled by the sampling pulses SAI, SA3 is the same as that of the sampling pulses SA2. S.A.
Waveform CV2, CV4 sampled by 4
The sampling level of q2 and q4 is lower than that of q2 and q4. As a result, an image signal Q whose level alternately fluctuates for each sampling is sent out from the sample/hold circuit 15 (
Figure 4 P', SA, Q).

Therefore, clock noise N+, N2, N3, ·
If you sample after completely removing ......,
Along with clock twist, imbalance can also be removed.

Hereinafter, one embodiment of the present invention will be described based on FIGS. 5 and 6. FIG. 5 is a block diagram of the noise removal circuit of the present invention, and FIG. 6 is a diagram showing its operating waveforms.

In FIG. 5, elements common to those in FIG. 1 are given the same reference numerals. That is, 11 is a CCD sensor, 12 is a transfer pulse generation circuit, φ1 and φ2 are drive pulses, SF is a shift pulse, R3 is a reset pulse, P is an image signal, and SA
is a sampling pulse, 13 is a preamplifier, 14 is a DC regeneration circuit, 15 is a sample/hold circuit, 17 is A
GC circuit, 18 is an A/D converter.

Reference numeral 21 denotes a discharge pulse and sample/receive/node signal generation circuit of the present invention, and only the rear discharge pulse DC' generation portion is shown. In the figure, the 22nd shift pulse SF
The delay circuit 23 is an ant circuit that manually outputs the reset pulse R3 and the delayed shift signal SF' to output a new discharge pulse DC'.

The operation shown in FIG. 5 will be explained together with the operation waveform diagram shown in FIG. 6.

The lyse node pulse R3 is supplied from the transfer pulse generating circuit 12 to the AND circuit of the discharge pulse and sample lyse node signal generating circuit 21, and further to the AND circuit of the transfer pulse generating circuit 12.
A shift pulse SF is supplied to a delay circuit 22 of a discharge pulse and sample/reset signal generation circuit 21. The delay circuit 22 delays the shift pulse SF by ΔT and applies the shift pulse SF' to the AND circuit 23. ΔT is the clock twist N+ HN2 present in the image signal P,...
The value is selected to be larger than the width of... Note that the pulse width of the shift pulse SF is equal to each pixel signal Vs+ of both signals P.
, Vs2, etc., coincide with the time Trs when they do not exist.

The AND circuit 1/323 takes the AND of the reset pulse RS and the delayed shift pulse SF', and outputs each pixel signal V.
A discharge pulse DC' whose width is expanded by Δ1' from the rising point of s1, 'Vs2, etc. is output.

When the transistor I9 is turned on by this discharge pulse DC' and the capacitor 2o is reset, the clock noises Nl, N2, etc. present at the rising edge of each pixel signal Vs1, Vs2, etc. of the image signal P are all reset to zero level. , all have the same waveform CVs at both ends of capacitor 2o.
An image signal P'' consisting of the following is generated.

Therefore, when sampled by the sampling pulses SA1, SA2, etc., each waveform cS is sampled at the same level qs. As a result, both signals Q' sent out from the sample-and-hold circuit 15 have the same qs level and become unbalanced image signals Q', as shown in the figure.

Clock noise N1. Since the generation state of N2 etc. changes somewhat depending on the type of CCD sensor, if the delay circuit 22 is made variable to adjust the delay time of the shift pulse SF, the operation to remove noise and imbalance becomes easy. Become.

FIG. 7 shows an example of a circuit that makes the delay circuit 22 variable, and includes a delay section consisting of a variable resistor 24 and a capacitor 25, and a shaping amplifier 26. By changing the value of the variable resistor 24, shift pulse SF is generated according to the time width of clock noise occurrence.
' delay time, that is, the time ΔT of the discharge pulse DC'
fJ! If it is properly arranged, clock noise can be effectively removed.

When there is no delay circuit 22, the discharge pulse DC is the same as the conventional one.
Therefore, the present invention can completely eliminate clock noise and imbalance with a simple circuit configuration that only requires the addition of the delay circuit 22.

Note that the zero reset period TS' in which there is no pixel signal is slightly increased for both new signals Q', but since they are binarized by the A/D converter 18, there is no problem. Furthermore, since the width of the discharge pulse DC' is expanded, the level at the time of sampling becomes slightly lower, but since all pixel signals have a similar drop, there is no problem in this point either.

Further, it is advantageous to use the reset pulse R3 and shift pulse SF from the transfer pulse generation circuit 12 because the synchronization relationship is good, but it goes without saying that they may be generated by an independent pulse generator. .

As described in detail, according to the present invention, the clock noise present in the image signal output from the CCD sensor can be completely removed using a simple circuit configuration, and high quality images without imbalance can be obtained. Image signals can be obtained.

[Brief explanation of the drawing]

Figure 1 is a block diagram of a conventional image sensor circuit using COD, Figure 2 is an operation waveform diagram of Figure 1, Figure 3 is a circuit diagram of a DC regeneration circuit, and Figure 4 shows the operation and operation of Figure 3. A diagram explaining the principle of the present invention, FIG. 5 is a block diagram of an embodiment of the present invention,
FIG. 6 is an operational waveform diagram of FIG. 5, and FIG. 7 is an explanatory diagram of a variable delay circuit used in another embodiment of the present invention. 11... CCD sensor, 12... Transfer pulse generation circuit, 13... Preamplifier, 14...
...DC regeneration circuit, 15... Sample bold circuit, 16... Sample recess]
・Signal generation circuit, 17...AGC circuit, 18.
...A/D converter, 19...Transistor, 20...Capacitor, 21...Discharge pulse, sample/reset 71-signal generation circuit, 22...
...Delay circuit, 23...AND circuit, 2
4...Variable resistance, 25...Capacity, 26
・・・・・・Shaping amplifier. Patent applicant Fujitsu Ltd.

Claims (1)

[Claims] (1) A DC regeneration circuit that regenerates DC with a pulse whose width is extended beyond the rising point of the CCD sensor output in order to match the 0 level of the output from the CCD sensor, and a sample that samples and bolds the output of the circuit. - A CCD sensor output noise prevention circuit characterized by having a hold circuit and removing clock noise and imbalance from the CCD sensor output. 21. The CCD sensor output noise prevention circuit according to claim 11, wherein the width of the pulse extended beyond the rising edge of the CCD sensor output is variable.