JPS6028021B2 - Data transfer control method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an interface between devices, and in particular, to an interface between a channel device and a main memory controller, which enables efficient data transfer through a bidirectional data bus. Regarding transfer control method.

Generally, it is preferable that the number of signal lines in an interface be small.

Among these, in the case where a single device has connection ports for interfaces with a plurality of devices, reducing the number of signal lines becomes a particularly important problem. One possible solution to this problem is to adopt a so-called bidirectional data bus, in which the data bus, which accounts for most of the interface signals, is shared for transmission and reception.

This is especially effective when the bus width of the transferred data is wide. An example of a slave interface using a bidirectional data bus will be described with reference to FIGS. 1 and 2. FIG.

FIG. 1 shows the interface signals between device 1 and device 2.

Only the minimum necessary signals are shown here. Device 1 is the side that issues the transfer request, and device 2 is the side that accepts it. Interface signals include a transfer request signal from device 1, a tag signal indicating the type of request (transmission or reception), a request acceptance signal, response signal, bus direction indication signal from device 2, and bidirectional signals. There is a data bus. Next, the interface sequence will be explained according to FIG.

For convenience of explanation, it is assumed that the device 1 is a channel device, and the device 2 is a main storage control device. First, the reception operation will be explained.

A time chart in this case is shown in Figure 2A. A request signal and a tag signal indicating that the request is a reception request are
Sent from device 1 to device 2.

When the device 2 receives this request, it returns an acceptance signal and prepares the data to be received. Here, since the device 2 is assumed to be a main memory control device, it takes a certain amount of time until the reception data is ready to access the main memory. When the device 2 is ready with this received data, it places the data on the data bus and sends a response signal back to the device 1. At this time, the bus direction indication signal from the device 2 has a value indicating the direction in which data on the bus is transferred from the device 2 to the device 1. Next, in the case of a transmission operation, as shown in the time chart in FIG.

The device 1 then sets the transmit data on the data bus. If the device 2 can receive the transmission data, it sets the bus direction indication signal to a value indicating that the data on the bus is to be transferred from the device 1 to the device 2, and receives the transmission data on the bus. , returns an acceptance signal. After this,
The device 2 performs an operation of storing the received data in the main memory, and when this is completed, returns a response signal to the device 1. In this way, when the device 2 receiving the data transfer request is a main storage control device, it may take a considerable amount of time to return a response to the request from the device 1.
This is one of the reasons why the transfer capability of the interface is greatly reduced.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a data transfer control method for improving the transfer efficiency of an interface using a bidirectional data bus as described above. The present invention includes means for displaying the use status of the bidirectional data bus in a second device, and a request for use of the data bus based on a transmission request from the first device when the display means does not indicate that the bidirectional data bus is in use. and a priority circuit that selects one of the requests for use of the data bus based on the readiness of the data to be received based on the reception request from the first device, and the transfer of the received data via the data bus. and a response control circuit that returns a reception response related to the data transfer request to the first device and returns a transmission response to the first device when the processing of the transmission data is completed. The data transfer control method is characterized by the ability to issue the next data transfer request before the data is returned from the second device.

However, when this multiple data transfer is performed, the interface sequence becomes as shown in the time chart of FIG. 3, and a data bus contention problem occurs.

That is, as shown in FIG. 3, when the preceding request (2) is a reception request and the subsequent request (2) is a transmission request, a data bus contention between transmitted and received data occurs. Accordingly, another object of the present invention is to provide a means for dealing with the above-described bidirectional data bus contention problem when performing multiple data transfers.

However, a feature of the data transfer control method according to the present invention is that the usage status of the data bus is displayed in the device that receives the transfer request, which is connected to the device that generates the data transfer request via a bidirectional data bus. means for prioritizing requests for use of the data bus in connection with the means; and a data transfer operation corresponding to the request for use of the data bus until permission for use is granted by the priority means for the request for use of the data bus. The purpose of this invention is to provide a means for temporarily delaying the start of the process.

Next, an embodiment of the present invention will be described with reference to FIGS. 4 to 7.

Note that the interface signals between the devices are the same as in FIG. FIG. 4 shows the main part of the control circuit section in the device 2 on the side that receives data transfer requests.

When the device 2 receives a request signal from the device 1, it checks the contents of the tag signal in the request determination circuit 101, and if the request is a reception request, the reception request flip-flop (reception request FF
)102, and if it is a send request, send request FFI03.
Set. When the reception request FFI02 is set, that is, when a reception request is received, since no data bus contention occurs at that point, the request reception control circuit 104 immediately sends an acceptance signal back to the device 1, and then,
The reception request FFI02 is reset by the reception acceptance signal.

On the other hand, when a transmission request is received, data bus contention occurs, so the following control is performed.

When the transmission request FFI03 is set, its output is given to the request reception control circuit 104, and at the same time, is also input to the bus priority circuit 105 as a bus use request (transmission). This bus priority circuit 105 is provided with a reception response FFIO 9 when a reception response occurs within the device 2.
The bus usage request (reception) output from the bus is also input. The bus priority circuit 105 displays the bus in use display F.
If FI07 is set, requests for the use of either the transmitting or receiving bus will not be accepted, but the FFI indicating that the bus is in use will not be accepted.
If 07 is not set, permission is given to requests for use of the transmission and reception bus according to predetermined priorities. When a bus use request is granted, a bus use permission signal issued from the bus priority circuit 105 sets the bus use indication FFI07 via the OR circuit 100, and the other bus is used until the bus use of the request is completed. Prohibits permission of bus use requests.
When the transmission request FFI03 is set and the request reception control circuit 104 receives a bus use permission signal (transmission) from the bus priority circuit 105, the request reception control circuit 104 returns the reception signal to the device 1, and then sends the transmission reception signal to the device 1. After that, the transmission request FFI03 is reset by the transmission acceptance signal.

Furthermore, when the bus line use permission signal (transmission) is issued, the bus line direction indicator FFIII is reset, and the bus line direction indication signal is set to a value that indicates that the direction of the data bus line is from device 1 to device 2. Ru. When the processing of the transmission request or reception request from device 1 is completed, device 2 returns a response signal to device 1, which is controlled by response control circuit 110. In the case of a response to a transmission request, bus contention does not occur.

Therefore, when the transmission response FFI08 is set by the transmission response issued upon completion of the processing of the transmission request, the response control circuit 11
0 immediately sends a response signal back to device 1. Thereafter, the transmission response FFI08 is reset by the transmission response signal.
On the other hand, in the case of a response to a reception request, bus contention occurs, so the following control is performed.

When the reception request processing is completed and a reception response is issued, the reception response FFIO9 is set and the bus priority circuit 10
A bus use request (reception) is issued for 5. This received bus usage request is granted, and the bus priority circuit 105
When the busbar use permission signal (reception) is output from the device 1, the response control circuit 110 returns a response signal to the device 1. At this time, the bus direction indicator FFIII is set by the bus use permission signal (reception), and the bus direction indication signal is set to a value indicating the direction from device 2 to device 1. Thereafter, the reception response FFIO9 is reset by the reception response signal. Note that when the bus priority circuit 105 permits use of the bus and the use of the bus ends, the request reception control circuit 104 or the response control circuit 110 outputs a bus use end signal.

These bus use end signals pass through the off circuit 106 to reset the bus use indicator FFI07. FIG. 5 schematically shows the flow of data between devices 1 and 2 and within each device. When sending data from device 2 to device 1 (in the case of reception), since the aforementioned bus direction indicator FFI I is set, the data (received data) set in the input/output data register 121 is sent to both sides through the bus driver 123. It is placed on the tropic data bus 124.

On the other hand, a signal obtained by inverting the bus direction instruction signal, which is the output of the bus direction display FFIII, by the inverter 22 is given to the device 1 as the bus direction instruction signal 125 of the inter-device interface, so the bus driver 126 in the device 1 is inhibited. The data on the data bus 124 is taken into the input/output data register 127. The above reception response is
This occurs when received data is prepared in the input/output data register 21 of the device 2. When sending data from device 1 to device 2 (in the case of transmission), the bus direction display FFI 11 is reset, so the input/output data register 127 in device 1
The transmission data set to 0 is passed through the bus driver 126 and placed on the data bus 124. This transmission data is taken into the input/output data register 121 of the device 2. When the capture of this transmission data is completed and the transfer to the main storage device is completed, the above-mentioned transmission response is issued (if the device 2 is a main storage control device). The contention between the transmitting and receiving data buses is controlled in the manner described above, and an example thereof will be explained with reference to the time charts of FIGS. 6 and 7. FIG. 6 is a time chart when a reception response to a previous transmission request and a next transmission request signal occur simultaneously.

In this case, requests to use the transmitting and receiving buses are issued at the same time. The bus priority circuit 105 first grants a bus use request from the transmitting side at the bus priority timing according to a predetermined priority order. As a result, bus bar use indication OFF FI07 is set, and permission of the bus bar use request on the receiving side is temporarily prohibited. Also, the bus direction display FFI I
I is reset. After returning the transmission request reception signal to the device 1, the request reception control circuit 104 transmits the transmission request FF.
Reset I03. When the reception of the transmission data from the device 1 is completed, the request reception control circuit 104 outputs a bus usage end signal, the bus usage indication FFI07 is reset, and the inhibition on the bus priority circuit 105 is released. At this point, the transmission request FFI03 has been reset and there is no longer a request to use the bus for transmission, so the bus priority circuit 105 grants a request for use of the bus for reception at the next bus priority timing.

As a result, the bus direction indicator FFIII is set, and the received data prepared in the input/output data register 121 of the device 2 is placed on the data bus. The response control circuit 110 returns the response signal to the device 1 and resets the reception response FFIO 9 using the reception response signal. When the transfer of the received data is completed, the response control circuit 110 resets the bus in use table FFI07 by the bus use end signal, and thereby the bus priority circuit 105 becomes in a state where it can approve a new bus use request. FIG. 7 is a time chart when a transmission request is issued from the device 1 immediately after a reception response is issued.

In this case, the bus priority circuit 105 grants the transmission bus use request first, so acceptance of the transmission request is delayed until the device 2 finishes transmitting the received data and the data bus is released. When the transmission of the received data is completed and the response control circuit 110 sets the bus use indication FF1.07 to IJ by the bus use end signal, the bus priority circuit 105 approves the bus use request for transmission. As a result, the request reception control circuit 104 accepts the transmission request, sends an acceptance signal back to the device 1, and data transmission from the device 1 begins. According to the present invention, as detailed above,
Multiple data transfer based on multiple transfer requests becomes possible, and the transfer capacity of a data transfer system using a bidirectional data bus can be greatly improved, and the effect is remarkable.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an inter-device interface using a bidirectional data bus, FIG. 2 is a time chart for explaining slave data transfer control in the inter-device interface of FIG. 1, and FIG. Figures 4 to 7 are time charts for explaining the data bus contention problem when multiple data transfer is performed using the inter-device interface shown in Figure 1.
The figures explain one embodiment of the present invention. Fig. 4 is a block diagram showing the main control circuitry within the device that receives the transfer request, and Fig. 5 shows the data transfer between the devices and within each device. A schematic block diagram showing the flow and main circuits for its control, and FIGS. 6 and 7 are time charts for explaining the operation of the above embodiment. 101...Request determination circuit, 102...Reception request FF, 103...Transmission request FF, 104...
...Request acceptance control circuit, 105... Bus priority circuit, 107... Bus bar in use display F
F, LI'08... Transmission response FF, 109...
...Reception response FF, 1 10...Response control circuit, 111...Bus line direction display FF, 1.21,1
27...I/O data register, 123, 126...Bus driver, 124...Data bus line. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7

Claims (1)

[Claims] 1. In a system that transmits and receives data through a bidirectional data bus between a first device that issues a data transfer request and a second device that receives a data transfer request, means for displaying the usage status of the data bus; and a means for displaying a usage status of the data bus based on a request for use of the data bus based on a transmission request from the first device and a reception request from the first device when the display means does not indicate that the data bus is in use. a priority circuit that selects one of the requests for use of the data bus line due to the completion of preparation of the data to be sent; and a priority circuit that returns a reception response related to the transfer of the received data to the first device, and processing of the transmission data is completed. By including a response control circuit that returns a transmission response to the first device, the next data transfer request can be issued before the response to the data transfer request issued by the first device is returned from the second device. A data transfer control method characterized by making it possible to