JPS6027147A - Semiconductor device and manufacture thereof - Google Patents
Semiconductor device and manufacture thereofInfo
- Publication number
- JPS6027147A JPS6027147A JP13419683A JP13419683A JPS6027147A JP S6027147 A JPS6027147 A JP S6027147A JP 13419683 A JP13419683 A JP 13419683A JP 13419683 A JP13419683 A JP 13419683A JP S6027147 A JPS6027147 A JP S6027147A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- film
- semiconductor device
- layer
- metallic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の配線構造とその製造方法に関する
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a wiring structure of a semiconductor device and a manufacturing method thereof.
従来、半導体装置におけるＳｔ配紳は第１図に示す如六
断面構造となっていた、すなわち、ｓｊ基板１の表面に
は拡散層２が形成され、Ｓｉ基板１の表面に形成された
絶縁膜３を介して形成されたＳｉ配線４とは絶縁膜３に
開けられたコンタタト穴を通して接続されて成るのが通
例であった。Conventionally, the St element in a semiconductor device has a cross-sectional structure as shown in FIG. It was customary to connect to the Si wiring 4 formed through the insulating film 3 through a contact hole made in the insulating film 3.
しかし上記従来技術によると、Ｓｔ配紳の配線抵抗が大
であること及び上部金属配線とのコンタクト抵抗が大で
あるという欠点があった。However, the above-mentioned prior art has disadvantages in that the wiring resistance of the St wiring is high and the contact resistance with the upper metal wiring is high.
上記従来技術の欠点をなくするための本発明の基本的な
構成は、半導体装置に於てｓｊ配線層の少なくとも側面
を含む表面にはＣ！７４． Ｗ、ＭＯ，Ｔｉ等の金属膜
が形成されて成ること、及び半導体装置の製造法に於て
前記金属膜をメッキ処理で形成すること、及び半導体装
置に於て前記金属膜上にはＡ１層が形成されて成ること
を特徴とする。１、以丁、実施例により本発明を詳述す
る。The basic structure of the present invention for eliminating the drawbacks of the prior art described above is that in a semiconductor device, C! 74. A metal film such as W, MO, Ti, etc. is formed, and in the manufacturing method of the semiconductor device, the metal film is formed by plating treatment, and in the semiconductor device, an A1 layer is formed on the metal film. It is characterized by the formation of 1. The present invention will be explained in detail with reference to Examples.
第２図は本発明の一実施例を示す半導体装置に於ける配
線構造を示す断面図である。Ｓｉ基板１１の表面ＶＣは
拡散層１２、絶縁膜１３が形成され、該絶縁膜１３上Ｖ
ｃけＳｉ配線１４が形成さノ］、該Ｓｉ配＃は拡散層１
２と絶縁膜１３に開けられたコンタクト穴を通して接続
されると共に、該Ｓｉ配、Ｉｉ！１４の表面ＶｃけＣｕ
等の金属メッキ液に浸漬して形成したα等の金属膜１５
がＳｉ配線１４の側面に迄形成されて成る。FIG. 2 is a sectional view showing a wiring structure in a semiconductor device showing an embodiment of the present invention. A diffusion layer 12 and an insulating film 13 are formed on the surface VC of the Si substrate 11.
The Si interconnection 14 is formed in the diffusion layer 1.
2 through a contact hole made in the insulating film 13, and the Si interconnection, Ii! 14 surface Vc ke Cu
A metal film 15 such as α formed by immersion in a metal plating solution such as
is formed up to the side surface of the Si wiring 14.
本発明の如く、Ｓｉ配線の側面に迄金属膜を形成するこ
とにより、Ｓｉ配線の配線抵抗が極めて小さくできると
共に、上記Ａｌ配線等とのコンタクト部でのコンタクト
抵抗も小さくできる効果がある。By forming a metal film up to the side surface of the Si wiring as in the present invention, the wiring resistance of the Si wiring can be extremely reduced, and the contact resistance at the contact portion with the Al wiring etc. can also be reduced.
本発明けＳ＜配線上の金属膜形成にとどまらず、更に、
Ａ１層等の配線全面又は部分的に形成しても良い。The present invention is not limited to forming a metal film on wiring;
It may be formed entirely or partially on the wiring such as the A1 layer.
第１図は従来技術による半導体装置の凹面図、第２図は
本発明の一実施例を示す半導体装置の断面図である。
１．１１・・・・・・Ｓｉ基板
２．１２・・・・・・拡散層
５．１３・・・・・・絶絹・膜
４．１４・・・・・・Ｓｉ配線層
１５・・・・・・金属膜
以上
出願人 株式会社 諏訪精工舎FIG. 1 is a concave view of a semiconductor device according to the prior art, and FIG. 2 is a sectional view of a semiconductor device showing an embodiment of the present invention. 1.11... Si substrate 2.12... Diffusion layer 5.13... Silk film 4.14... Si wiring layer 15... ...Applicant for metal films and above Suwa Seikosha Co., Ltd.
Claims (3)
ｎ、Ｎ（、ＭＯ，Ｗ、Ｔｉ等の金属膜が形成されて成る
ことを特徴とする半導体装置。(1) The surface of the Bi wiring layer, including at least the side surfaces, has a
A semiconductor device characterized in that a metal film such as n, N(, MO, W, Ti, etc.) is formed.
ッキ液に浸漬し、ａｕ、 Ｎｉ、ＭＯ，Ｗ、Ｔｉ等の金
属膜を形成することを特徴とする半導体装置の製造方法
。(2) A method for manufacturing a semiconductor device, which comprises immersing the surface of the E3i wiring layer, including at least the side surfaces, in a plating solution to form a metal film of au, Ni, MO, W, Ti, or the like.
、 Ｍｏ 。 Ｗ 、 Ｔｉ等の金属膜上にけＡ１層が形成されて成る
ことを特徴とする判導体装置。(3) Cqt and Ni formed on the surface of the Si wiring layer
, Mo. A conductor device characterized in that an A1 layer is formed on a metal film such as W or Ti.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13419683A JPS6027147A (en) | 1983-07-22 | 1983-07-22 | Semiconductor device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13419683A JPS6027147A (en) | 1983-07-22 | 1983-07-22 | Semiconductor device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6027147A true JPS6027147A (en) | 1985-02-12 |
Family
ID=15122674
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13419683A Pending JPS6027147A (en) | 1983-07-22 | 1983-07-22 | Semiconductor device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6027147A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100728945B1 (en) * | 2001-06-27 | 2007-06-15 | 주식회사 하이닉스반도체 | A method for fabricating metal line |
-
1983
- 1983-07-22 JP JP13419683A patent/JPS6027147A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100728945B1 (en) * | 2001-06-27 | 2007-06-15 | 주식회사 하이닉스반도체 | A method for fabricating metal line |
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