JPS594876B2 - Thick film circuit board and its manufacturing method - Google Patents

Thick film circuit board and its manufacturing method

Info

Publication number
JPS594876B2
JPS594876B2 JP53120744A JP12074478A JPS594876B2 JP S594876 B2 JPS594876 B2 JP S594876B2 JP 53120744 A JP53120744 A JP 53120744A JP 12074478 A JP12074478 A JP 12074478A JP S594876 B2 JPS594876 B2 JP S594876B2
Authority
JP
Japan
Prior art keywords
solder
paste layer
gold
circuit board
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP53120744A
Other languages
Japanese (ja)
Other versions
JPS5546575A (en
Inventor
民雄 斎藤
義孝 福岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP53120744A priority Critical patent/JPS594876B2/en
Publication of JPS5546575A publication Critical patent/JPS5546575A/en
Publication of JPS594876B2 publication Critical patent/JPS594876B2/en
Expired legal-status Critical Current

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Description

【発明の詳細な説明】 この発明は耐半田性に優れた厚膜回路基板およびその製
法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thick film circuit board with excellent solder resistance and a method for manufacturing the same.

0 厚膜回路基板は主として金ペーストおよび絶縁体ペ
ーストによつて回路が構成されるが、金ペーストは耐半
田性が悪いため、基板との接着性が劣化し易く半導体製
品の信頼性を損なう原因となるなどの問題があつた。
0 Thick-film circuit boards mainly consist of circuits made of gold paste and insulating paste, but gold paste has poor solder resistance, so its adhesion to the board tends to deteriorate, causing a loss in the reliability of semiconductor products. There were problems such as.

そのため、金ペースト上に5 蒸着、メッキ等により金
ペーストよりも半田に対する拡散係数の低い物質の被膜
を形成することが考えられるが、その場合、たとえば金
厚膜上では該厚膜が多孔質であるため、この上に蒸着あ
るいはスパッタリングで低拡散物質を被膜させるので0
は、程度の差は多少あるが、やはり多孔質の被膜がで
きることと、冷却速度の不均一等により格子欠陥ができ
る。しかして、半田はこのような孔や格子欠陥に沿つて
速やかに拡散するので金厚膜上に形成された蒸着膜やス
パッター膜では、半田、’5 特にSn/Pb半田に対
して、半田の拡散防止効果を十分に奏し難い。他方、絶
縁体厚膜上では、該厚膜が多孔質のため、電気メッキを
おこなつたのでは下部電極と短絡したり、孔の中にメッ
キ液が残留したりして、製品の信頼性を損うおそれがに
0あり好ましくない。従つて、金ペースト層と絶縁ペー
スト層が表面に露出している厚膜回路基板において、耐
半田性を向上させるためにメッキによる被膜又は蒸着や
スパッタリングによる被膜のみを形成するのは、i5上
記説明から明らかなように好ましくなかつた。
Therefore, it is conceivable to form a film of a substance with a lower diffusion coefficient for solder than the gold paste by vapor deposition, plating, etc. on the gold paste, but in that case, for example, on a thick gold film, the thick film is porous. Therefore, since a low-diffusion material is coated on top of this by vapor deposition or sputtering, the
Although there are some differences in degree, lattice defects are still formed due to the formation of a porous film and non-uniform cooling rate. However, since solder quickly diffuses along such holes and lattice defects, in vapor-deposited or sputtered films formed on thick gold films, solder, particularly Sn/Pb solder, is Difficult to achieve sufficient diffusion prevention effect. On the other hand, since the thick film is porous, electroplating on a thick insulator film may cause a short circuit with the lower electrode or the plating solution may remain in the pores, resulting in poor product reliability. There is zero risk of damage to the product, which is not desirable. Therefore, in a thick film circuit board where the gold paste layer and the insulating paste layer are exposed on the surface, forming only a coating by plating or a coating by vapor deposition or sputtering in order to improve solder resistance is in accordance with the above explanation in i5. As is clear from this, it was not desirable.

この発明は上記事情に鑑みてなされたものであつて、半
田に対して長期信頼性を有する厚膜回路基板およびその
製法を提供することを目的とする。すなわち、この発明
は金ペースト層と絶縁ペースト層とを具備してなる厚膜
回路基板であつて、露出している金ペースト層上に、半
田に対し金よりも拡散係数の小さい金属のメツキ層が被
覆され、絶縁ペースト層上には半田中に拡散する係数よ
りも半田が拡散してくる係数の方が大きい金属の蒸着膜
またはスパツタ一膜が被覆されていることを特徴とする
厚膜回路基板、ならびにその製造法として、回路基板上
に、半田に対し、金よりも拡散係数の小さい金属、ある
いは半田中へ拡散する速度よりも、半田が拡散してくる
速度の方が大きい金属を蒸着またはスパツタリングで被
膜せしめ、絶縁体によつて被覆されていない金ペースト
上にのみ、半田に対し金よりも拡散係数の小さい金属を
選択メツキをおこない、ついで該メツキ部分と、絶縁体
上の所定の回路パターンを形成すべき部分とを除いた他
の部分の上記蒸着膜またはスパツタ一膜を選択的エツチ
ング除去することを特徴とする厚膜回路基板の製法を提
供するものである。以下、この発明を図示の一実施例に
基づいて説明する。第1図は耐半田性処理を末だ施して
いない厚膜回路基板を示すもので半導体装置基板1上に
、金ペースト層2および該金ペースト層2と一部重複す
るようにして、絶縁体ペースト層3がそれぞれ被着され
ている。まず、この金ペースト層2および絶縁体ペース
ト層3上に、半田に対し金よりも拡散係数の小さい金属
又は半田中へ拡散する速度よりも、半田が拡散してくる
速度の方が大きい金属たとえば、Ni,Cu等からなる
厚さたとえば1〜8μの蒸着膜あるいはスパツタ一膜4
を被覆させる。なお、この場合、接着強度を良くするた
め、これら蒸着膜あるいはスパツタ一膜4の形成は必要
に応じ、予め酸化し易く、かつ酸素との結合の力の大き
い金属、たとえばCr,Ti,,Ni等からなる接着層
5を蒸着、スパツタリング等の手段によつて金ペースト
層2および絶縁体ペースト層3上に形成したのちにおこ
なつてもよい(第2図参照)。つぎに、絶縁体ペースト
層3によつて被覆されていない部分の金ペースト層2上
のみが開口するようにして、フオトレジスト層6をパタ
ーニングする(第3図参照)。
The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a thick film circuit board that has long-term reliability with respect to solder, and a method for manufacturing the same. That is, the present invention is a thick film circuit board comprising a gold paste layer and an insulating paste layer, and a plating layer of a metal whose diffusion coefficient is smaller than that of gold for solder on the exposed gold paste layer. A thick film circuit characterized in that the insulating paste layer is coated with a vapor-deposited film or a sputtered film of a metal whose coefficient of diffusion of the solder is larger than the coefficient of diffusion into the solder. The substrate and its manufacturing method include vapor deposition of a metal that has a lower diffusion coefficient than gold for solder, or a metal that diffuses faster than the solder into the solder, onto the circuit board. Alternatively, a metal with a diffusion coefficient smaller than that of gold for solder is selectively plated only on the gold paste that is not covered with an insulator by sputtering, and then the plated part and a predetermined area on the insulator are plated. The present invention provides a method for producing a thick film circuit board, characterized in that the vapor deposited film or the sputtered film is removed by selective etching in a portion other than a portion where a circuit pattern is to be formed. The present invention will be explained below based on an illustrated embodiment. FIG. 1 shows a thick-film circuit board that has not been subjected to solder-resistant treatment.A gold paste layer 2 and an insulator are placed on a semiconductor device substrate 1 so as to partially overlap the gold paste layer 2. A paste layer 3 is applied in each case. First, on the gold paste layer 2 and the insulating paste layer 3, a metal having a smaller diffusion coefficient than gold for the solder or a metal with which the solder diffuses at a higher rate than the rate at which the solder diffuses into the solder, for example, , a vapor deposited film or a sputtered film 4 having a thickness of 1 to 8 μm, for example, made of Ni, Cu, etc.
to be coated. In this case, in order to improve the adhesive strength, the vapor-deposited film or sputtered film 4 may be formed using a metal that is easily oxidized and has a strong bonding force with oxygen, such as Cr, Ti, Ni, etc., if necessary. The bonding layer 5 may be formed on the gold paste layer 2 and the insulating paste layer 3 by means such as vapor deposition or sputtering (see FIG. 2). Next, the photoresist layer 6 is patterned so that only the portions of the gold paste layer 2 not covered by the insulating paste layer 3 are opened (see FIG. 3).

ついで半田に対し金よりも拡散係数の小さい金属、たと
えばCu,Niからなる厚さたとえば5〜15μのメツ
キ層7を上記フオトレジスト層6の開口部に形成したの
ち、該フオトレジスト層6を除去する(第4図参照)。
つぎに、メツキ層7および絶縁体ペースト層3上の所定
の回路パターン形成部分のみにエツチング用レジスト膜
8を露光、現像により形成し(第5図参照)、他の部分
の蒸着又はスパツタ一膜4および接着層5を選択的にエ
ツチング除去したのち、レジスト膜8を除去する(第6
図参照)。この結果、厚膜回路基板は絶縁ペースト層3
から露出している金ペースト層2部分は完全に半田に対
し金よりも拡散係数の小さい金属で覆わ法しかもこの種
金属のメツキ層7によるレベリング効果により、金ペー
スト層2の多孔性は失わへまた格子欠陥の少ないものが
得られるから、半田の拡散を著るしく防止することがで
き、耐半田性が良好となる。
Next, a plating layer 7 made of a metal having a diffusion coefficient smaller than that of gold for solder, such as Cu or Ni, and having a thickness of 5 to 15 μm, for example, is formed in the opening of the photoresist layer 6, and then the photoresist layer 6 is removed. (See Figure 4).
Next, an etching resist film 8 is formed by exposure and development only on the predetermined circuit pattern formation portions on the plating layer 7 and the insulating paste layer 3 (see FIG. 5), and the other portions are deposited or sputtered. 4 and the adhesive layer 5 are selectively etched away, and then the resist film 8 is removed (sixth
(see figure). As a result, the thick film circuit board has an insulating paste layer 3
The part of the gold paste layer 2 exposed from the solder is completely covered with a metal whose diffusion coefficient is smaller than that of gold for the solder.Moreover, due to the leveling effect of the plating layer 7 of this type of metal, the porosity of the gold paste layer 2 is lost. Further, since a product with few lattice defects can be obtained, solder diffusion can be significantly prevented, and the solder resistance is improved.

他方、絶縁体3上に形成された蒸一着またはスパツタ一
膜4からなる金属パターンは上記メツキ時にメツキ液に
さらされないため、メツキ液が残留することもなければ
絶縁体ペースト層3下方の金ペースト層2との間で絶縁
不良となるおそれもない。なお、蒸着またはスパツタ一
膜4は多孔質の膜であるので、メツキ層7と比較して半
田に対し早く拡散する。
On the other hand, since the metal pattern formed on the insulator 3, consisting of a single vapor-deposited or sputtered film 4, is not exposed to the plating solution during the plating process, no plating solution remains and the metal below the insulator paste layer 3 is not exposed to the plating solution. There is no risk of poor insulation between the paste layer 2 and the paste layer 2. Note that since the vapor-deposited or sputtered film 4 is a porous film, it diffuses into the solder more quickly than the plating layer 7.

しかし、蒸着またはスパツタ一膜4の材料として、Cu
,Niを用いた場合、CuやNiが半田、たとえばSn
,Pb,In等の合金へ拡散する拡散係数がSn,Pb
,In等の合金がCuやNlに拡散する拡散係数より小
さいため、いわゆるカーケンドールボードが絶縁体ペー
スト層の接着面に発生せず、したがつて、基板との接着
性が失われることもない。しかして、この発明に係わる
厚膜回路基板は上述の如く耐半田性が良好なため、長期
信頼性を有するものとなる。
However, as a material for the vapor-deposited or sputtered film 4, Cu
, Ni, when Cu or Ni is used as a solder, for example, Sn
, Pb, In, etc., the diffusion coefficient of Sn, Pb, etc.
, In and other alloys are smaller than the diffusion coefficient of Cu and Nl, so the so-called Kirkendall board does not occur on the bonding surface of the insulating paste layer, and therefore the adhesion with the substrate will not be lost. . Since the thick film circuit board according to the present invention has good solder resistance as described above, it has long-term reliability.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第6図は本発明に係わる厚膜回路の基板の
製造法を工程順に示す厚膜回路基板の要部断面図である
。 図中、1・・・・・・基板、2・・・・・・金ペースト
層、3・・・・・・絶縁体ペースト層、4・・・・・・
蒸着またはスパツタ一膜層、5・・・・・・接着層、6
・・・・・・フオトレジスト層、7・・・・・・メツキ
層、8・・・・・・エツチング用レジスト膜。
1 to 6 are sectional views of essential parts of a thick film circuit board showing the method of manufacturing a thick film circuit board according to the present invention in order of steps. In the figure, 1...substrate, 2...gold paste layer, 3...insulator paste layer, 4...
Vapor deposition or sputtering single layer, 5... Adhesive layer, 6
. . . Photoresist layer, 7 . . . Plating layer, 8 . . . Etching resist film.

Claims (1)

【特許請求の範囲】 1 金ペースト層と絶縁ペースト層が表面に露出してい
る厚膜回路基板において、露出している金ペースト層上
に半田に対し金よりも拡散係数の小さい金属のメッキ層
を形成し、露出している絶縁ペースト層上に半田中に拡
散する係数よりも半田が拡散してくる係数の方が大きい
金属の蒸着膜またはスパッタ膜を形成したことを特徴と
する厚膜回路基板。 2 金ペースト層と絶縁ペースト層が表面に露出してい
る厚膜回路基板上に、半田に対し金よりも拡散係数の小
さい金属あるいは半田中へ拡散する速度よりも半田が拡
散してくる速度の方が大きい金属を蒸着またはスパッタ
リングで被膜し、ついで前記露出している金ペースト層
上に半田に対し金よりも拡散係数の小さい金属のメッキ
を行ない、ついでこのメッキ部分と絶縁ペースト層の半
田付けをする部分を除いた部位の前記蒸着またはスパッ
タリング被膜をエッチング除去することを特徴とする厚
膜回路基板の製法。 3 蒸着またはスパッタリング被膜形成工程を、予め回
路基板上に酸素との結合力が大きい易酸化性金属被膜を
形成させたのちにおこなうことを特徴とする特許請求の
範囲第2項記載の回路基板の製法。
[Claims] 1. In a thick film circuit board in which a gold paste layer and an insulating paste layer are exposed on the surface, a plating layer of a metal having a diffusion coefficient smaller than that of gold for solder is provided on the exposed gold paste layer. A thick film circuit characterized in that a vapor deposited film or a sputtered film of a metal whose coefficient of diffusion of the solder is larger than the coefficient of diffusion into the solder is formed on the exposed insulating paste layer. substrate. 2. On a thick film circuit board with a gold paste layer and an insulating paste layer exposed on the surface, use a metal with a lower diffusion coefficient than gold for solder, or a metal whose diffusion coefficient is lower than the rate at which the solder diffuses into the solder. A larger metal is coated by vapor deposition or sputtering, and then the exposed gold paste layer is plated with a metal whose diffusion coefficient is smaller than that of gold for solder, and then this plated part and the insulating paste layer are soldered. A method for manufacturing a thick film circuit board, characterized in that the vapor deposited or sputtered coating is removed by etching except for the portion where the coating is applied. 3. The circuit board according to claim 2, wherein the step of forming a film by vapor deposition or sputtering is performed after forming an easily oxidizable metal film having a strong bonding force with oxygen on the circuit board in advance. Manufacturing method.
JP53120744A 1978-09-30 1978-09-30 Thick film circuit board and its manufacturing method Expired JPS594876B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP53120744A JPS594876B2 (en) 1978-09-30 1978-09-30 Thick film circuit board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53120744A JPS594876B2 (en) 1978-09-30 1978-09-30 Thick film circuit board and its manufacturing method

Publications (2)

Publication Number Publication Date
JPS5546575A JPS5546575A (en) 1980-04-01
JPS594876B2 true JPS594876B2 (en) 1984-02-01

Family

ID=14793901

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53120744A Expired JPS594876B2 (en) 1978-09-30 1978-09-30 Thick film circuit board and its manufacturing method

Country Status (1)

Country Link
JP (1) JPS594876B2 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5174278A (en) * 1974-12-23 1976-06-28 Marukon Denshi Kk DENSHIKAIROYODOTAINOSEIZOHOHO

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5174278A (en) * 1974-12-23 1976-06-28 Marukon Denshi Kk DENSHIKAIROYODOTAINOSEIZOHOHO

Also Published As

Publication number Publication date
JPS5546575A (en) 1980-04-01

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