JPS602709B2 - Data processing system with building block structure - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing system having a building block architecture, particularly, for example, a main memory unit, a central processing unit, and a channel.

By combining basic structural units consisting of channel units such as processors and control devices into a building block structure, data processing systems of any size can be constructed using a relatively small number of signal lines. It concerns a data processing system with a built-in building block structure. Generally speaking, one way to increase the processing power of a system is to use a so-called multiprocessor. However, as the number of central processing units increases, the number of signal lines becomes enormous. It is also desirable to adopt a configuration that allows the multiprocessor system as described above to be divided into smaller systems of arbitrary scale. The present invention aims to solve the above-mentioned problems, and the data processing system having the building block structure of the present invention is a data processing system having a main memory unit, a central processing unit, and a channel. or a main storage unit and a central processing unit, or a main storage unit and a channel unit, or a main storage unit and a central processing unit and a channel unit.
The unit has a plurality of basic structural units that are connected to the control device by internal wiring to form a group, and an input direction interface that connects the basic structural units and connects the basic structural units. Provides an output direction interface and an interface between control devices,
A building block structure is formed in which the above basic structural units are combined to form a system, and communication between units belonging to one basic structural unit and units belonging to other basic structural units is carried out via the above-mentioned inter-control device interface. The interface is characterized in that it supplies at least general-purpose data bus information and a data identification code indicating the type of information carried on the general-purpose data bus.

This will be explained below with reference to the drawings. Figure 1 shows an example of the configuration of a multiprocessor system in which four central processing units, four channel processors, and four main memory devices are connected in a complete octopus-like connection system. 3 and 3 respectively show the configuration of an embodiment of the data processing system of the present invention, FIGS. 4A, B, C, and D each show the configuration of an embodiment of the basic structural unit according to the present invention, and FIG. FIG. 6 is an explanatory diagram illustrating the interface between control devices referred to as the control device interface, and FIG.
Figures A to F are explanatory diagrams illustrating information transmitted via the general-purpose data bus, respectively, and Figure 8 is an operation used for the memory request information shown in Figure 7A.

An explanatory diagram for explaining the code, FIG. 9 is an example configuration of the control device and main storage unit of the present invention.
, C respectively show the configuration of another embodiment of the multiprocessor system used in the present invention. In Figure 1, 1-
0 None, and 1-3 are the main storage device or main storage unit, respectively. 2-0 None, and 2-3 are the central processing unit or central processing unit unit, respectively. 3-Q to 3-3 are the channels, respectively.

processor or channel. processor. represents the unit. When a system consisting of four main storage devices 1, central processing units 2, and channel processors 3 is connected in a complete octopus connection system, the number of required signal lines is as follows.

That is, W 200 [books] x 16 = 3200 [books] between the central processing unit and the main memory; 20 [books] between the 'B' channel processor and the main memory.
0 [books] x 16: 3200 [books]} Between central processing units 100 [books] x 6 = 600 [books] ■ Between central processing units and channel processors・1
00 [wires] x 16 = 1600 [wires] A total of 8,600 signal wires are required.

In the case of this configuration, ``It is relatively easy to divide the system, but there is a drawback that flexibility is poor when setting up a larger system.In order to solve this point, in the case of the present invention, By combining basic structural units as shown in Figure 2 or Figure 3, it is possible to build up a system of any size. correspond to FIG. 1, respectively, 4-0 to 4-3 are control devices, and 5-0 and 5-3 respectively
are each a service processor, 6 is a supervisor console, 7-01, 7-02, 7-03, 7-12, 7
-13 and 7-23 represent inter-control device interfaces, respectively. Also, BFO or BF3 are respectively buffers.
represents memory. In the case of the present invention, the basic structural unit (
(described later with reference to FIG. 4) constitutes a multiprocessor system.

Interfaces 7101 to 7123 are also provided between the control devices 4 to connect the basic structural units. When the central processing unit 2-0 belonging to one basic structural unit accesses the main storage unit 1-2 belonging to another basic structural unit, the central processing unit 2-0' or the main memory Equipment unit 1-
2 is specified and an access request is issued to the control Hishitaka 4-0. Accordingly, the access is performed via the control device 4-Q, the interface 7-02, and the control device 4-2. Moreover, the central processing unit units 2-0 belonging to one basic configuration unit have the same basic configuration. Needless to say, access to the main storage unit 1-0 belonging to the unit is also performed via the control device 4-0. Note that an arbitrary system configuration can be configured via the service processor 5 according to instructions from the supervisor console 6 shown in the figure. The case shown in FIG. 2 represents a system of the same scale as that in FIG. 1, but the number of required signal lines is as follows.

i.e. 'E' 200 [books] x 4 = 800 [books] between the central processing unit and the control unit; 'F' 200 [books] between the channel processor and the control unit.
[Books] x 4 = 800 [Books] ■ Between control devices (100-100) [Books] x 6: 1200 [Books] total 1
Minejin's 2800 signal lines are sufficient.

This is for example the connection between the central processing unit CPU 2-0 and the CPU 2-3 without the CPU 2-1 in the configuration shown in FIG. There is no connection between the central processing unit CPU2-0 and the channel processor 3-1.
-3, etc., in the configuration shown in Figure 2,
This may be because the connection lines between the control devices are used. Furthermore, when dividing the system, the supervisor console 6 can be used to freely divide the system into basic structural units. If the system scale is to be further increased, a so-called building block method can be used by adding a control device boat (described later with reference to FIG. 9) in each control device 4. becomes possible. The basic structural units referred to in the present invention are, as shown in FIGS. 4A to 4D, a main storage unit 1, a central processing unit 2, and a channel processor unit 3.
and a control device 4, 'b - a main storage unit 1, a channel processor unit 3 and a control device 4.
{c} one consisting of a main storage unit 1, a central processing unit 2 and a control device 4, {d}
Either one consisting of the main storage unit 1 and the control device 4 can be used.

Note that the reference numerals in the figure correspond to those in FIG. 2 or 3.
FIG. 5 is an explanatory diagram for explaining the inter-control device interface used in the present invention, where 4-i and 4-j are control devices, 7-ii is the inter-control device interface, and 8-ii is the control device 7-i. 9-ii is the input interface seen from the control device 7-i, 10 is the tag line,
11 represents a general-purpose data bus, and 12 represents a control line.

Note that the control line 12 can be provided as required. 6th below
Information transmission by the evening line and the general-purpose bus will be explained with reference to FIGS. 8 through 8.

A "data identification code indicating the type of information carried on the general-purpose data bus 11" is transmitted by the tag line 10, and its bit configuration is shown in FIG. The bus code 13 is composed of, for example, 3 bits, and includes, for example, a pattern "
001" to indicate a memory request.

The source code 14 is composed of 4 bits in order to represent the source, for example in the configuration shown in FIG.
0010'' is given. Note that "**" in the figure can be considered to be given the control device machine number of the sender. The destination code 15 is similarly composed of 4 bits to represent the destination, for example, the main storage unit 1.
-3 is the destination, the pattern "1101" is given. Note that "**" in the figure can be considered to be the counterfeit control equipment number of the destination. Various data shown in FIG. 7 are transmitted to the general-purpose data bus 11.

7A represents the case of memory request information, FIG. 7B represents the case of store data, FIG. 7C represents the case of fetch data, and FIG. 7D represents the case of input/output instructions. Figure 7E shows the case of channel
Figure 7F shows the case of mask loading.
This shows the case of Mask J Store.

FIG. 8 shows the pattern of the operation code (OPCODE) written in the memory request information shown in FIG. 7A.

For example, if a pattern "1010" is given to the code, it instructs a block fetch with key information omitted. Also, when the pattern "0000" is given, the buffer of the other party's central processing unit. Indicates that the specified block of memory is to be invalidated. In addition, as shown in FIG. 2, the central processing unit is a buffer. If memory BF is provided, all L memory fetches can be considered to be block fetches. FIG. 9 shows the configuration of an embodiment of the control device and main storage unit of the present invention.

Codes in the diagram: 1-072-0, 3-Q, 4-0 None, 4
13, 5-0, 7-01 none, and 7-03 correspond to FIG. 2, respectively, and 16 is memo IJ. Access control unit (MAC
), 17 is priority processing and bus. pin selection circuit, 1
8 is a bus out control circuit, 19 is a local central processing unit unit port, and 20' is a local channel. Reference numerals 21 to 23 represent processor unit ports, respectively, a pair of controller ports, 24 a memory refresh control section, and 25 a clock control section. For example, when the central processing unit 2-10 shown in FIG. 2 makes a full store access request to the main storage unit 1-3, the process is as follows.

'1} The central processing unit 210 writes the pattern '00' on the tag line as a bus code as shown in Figure 6.
1” as the source code, pattern “0010” as the destination code, and pattern n10U as the destination code.
give.

Then, add the pattern "0110" to the OP code on the general-purpose data bus as shown in Figures 7A and 8.
Provide address information to access the ESS area. Each of these pieces of information is then led to the local central processing counterfeit unit boat 19 in the control counterfeiter 4-01. '21 In the control device 410, the circuit 17 performs priority processing and determines from which port the input is received and where it should be sent.

In this case, since the information should be sent to the control device 4-3, the circuit 17 sends the information to the bus-out control circuit 1.
8, and circuit 18 sends it out via boat 23 as tag out and data out. {31 Control device 4
-3 also has the same configuration as that in FIG. 9, and the control device 4-3 receives the tag out and data out from the control device 410.

A circuit 17 similar to that shown in FIG.
is received. '4' In this case, since the request is for access to the main storage unit 1-3 belonging to the self, the memory access control unit 16, which is the same as that shown in FIG. 9, performs access processing to the main storage unit 1-3. to go into.

{5' In the above example, central processing unit unit 1-Q'
Well, since the store data is then sent onto the general-purpose data bus, the full data is sent to the desired address location in the control unit 4-3.

Store. Note that the priority order in the interface between control devices is given as follows.

That is, in order of priority, [1st] fetch data, [2nd] store data, and [3rd] memory. address or invalidation address, [4
5th place] Channel mask store ``[5th place] Input/output instruction or channel mask. It is considered a load. Fetch data is given the highest order. This is due to the fact that it cannot be kept waiting because it is transferred four times.

In the second and third place groups, the signals may be sent from both the central processing unit and the channel processor unit, respectively, but in this case, the central processing unit has priority.

In the case of a full store, it is necessary to transfer the store data following the transfer of the address information as described above, and to make this transfer possible, the address information is transferred while checking the "transfer notice" of the fetch data. A priority process is performed to accept the information. On the other hand, in the case of so-called partial write, or partial store, address information is accepted while confirming the "transfer notice" of fetch data so that the store data can be transferred within four cycles following the transfer of address information. Priority processing is performed Z. In the above explanation, it is assumed that there are direct interfaces between the control devices of each basic structural unit, but in the case of the present invention, a method of communicating via the control devices of other basic structural units is adopted. be able to.

FIGS. 10A to 10C show the manner of coupling in that case. In the case of Fig. 10A, when communicating from a control device assigned a machine number "000" to a control device assigned a machine number "011," a control diamond assigned a machine number n00 is used. Via In the case of FIG. 10B, it is possible to communicate with the target control device via a maximum of two control devices. Also the first
In the case of Figure 0C, it is possible to communicate with the target control device via a maximum of three control devices. As explained above, according to the present invention, basic structural units can be adjusted according to the system scale, and the system can also be easily operated in divided form as necessary.

It also has the advantage that the number of signal lines does not increase in proportion to the system scale.

[Brief explanation of the drawing]

Figure 1 shows an example of the configuration of a multiprocessor system in which four central processing units, four channel processors, and four main memory devices are combined in a complete octopus connection system. 3 and 3 respectively show the configuration of an embodiment of the data processing system of the present invention, FIGS. 4A, B, C, and D each show the configuration of an embodiment of the basic structural unit according to the present invention, and FIG. FIG. 6 is an explanatory diagram illustrating the information supplied via the tag line of the interface, and FIGS. 7 A to F are general-purpose data and
FIG. 8 is an explanatory diagram explaining the information transmitted via the bus. FIG. 8 is an explanatory diagram explaining the operation code used for the memory request information shown in FIG. 7A. FIG. 9 is an explanatory diagram explaining the control bag of the present invention. FIGS. 10A, 10B and 10C each show another embodiment of the multiprocessor system used in the present invention. In the figure, 1 is a main storage unit, 2 is a central processing unit, 3 is a channel unit, 4 is a control board, 5 is a service processor, 6 is a supervisor console,
7 is an interface between control devices, 10' is a tag line, 11
16 is a memory access control unit; 17 is a priority processing and bus iso selection circuit; 18 is a general-purpose data bus;
19 represents a bus out control circuit, 19 represents a local central processing unit unit port, 20 represents a local channel unit port, and 21 to 23 represent a control unit 0 counterfeit board, respectively. Game red game Z evil na 3 legs completed 4 evil S legs bu 6 female completed V evil ya. 8 legs na 0th place O completed q marrow

Claims (1)

[Scope of Claims] 1. In a data processing system having a main storage device, a central processing unit, and a channel, a main storage device unit, or a main storage device unit and a central processing device unit, or a main storage device unit and a channel unit, Alternatively, a main storage unit, a central processing unit, and a channel unit are connected to the control device by internal wiring to create a plurality of basic structural units constituting a group, and when connecting the basic structural units, An inter-control device interface consisting of an input direction interface and an output direction interface that connects the basic structural units is provided, and a building block structure is created in which the system is configured by combining the above basic structural units, and one basic structural unit is created. Communication between the units belonging to the unit and the units belonging to the other basic structural units is carried out via the inter-control device interface, and the interface communicates at least the general-purpose data bus information and the information on the general-purpose data bus. A data processing system having a building block structure, characterized in that a data identification code indicating the type of data is supplied. 2. A data processing system having a building block structure as claimed in claim 1, wherein the plurality of basic structural units are directly coupled to each other by an interface between control devices. 3. A data processing system having a building block structure according to claim 1, wherein said one basic structural unit is connected to a third basic structural unit via another basic structural unit. 4. The inter-control device interface has a building block structure according to any one of claims 1 to 3, which includes at least a general-purpose data bus section, a tag section, and an interface control line. data processing system. 5 The tag section is supplied with at least a code that identifies the type of information on the general-purpose data bus, a source code that identifies the source device, and a destination code that identifies the destination device. A data processing system having a building block structure according to claim 4. 6. The control device comprises at least a local central processing unit unit port, a local channel unit port, and a plurality of control device ports for other control devices. A data processing system having a building block structure according to any one of paragraphs. 7. The control device according to claim 6, wherein the control device includes at least a bus-in selection circuit section and a bus-out control circuit section, and is configured to control communications performed via each of the ports. A data processing system with a building block structure.