JPS60263578A - Picture signal correcting method - Google Patents

Abstract

PURPOSE:To correct the edge part of a picture signal to obtain a sharpened and smoothened picture by leading a correction value SK to an adder/subtracter that can change to addition or subtraction mode and making addition or subtraction to picture information amm of central picture element of a window. CONSTITUTION:A value obtained by multiplying address value of a table random access memory RAM21 that can be preset by a linear or non-linear correction coefficient K is stored in each address of the table RAM21. When the correction S is supplied as an address signal of the table RAM21, it is converted to a correction coefficient SK by multiplying the correction S by correction coefficient K. This correction coefficient SK is led to an adder/subtracter 23 that can be changed to addition mode or subtraction mode, and addition or subtraction is made to picture element information amm of a picture element at central position of the window, and a picture for which outline is corrected optionally is obtained. In such a case, sharpening or smoothing can be changed by a command from external process. Sharpening can be made by addition, and smoothing can be made by subtraction.

Description

[Detailed Description of the Invention] (Industrial Application Field) This invention is for correcting images by sharpening or smoothing recorded images in image scanning recording devices such as printing plate-making scanners and facsimiles. The present invention relates to an image signal correction method.

(Prior Art) First, an example of a conventional image scanning and recording apparatus to which the present invention can be applied will be briefly described with reference to FIG.

FIG. 6 shows the configuration of the original image reading system and recording system of this image scanning and recording apparatus.

In this figure, 81 is an Ar laser light source for both recording and reading, which emits a randomly polarized light beam. The light beam from this laser light source 81 is sent to the beam splitter 3z.
The recording beam B1 is partially separated into an S-polarized recording beam Bl and a p-polarized reading beam B2, and then the recording beam B1 is passed through an optical modulator 88, and then combined with the reading beam B2 by a half mirror 84 to generate a galvano-mirror, which is a scanning optical system. -85, the galvanometer mirror 85 converts the light into one-dimensional scanning light, and the beam is made incident on the next light beam splitting system 86. Here, the recording beam B1 is again divided into the recording beam B1 and the reading beam B2, and the recording beam B1 is transmitted to the recording device 87.
The information is sent to the recording material and recorded on the recording material.

On the other hand, the reading beam B2 is directed toward the original 88 and acts as a scanning beam to scan the surface of the original 88.

This scanning method is referred to as the main scanning direction.

The original 88 is conveyed by an appropriate feeding means in the direction indicated by the arrow perpendicular to the main scanning direction. The direction in which this document is conveyed is defined as the sub-scanning direction.

Therefore, the scanning beam scans the original image of the document 88 two-dimensionally in the main and sub-scanning directions. An image signal is obtained by a light receiving system including a fiber 89 and a photoelectric conversion element 40, amplified by an amplifier 41, and supplied to a control circuit 50.

On the other hand, the beam splitting system 86 takes out a part of the reading beam B11 and sends it to the grating 42, and the light that has passed through the grating 42 is converted into an electrical signal by the photoelectric converter 48, and further amplified by the amplifier 44 to generate the original document. The configuration is such that a grating signal synchronized with scanning is extracted and this grating signal is supplied to the I10 interface 51Fc in the control circuit 50.

The I10 interface 51 generates a clock signal based on the grid signal, and supplies this clock signal to the drive circuit 45 of the galvanometer mirror 85, and the first signal processing circuit 52 in the control circuit 50 and the line memory device 58.
, a second signal processing circuit 54 and a halftone image forming device 55. Note that the interface 51 and each of these circuits 5
1 to 55 are connected to the central processing unit 57Vc via the pass line 56.
The central processing unit 57 is connected to the central processing unit 57, and each village is controlled by commands from the central processing unit 57.

The image signal supplied to the control circuit 50 is stored in the line memory device 53 after being subjected to A/D conversion, gradation conversion, and shading correction in the second signal processing cycle M5z. The image signal read from the line memory device 58 is corrected for image sharpness in the second signal processing circuit 54 using a method described later, and then led to the halftone image forming device 55 to form a halftone image signal. Then, this halftone image signal is supplied to the optical modulator driver 46. In response to this halftone image signal, a modulation signal is applied from the optical modulator driver 46 to the optical modulator 88 to modulate the recording beam B1 from the laser light source 81, thereby transmitting image information whose sharpness has been corrected to the recording device 87. can be recorded on a recording material.

By the way, the sharpness correction method performed in such an image scanning recording device is performed by the line memory device 5B and the second signal processing circuit 54, and the sharpness correction method is performed by the line memory device 5B and the second signal processing circuit 54. A pixel matrix area of predetermined n rows and n columns centered on a pixel (hereinafter referred to as
It's called "Wind". ), and set the correction amount S for the pixel information at the center position within this window, for example, S =
n amm - (all + alJ - ten aln
+ agl +-・+ ann) (11, however, m =
, (n+1)/2 amm': Pixel information of the center pixel all to anne Pixel information of each pixel in the window 3 Calculated using the following formula.

In the calculation, all of the image information all to ann of nXn pixels within the window is once stored in the line memory device 5.
These image information are stored in the line memory in B) and then sequentially read out, first calculating the amount of correction S by formula (1) (%), and then calculating the correction amount S by computer processing based on formula (1). First, by this correction 23, the center pixel signal of the original image is corrected.

(Problem to be Solved by the Invention) However, as is well known, image signals obtained by two-dimensionally scanning a document are arranged in chronological order. Until sequential writing is completed to each corresponding line memory for all lines of
n + alJl +-+ ann) is not possible. Moreover, it is not possible to read from line memo 1 at the same time as writing to line memo 1. Therefore, unlike the conventional method described above, image information of all pixels within the window cannot be read from line memo 1. The method of performing the arithmetic processing of equation (1) after writing into the image has the disadvantage that the arithmetic processing takes a long time and high-speed image processing cannot be achieved.

(Means for Solving the Problems) This invention provides an image signal obtained by scanning an original image.
A window of nXn pixel matrix (where n is an odd number) is set, and a correction amount S for pixel information amm at the center position of the window is calculated using a predetermined calculation formula based on all pixel information in the window, and the correction amount In the image signal correction method in which the image information amin of the center position of the window is corrected according to The value obtained by multiplying by the correction coefficient k is stored in each address of the table random access memory, and the correction amount S is supplied as an address signal of the table random access memory. , a correction value Sk obtained by multiplying the correction amount by the correction coefficient k
K conversion is performed, and this correction value Sk is introduced into an adder/subtractor that can be switched to addition or subtraction mode, and is added or subtracted from the pixel information amm of the pixel at the center position of the window, thereby adjusting the edge portion of the image signal. It is characterized by sharpening or smoothing.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 (Al is a block diagram for explaining the present invention in detail, and corresponds to the line memory device 5B and the second signal processing circuit 54 in the image scanning and recording apparatus of FIG. 6).

Now, a case will be described in which a window consisting of a pixel matrix of n rows and n columns having a pixel to be corrected at its center is set for two-dimensionally arranged image signals. In this case, n is an odd number, the column direction corresponds to the main scanning direction and is the line direction, and the row direction corresponds to the sub-scanning direction and corresponds to the number of lines.

1 is a data signal input terminal, and the original 37 is connected to this terminal 1.
A for the input direct image signal obtained by two-dimensional scanning of an image such as
A signal obtained by performing /D conversion, gradation conversion, and shading correction is supplied.

2a to 2p are P line memory devices each consisting of a line memory 8 and a multiplexer 4, and the number P is set to be one more than the maximum number N of lines in the maximum window size to be set. be.

Reference numeral 5 denotes a control section which is controlled by a clock signal generated based on the grid signal, and controls the line memory device 2a=2p by receiving various write/read selection signals, write signals, read signals, etc. from the control section 5. This is done using the control signal.

This control signal allows P (P>n, n is an odd number) line memory devices 2 a = 2. One of p is cyclically used for sequential writing and all the rest are used for reading.

Therefore, the number n of line memory devices corresponding to the number n of lines in the window size to be set, including the line memory device to which writing has been completed immediately before the line memory device being written to, is counted in the reverse order of the writing order. If the read pixel information of the device is led to the adder sequentially and simultaneously, the writing and reading processes of the line memory device can be performed simultaneously in parallel, making it possible to perform these processes in real time. Become.

6a to 6p selectively guide the readout pixel information of these line memory devices 2a to 2p to the adder 7 in accordance with the number n of lines in a desired window size. P gate circuits.

That is, among these gate circuits 6a to 6p, data is written in the reverse order of the writing order, starting from the line memory device for which writing was completed immediately before the line memory device currently being written, corresponding to the number of lines nK of the window size to be set. The n gate circuits that lead the read pixel information of the n line memory devices up to the line memory device written n times before to the adder 7 are selectively turned on all at once. The gate circuit is controlled by control number i from the control section 5.

In this way, pixel information from the selected n line memory devices is stored in the nxn size window set by the selection of the gate circuits 6a to 6p as described above.
Pixel information is added by an adder 4 for each piece of pixel information arranged in the column direction (sub-scanning direction) of the pixel matrix, and this addition is performed by sequentially calculating n for the pixel columns in the row direction (main-scanning direction).
Let's go around.

FIG. 1(B) shows a write line selection signal for selecting a write line memory, a gate signal for selectively turning on gate circuits 6a to 6p all at once, and a line memory output corresponding to the center row of the window. Control for obtaining a center row selection signal for controlling the multiplexer 14 to selectively retrieve, and a write address signal and a read address signal for controlling each multiplexer No. 1 in each line memory device 2aS-2plC. FIG. 2 is a block diagram showing an example of the configuration of main parts in the section 5. FIG.

In the same figure, z4 is a P-adic, for example, a decimal-adic line counter that counts line block pulses, and every time one line's worth of image signals is written cyclically and sequentially into the line memory device [2a=2p, +1 Or generate a count value that advances by 11 steps. By adding this counted value to the first decoder 25, one of the sequential line memory devices 2 a = 2 p is sequentially and cyclically stored corresponding to the counted value, as illustrated in Table 1 below. A write line selection signal is obtained to select the write memory.

At the same time, the count value of the line counter 24 is added to the second decoder 26 together with the window size designation signal, thereby corresponding to the window size of the designated nxn pixels, as illustrated in Tables 2 to 5 below. do n
gate signals for selectively and simultaneously conducting the gate circuits according to the count value; and the specified window size in the output of each line memory device guided to the gate circuits made conductive by these gate signals. A center row selection signal for extracting pixel information of the center row is obtained.

Note that 27 is a read address. A counter 28 is a write address counter, which uses the read clock signal and the write clock signal to increase the output address every time data reading of 1ulj pixels is completed or data writing of 1 pixel is completed.
It is configured to output a read address and a write address by setting it to 1 or -1, and is reset to the initial value each time one line of reading ends and each time writing ends.

The read address signal and the write address signal from the read address counter 27 and the write address counter 28 are commonly supplied to each memory device 2a-2p, and only the line memory device selected by the write line selection signal receives its write address. The input image signal is stored using the signal, and the stored values of the remaining unselected line memory devices are read out using the read address signal.

Further, as shown in FIG. 1 (At, dividers 8a to 8p are inserted between the input side of the adder 7 and the output side of each line memory device 2a to 2p, and the input side to the adder 7 is By dividing the digitized image information by an appropriate divisor, the lower bits of the digitized signal representing the image information are removed, thereby preventing fluctuations in the lower bits due to the influence of noise from affecting the added value. ing.

Addition iW? The sum value V of each determination of the image information of n pixels lined up in a row in the sub-scanning direction within the window added by
is a P-stage register provided corresponding to the number of pixels in the main scanning direction of the window, that is, in this embodiment, the number of pixels N in the main scanning direction in the maximum window is set to 11, and P=11.
The output of the adder 7 is guided to a first shift register 9 consisting of +l la stages v1 to V12 and sequentially stored therein.

Numerals 10a to 10d are multiplexers for selecting the (n+1)th stage register determined by the size of the nXn pixel matrix of the window to be set and taking out the output. In this example, these multiples are
By selectively operating a to lOd from the outside, 5
x5.7 x 7.9 It is. In this example, four multiplexers are provided, but more may be provided depending on the size of the window. The stored value v1 taken out via one of the multiplexers 10a=10d in connection with the setting of the window is supplied to the subtractor 11.

On the other hand, the latest stored value v1 stored in the first stage register Vl of this first register 9 is supplied to the subtracter 11, and here the (n+1)th stage stored value v1 is subtracted from this stored value v1. Then, the subtraction value V is calculated.

By inputting this subtraction value V to an adder and adding it, it is possible to obtain a cumulative addition value obtained by adding all lNl elementary information within a window set to an arbitrary desired size in real time. That is, the output V of this subtracter 11 is added to 612
K, the latch value Σ corresponding to the previous cumulative addition value latched by the latch circuit '18 is returned and supplied to the previous stage addition base lz, and the subtracted value V and its latch value Σ are combined in this adder 12. By adding , the sum of all pixel information within the window can be found.

This added value is then latched as a new Σ in the latch circuit 1B.

On the other hand, the multiplexer 14 is controlled by a control signal from the control unit 5 to transfer the image information amm of the pixel at the center position of the center line within the window in the readout signal of each line memory device 2a to 2p to the line of the window. The pixel information is extracted sequentially as the pixel information moves in the direction, and is inserted into a circuit that adds a correction value obtained using the extracted pixel information to an adder/subtractor in at least (P/20M) stages (M is the correction value obtained using the extracted pixel information). For example, in this embodiment, the shift register 15 consists of nine stages of registers M1 to M9.
supply to.

Numerals 16a to 18d are multiplexers that can be selectively operated by commands from an external processor according to the size of the window to be set, and (n+1)/2 of the shift register 15.
In this example, the output of the registers in each stage from the 8th stage onward is 5X5, 7X? , 9×9 window settings, and are selected and taken out from each of the registers M8 to M6. The image information amm extracted in this way is information on the center pixel of the window, and when calculating the correction amount S of the above-mentioned equation (1) using the image information amm of the center pixel, the pixels within the window Considering that the number is nXn, in the multiplier 17 this image information amm K n
” and sends n2x amm to the latch circuit 18.

Next, the signals Σ and n2x amm of the latch circuit 1B and this latch circuit 18 described above are added in addition 519 (
In reality, the calculation of n2x amm-Σ is required) Correction amount S
get.

This correction amount S can be preset via a latch circuit 20 in a table random access memory (hereinafter referred to as rRAM).
It's called J. )21. The table RAM 21 is
As is well known, an input signal is converted into an address signal, and the input signal is converted into a value corresponding to the address and output. In other words, for the correction amount SIC obtained by applying the pressure as described above, the stored value of the address for the correction lid s is calculated in a manner that corresponds to the value of the correction amount S, is linear or nonlinear, and is influenced by the division described above. Access l- is made so that the correction coefficient k that takes into account the compensation of is converted into a correction value Sk obtained by multiplying the correction amount S and output.

Therefore, the correction coefficients set corresponding to each of the input correction amounts S can be preset by a processor (not shown). Therefore, when the correction amount S is input to this table RAM 21, it is possible to output in real time a correction value Sk that changes with the desired characteristics corresponding to the correction amount S and can compensate for the influence of division. The correction value Sk can be calculated at high speed.

The correction value Sk from the table RAM 21 is supplied via a latch circuit z2 to an adder/subtractor 28 for sharpening or smoothing the edge portions of the image.

On the other hand, for this addition/subtraction 1T728, center image information amm is selected from the stage whose timing coincides with the correction value Sk obtained as described above in the adder/subtractor 28 in the sixth to ninth stages M6 to M9 of the shift register 15. supply. In this example, the multiplication ill? Pixel information a at the window center position obtained from
When mm is used to calculate the correction value and reaches the adder/subtractor 28, it is latched by eight latch circuits of 18, 20, and 2z. Therefore, the number of corrected values guided to the adder/subtractor is equal to the number of latch circuit stages. It is necessary to delay the pixel information amm. Therefore, the second shift register 15 is set to (
P/2+8) stages, for example, 5 to 9 stages as shown in the figure.

Then, another multiplexer 20 is connected to the (n+1)/2 + 8th and subsequent registers 146 to M9 corresponding to the nXn multiplication matrix of the arbitrarily set window size.
a=20d, and the output of a desired register stage in which image information of the center pixel within the window is stored among these registers M6 to M9 is selectively taken out by a command from a processor (not shown). Configure.

The central plane k 'It# information a m taken out in this way
, add or subtract m,! :Supplied to poetry za and the above-mentioned correction (gs
By performing addition and subtraction with k, an image signal whose contour of the image is arbitrarily corrected is obtained. In this case, sharpening or smoothing can be switched by a command from an external processor, and sharpening can be performed by adding, and smoothing can be performed by subtracting.

Next, the operation of image signal correction in the above embodiment will be explained in detail with reference to FIGS. 2 to 5. The IE2 diagram is an explanatory diagram for explaining a specific example where the window is fixedly set to a 5x5 pixel matrix. The pixel arrangement within the window in this case is shown in FIG.

In this embodiment, for convenience of explanation, lines from the line memory device during writing are omitted, and the second and second shift registers 9 and 9 are arranged in correspondence with the size of the pixel matrix of the set window. The number of stages in FIG. 15 is increased to six, and the window switching multiplexer is omitted, and the other configurations are the same as in the case of FIG. 1, so a detailed explanation thereof will be omitted.

In this example, 5 lines of signals are aS b, c, d.

The central image information is shown as C in the third stage, and is connected so as to be input to the second shift register 15.

FIG. 3 shows the holding state of the stored value v1 in each stage of the first shift register 9, the holding state of the center image information C in each stage of the shift register 15, and the latch circuit for these stored values v1 and center image information cK. FIG. 18 is an operation explanatory diagram showing the contents of the latch value Σ in step 18 in a table.

As shown in FIG. 8, the first register VIK of the first shift register 9 is the first register of the second shift register 15 when the first addition value from the adder 7 is stored as the stored value v1. Image information C1 of the third line is input to M1. next.

At the same time that the second addition value is recorded in the register v1 as the storage value v2, the first storage value v1 is shifted to the next register (2). Similarly, the second shift register 15
The pupil value C1 recorded in the first register MlO is also the same as the next register M
2, the next center image information c2 of the third line is newly stored in the Ml register, and the latch value Σ is v
It becomes l.

When the 1st F is made the same stock and stored sequentially, and the 6th addition value is obtained as the stored value v6, both shift registers 9 and 1
All of the 5 registers will store memory values,
The latch value Σ also shows the correct value and reaches a steady state, with only 5
It can be seen that the correction amount S can be obtained in one calculation time.

Furthermore, the correction amount S is calculated from the table R as described above.
Since it is immediately converted into a linear or non-linear correction value Sk by AM21, the image can be processed to achieve the desired sharpness.
The calculation speed for emphasizing or smoothing edge portions can be significantly increased compared to conventional image signal correction devices of this type.

For example, when the image information of the pixels in the window for the original image is arranged as shown in FIG. 4, the image information of the pixel at the center position is a88. In addition d7, addition (i (Q 11 +
621 + all + a41 + a51) or (aiz + az2+ a82 + a42 + a
5g), the added value V is sequentially sent to the first shift register 9.

Therefore, the correction value Sk in this case is Sk = k(25a8B - (all + a12 +
-・+a15+a21+...+a 5 s ) )
(2)°, and the corrected image information X becomes X=a88+Sk fa), and is corrected by K as described below with reference to FIG.

FIG. 5 (Al to fE) is a waveform diagram for explaining the progress of the above-mentioned correction.

FIG. 5 (Al indicates an image signal amm having an edge portion to be corrected, FIG. 5 fB) shows the image signal amm
Corrected image ik (in this case, k
is a number less than 1). When this correction value Sk is added with positive polarity to amm shown in FIG.

In addition, the image signal amm of Fig. 5 fAl is shown in Fig. 5 (0
) when the correction value Sk shown in Figure 5 (E
As shown in FIG. 1, the waveform has smoothed edges.

Therefore, the digitized image signal thus corrected is added to the halftone image forming device 48, which includes the D/A converter of the image scanning and recording device described with reference to FIG.

Therefore, by converting it into a halftone image signal and supplying the resulting signal to the light modulation driver 51 to modulate the six polarized lights from the recording laser 81, the recording device outputs an image corrected to the desired sharpness. It can be recorded by

In addition, the table RAM 21 K is the correction value S to be preset.
When calculating k, the correction coefficient multiplied by the correction amount SK can be easily and quickly changed by an external processor. In this case, the correction coefficient k can be selectively used to form a line or non-linearly depending on the nature of the original image.

It is clear that the present invention is not limited only to the embodiments described above.

It is also clear that the image device to which this invention can be applied is not limited to the type of device shown in FIG.

(Effect of the Invention) As is clear from the above explanation, according to the method of the present invention, the correction amount S determined by a predetermined calculation formula is stored in the table RAM as a predetermined correction corresponding to the correction amount SK. By multiplying the coefficient by this correction amount S, it is converted into a correction value Sk in real time, and this correction value Sk is supplied to an adder/subtractor whose operation mode is controlled by a processor, and this correction value Sk is set to the center of the window. Since this method corrects the image signal by performing addition and subtraction on the image information of the position, it is possible to perform calculation processing much faster than conventional methods.
By setting in advance to change with appropriate characteristics,
Not only can the image signal be corrected so that the outline of the image is emphasized or smoothed with desired characteristics, but also the image signal can be corrected within a predetermined dynamic range.

Furthermore, such high-speed processing can be easily performed using a device that is approximately the same scale as conventional devices.

Table 1 Table 2 Table 8 --- Table 4 Table 5

[Brief explanation of the drawing]

FIG. 1(A) is a block diagram for explaining one embodiment of the image signal correction method of the present invention. A block diagram showing the strategy of the configuration of the control unit, FIG. 2 is an explanatory diagram for explaining the image signal correction method when the window is set as a 5×5 pixel matrix, and FIG. 8 is used to explain the present invention. Explanatory diagram, Figure 4 is 5x
A line diagram showing the pixel arrangement within the window of a five-sided cumulative matrix, FIG. 5 is a waveform diagram for explaining the process of correction of central image information by the method of this invention, and FIG. 6 is an image to which this invention can be applied. FIG. 2 is a configuration diagram showing an example of a front-of-vehicle recording device. 1... Data signal input terminals 2a to 2p... Line memory device 8... Line memories 4, 10a to 10d, 14, 16a to 16
d-multiplexer 5...control section 6a-6p...
・Gate circuit? , 12.19... Adder 8a to 8p
...Divider 9...First shift registers 10a to 10d, 14...Multiplexer 11.
...Subtractor 18.18.20.22...Latch circuit 15...Second shift register 17...Multiplication base z1...Table RAM2B...
Addition/subtraction IS 84...Line counter 25...First decoder 26...Deni decoder z7...Read address counter 28...Write address counter. Patent applicant: Fuji Photo Film Co., Ltd. Figure 1. No. 41 Key toy name All-selected name (73) Address for writing Address for public and private sector Figure 3 Procedure amendment June 6, 1985 Commissioner of the Patent Office Mr. Manabu Shiga Manabu Shiga 1 Case Indication 1988 patent Application No. 118848 2 Name of the patent Image signal correction method 3 Person making the correction Relationship to the case Patent applicant address 210 Nakanuma, Minamiashigara City, Kanagawa Prefecture Name (520)
Fuji Photo Film Co., Ltd. Representative Minoru Onishi 4 Agent Address: 805 Ikebukuro White House Building, 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Name (8541) Patent Attorney Takashi Ogaki 5 Date of amended order Contents of the amendments in Figure 6 and 7 of the "Claims" column of the specification subject to the spontaneous 6th amendment, the Detailed Description of the Invention column, and the drawings. (1) Description, Claims The column is corrected as follows: lr2, Claim 1, The window of the nXn pixel matrix (where n is an odd number) is revised for the image signal obtained by scanning the original image, and the center of the window is revised. An image in which a correction amount S for pixel information amm at a position is calculated using a predetermined calculation formula based on all pixel information in the window, and pixel information amm at the center position of the window is corrected according to the correction amount S. In the signal correction method, by supplying the correction amount S as an address signal of the table random access memory, the correction amount S becomes a correction value Sk obtained by multiplying the correction amount by the correction coefficient k.
The edge portion of the image signal is converted to An image signal correction method characterized by sharpening or smoothing. 1 (2), page 4, line 7, "This scanning method" is corrected to 1, this scanning direction. (3), same, page 9, line 11 "in memory, for the address value of the memory" to each address of r memory, the correction 1
Correct s to 1. (4), page 9, line 12, ``the multiplied value'' is multiplied by 1, and the correction value Sk is corrected to 1. (5), same page 9, lines 12 to 13, ``The table......at each address'' is deleted. (6), page 14, lines 18 to 20 are corrected as follows. 1 and the write clock signal, the output address is increased or decreased by +1 or -1 each time one pixel's data reading is completed or one pixel's data writing is completed, and the readout address is read out at 1 (7), page 18, line 11 r18a. ~18d is”
is corrected to r16a~led as j. (8), page 18, line 16, "9x9 window" is corrected to 9x9, wind 1 of IIX 11. (9), page 25, line 20, “halftone image forming device 48
" is corrected to "halftone image forming device 55." (10), same, page 26, line 2, "Driver 51" is corrected as "driver 48j". (11), same, page 30, table 3 is corrected as follows. Kaede 8 Gakusei (12) , Figure 6 of the drawing is corrected as shown in the attached corrected drawing.

Claims (1)

[Claims] L A window of nxn pixel matrix (where n is an odd number) is set for an image signal obtained by scanning an original image, and a correction amount S is set for pixel information amm at the center position of the window. An image signal correction method in which image information anti of the center position of the window is corrected according to the correction amount S calculated using a predetermined calculation formula based on information on all pixels in the window, the image signal being presettable. In the table random access memory, a value obtained by multiplying the address value of the memory by a linear or nonlinear correction coefficient k is stored in each address of the table random access memory, and the correction amount S is applied to the table random access memory. By supplying the correction amount S as an address signal of the table random access memory, the correction value 5k obtained by multiplying the correction amount by the correction coefficient k
The edge portion of the image signal is calculated by introducing the correction value Sk into an adder/subtractor that can be switched to addition or subtraction mode and adding or subtracting it from the image information amm of the pixel at the center position of the window. An image signal correction method characterized by sharpening or smoothing.