JPS60263580A - Picture signal correcting method - Google Patents

Abstract

PURPOSE:To suppress the influence of noise included in a picture signal to be exerted on a finally corrected picture signal by dividing picture information of each picture element in a window using a proper divisor before addition of the amount of correction S. CONSTITUTION:Dividers 8a-8p are interposed between gate circuits 6a-6p and an adder 7. Digitized picture information inputted to the adder 7 is divided by a proper divisor by dividers 8a-8p. Thereby, lower rank bits of digitized signals representing the picture information are removed, and influences of fluctuation of lower rank bits due to influences of noise on the added value is prevented. When calculating the amount of correction S using picture information amm of central picture element, considering that the number of picture elements in the window is (n)X(n), information amm is multiplied by n<2> in the multiplier 17, and this n<2>Xamm is sent to a latch circuit 18. A signal SIGMA of the latch circuit 13 and n<2>Xamm of the circuit 18 are added by an adder 19 (actually, operation of n<2>Xamm-SIGMA is performed) and the amount of correction S is obtained.

Description

Detailed Description of the Invention (Industrial Application Field) This invention is applicable to printing plate making scanners, facsimile IJ
The present invention relates to an image signal correction method for correcting an image by sharpening or smoothing a recorded image in an image scanning recording apparatus such as the above.

(Prior Art) First, an example of a conventional image scanning and recording apparatus to which the present invention can be applied will be briefly described with reference to FIG.

FIG. 6 shows the configuration of an original image reading system and a recording system of this image scanning and recording apparatus.

In this figure, 31 is an Ar laser light source for both recording and reading, which emits a randomly polarized light beam. The light beam from this laser light source 31 is sent to a beam splitter 8z.
The recording beam Bl is partially separated into an S-polarized recording beam B1 and a Torr-polarized reading beam B2.The recording beam Bl is passed through an optical modulator 33, and then combined with the reading beam B2 by a half mirror 34 to generate a galvanomirror, which is a scanning optical system. 35, the galvanometer mirror 35 converts the beam into one-dimensional scanning light, and the beam is made incident on the next beam splitting system 36. Here, the recording beam B1 is again divided into the recording beam B1 and the reading beam B2, and the recording beam B1 is
The information is sent to the recording material and recorded on the recording material.

On the other hand, the reading beam B2 is directed toward the original 38 and acts as a scanning beam to scan the surface of the original 38.

This scanning method is referred to as the main scanning direction.

The document 38 is conveyed by an appropriate feeding means in the direction indicated by the arrow perpendicular to the main scanning direction. The direction in which this document is conveyed is defined as the sub-scanning direction.

Therefore, the scanning beam scans the original image of the document 38 two-dimensionally in the main and sub-scanning directions. With this scan,
An image signal is obtained by a light receiving system including an optical fiber 39 and a photoelectric conversion element 40 configured and arranged to receive reflected light or transmitted light of the scanning beam, amplified by an amplifier 41, and supplied to a control circuit 50.

On the other hand, the beam splitting system 36 extracts a part of the reading beam B2 and sends it to the grating 42. The light that has scanned the grating 42 is converted into an electrical signal by the photoelectric converter 43, and further amplified by the amplifier 44. The configuration is such that a grid signal synchronized with document scanning is extracted and this grid signal is supplied to an I10 interface 51 within the control circuit 50.

This I10 interface 51 generates a clock signal based on the grid signal, and supplies this clock signal to the drive circuit 45 of the galvanometer mirror 85, as well as the first signal processing circuit 52 in the control circuit 50 and the line memory device 53.
, a second signal processing circuit 5 and a halftone image forming device 55. Note that the interface 51 and each of these circuits 5
1 to 55 are connected to a central processing unit 57 via a pass line 56, and are configured to perform various controls based on commands from the central processing unit 57.

The image signal supplied to the control circuit 50 is subjected to A/D conversion, gradation conversion, and aging correction in the first signal processing circuit 52, and then stored in the line memory device 53. After the image signal read from the line memory device 53 is corrected for image sharpness in the second signal processing circuit 54 using a method described later, it is led to the halftone image forming device 55 to generate a halftone image signal. This halftone image signal is supplied to the optical modulator driver Φ6. In response to this halftone image signal, a modulation signal is applied from the optical modulator driver 46 to the optical modulator 83 to modulate the recording beam B1 from the laser light source 81, thereby transmitting the sharpness-corrected image information to the recording device 3. ? "Can be recorded on recording materials."

By the way, the sharpness correction method performed in such an image scanning recording device is performed by the line memory device 53 and the second signal processing circuit 54, and the sharpness correction method is performed by the line memory device 53 and the second signal processing circuit 54. A pixel matrix area of predetermined n rows and n columns centered on a pixel (hereinafter referred to as
It's called "Wind". ), and set the correction amount S for the pixel information at the center position within this window, for example, S:
= n2amm −(ali + a12 ・−・+
aln + all +=-+ ann)' (1) However, m=(n+1)/2 amm: Pixel information of the center pixel all to ann: Calculated using the formula of pixel information of each pixel within the window.

In the calculation, all of the image information all to ann of nxn pixels within the window is once stored in the line memory device 5.
After storing the image information in the line memory in B, the image information is sequentially read out to first calculate the equation (1) (0 equation %), and then calculate the correction amount S by computer processing based on the equation (1). , the center pixel signal of the original image is corrected using this correction amount S.

(Problem to be Solved by the Invention) However, as is well known, image signals obtained by two-dimensionally scanning a document are arranged in chronological order. In the case where writing is completed sequentially to each corresponding line memory for all lines, (a 11 + a12 +=・+aln,
+ a21 +°−+ ann) is impossible. Moreover, it is not possible to read from this line memory at the same time as 13 is written into the line memory, and therefore, as in the conventional method described above, the image information of all pixels within the window is written to the line memory. later (1)
In the method of performing arithmetic processing of the equation, the arithmetic processing takes a long time and high-speed image processing cannot be achieved. Errors may occur in the corrected image signal that is finally obtained due to noise or errors during A/D conversion, etc.
There was a drawback that desired image signal correction could not be achieved.

The purpose of the present invention is to eliminate the drawbacks of the above-mentioned conventional methods, and to suppress the influence of noise contained in image signals, errors generated during A/D conversion, etc. on final corrected image signals. An object of the present invention is to provide an image signal correction method.

(Means for Solving the Problems) This invention provides an image signal obtained by scanning an original image.
A window of nXn pixel matrix (where n is a count) is set, and a correction amount S for pixel information amm at the center position of the window is calculated using a predetermined calculation formula based on all pixel information within the window, and the correction amount In the image signal correction method in which image information amm at the center position of the window is corrected according to S, the correction amount S is calculated using an added value obtained by adding all pixel information within the window. In doing so, prior to the addition process, the image information of each pixel in the window is divided by an appropriate divisor, and the correction value S is divided into the correction value S by the effect of the division on the correction value S. It is characterized in that the image information amm is converted into a correction value Sk obtained by multiplying it by a correction coefficient k that also takes into consideration, and the image information amm is corrected using this correction value Sk.

(Description of Embodiments) Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1(A) is a block diagram for explaining the present invention in detail. Equivalent to.

Now, a case will be described in which a window consisting of a pixel matrix of n rows and n columns having a pixel to be corrected at its center is set for two-dimensionally arranged image signals. In this case, n is an odd number, the column direction corresponds to the main scanning direction and is the line direction, and the row direction corresponds to the sub-scanning direction and the number of lines.

■ is the data signal human world terminal, and this terminal 1 has the Muma manuscript 8
A signal obtained by performing A/D conversion, gradation conversion, and shading correction on an image signal obtained by two-dimensionally scanning an image such as No. 7 is supplied.

'2a to 2p are P line memory devices each consisting of a line memory 3 and a multiplexer 4, and the number P is set to be one more than the maximum number N of lines in the maximum window size to be set. It is.

Reference numeral 5 denotes a control unit controlled by a clock signal generated based on a grid signal, and the line memory devices 2a to 2p are controlled by a write/read selection signal, a write signal, a read signal, etc. from the control unit 5. This is done using various control signals.

This control signal causes one of the P line memory devices 2a to 2p (P''2n, n is an odd number) necessary for obtaining the desired maximum window size to be used for writing in a sequential manner in a cyclic manner. Use it for reading.

Therefore, the number n of line memory devices corresponding to the number n of lines in the window size to be set, including the line memory device to which writing has been completed immediately before the line memory device currently being written, is counted in the reverse order of the writing order. By sequentially guiding the read pixel information to the adder, the writing and reading processes of the line memory device can be performed simultaneously in parallel, making it possible to perform these processes in real time. Become.

6a to 6p selectively read the read pixel information of these line memory devices 28 to 2p to n line memory devices corresponding to the line @n in a desired window size.
These are P gate circuits for guiding the power to the adder 7. In other words, among these gate circuits 6a to 6p, in accordance with the number n of lines of the window size to be set, the line memory device in which writing has been completed immediately before the line memory device in which writing is being performed is performed in the reverse order of the writing order. In order to selectively conduct all n gate circuits leading to the adder 7, the read pixel information of the n line memory devices up to the line memory device that has been written n times before is made to conduct selectively all at once. These gate circuits are controlled by control signals from the control section 5.

In this way, the pixel information from the selected n line memory devices is stored in the window of the size set by the selection of the gate circuits 6a to 6p as described above.
The pixel information is added for each pixel information arranged in the column direction (sub-scanning direction) of the pixel matrix by addition'a 4 VC,
This addition is performed sequentially for the pixel columns in the row direction (main scanning direction) n times in total.

FIG. 1 fBl shows a write line selection signal for selecting a write line memory, a gate signal for selectively turning on the gate circuits 6a to 6p all at once, and a line memory output corresponding to the center digit of the window for selectively selecting the write line memory. The control unit 5 obtains a center row selection signal for controlling the multiplexer 14 to take out data, and a write address signal and a read address signal for controlling the multiplexers 14- in each line memory device Za to 2pK. FIG. 2 is a block diagram showing an example of the configuration of main parts within the system.

In the figure, 24 is a P-adic, e.g., 12-adic, line counter that counts line block pulses, and is given +1 or -1 every time an image signal for l life is sequentially written into the line memory devices 28 to 2p in a circular manner. Generates an incremented count value. By adding this count value to the first decoder 25,
As illustrated in Table 1 below, a write line selection signal is obtained that sequentially and cyclically selects one of the sequential line memory devices 2a to 2p as a write memory in accordance with the count value.

By adding the count value of the line counter 24 to the Kiji decoder 26 together with the window size designation signal at the same time as the switching, as illustrated in Tables 2 to 5 below, the window size of the designated nXn pixels is the gate signals for selectively and simultaneously conducting the n gate circuits corresponding to the size according to the count value, and the designation in the output of each line memory device guided to the gate circuits that are turned on by these gate signals; A center row selection signal is obtained for extracting pixel information of the center row in a window size of .

Note that 27 is a read address counter, and 28 is a write address counter, which outputs a read clock signal and a write clock signal every time one pixel's data read is completed or once.
It is configured to output the read address and write address by setting the output address to +1 or -1 each time data writing of a pixel is completed, and is reset to the initial value each time one line of reading and writing is completed. .

The read address signal and the write address signal from the read address counter 27 and the write address counter 28 are supplied to iN+ to each memory device Za to 2p, and only the line memory device selected by the write line selection signal performs the write operation. The input image signal is stored using the address signal, and the stored values of the remaining unselected line memory devices are read out using the read address signal.

In addition, in FIG. 1(A), between the input end of the adder 7 and the output side of each line memory device 2 a = 2 p,
As shown in the figure, by inserting dividers 8a to 8p and dividing the digitized image information input to the adder 7 by an appropriate divisor, the lower bits of the digitized signal representing the image information are removed. However, this prevents fluctuations in the lower bits due to the influence of noise from affecting the impact value.

A P-stage register in which the sum value V of each determination of the image information of n pixels arranged in a line in the sub-scanning direction within the window added by the adder 7 is provided in correspondence with the number of pixels in the main-scanning direction of the window. That is, in this embodiment, the number of pixels N in the main scanning direction in the maximum window is set to 11, and P=11+
1 12 stages ■First shift register 9 consisting of 1 to V12
The output of the adder 7 is led to and sequentially stored.

10a-10. d is a multiplexer for selecting the (n+1)th register determined by the size of the nXn pixel matrix of the window to be set and taking out the output. In this example, these multiplexers lO
By selectively operating a to 10d from the outside, 5
×5.7 × 7.9 It is configured to be read. Although four multiplexers are provided in this example, more may be provided depending on the size of the window. The stored value v1 taken out via any of the multiplexers 10a to 10d in connection with the setting of the window is supplied to the subtractor 11.

On the other hand, the latest stored value v1 stored in the first stage register v1 of this first register 9 is supplied to the subtracter 11, and the (n + 1)th stage stored value v1 is obtained from this stored value v1. A subtracted value V is calculated by subtracting .

By inputting this subtraction value V to an adder and adding it, it is possible to obtain a cumulative addition value obtained by adding all pixel information within a window set to an arbitrary desired size in real time.

That is, E, , IJv of this subtracter 11 is led to the adder 12, and the latch value Σ corresponding to the previous cumulative addition value latched by the latch circuit 18 is returned and supplied to the adder 12 at the previous stage. However, by adding the subtracted value V and its latch value Σ in this adder 12, the added value of all the pixel information within the window can be found.

This added value is then latched into the launch circuit 18 as a new Σ.

On the other hand, one multiplexer is controlled by a control signal from the control unit 5 to transfer image information amm of the pixel at the center position of the center line within the window in the readout signal of each line memory device 2a to 2p to the window. At least (P/2+
M) stages (M is the number of latch stages inserted in a circuit that adds a correction value obtained using extracted pixel information to an adder/subtractor as a correction value for that pixel information), for example, 9 in this embodiment.
A shift register 5 consisting of stage registers M1 to M9 is supplied.

Numerals 16a to 18d are multiplexers that can be selectively operated by commands from an external processor according to the size of the window to be set, and (n+1)/2 of the shift register 15.
In this example, the outputs of the registers in the third and subsequent stages are selected from each of registers M3 to M6 in accordance with the window settings of 5 x 5.7 x 7.9 x 9. I'll take it away. The image information amm extracted in this way is information on the center pixel of the window, and when calculating the correction amount S in equation (1) described above using the image information amm of the center pixel, it is necessary to Considering that the number of pixels is nXn, the multiplier 17 adds n2 to this image information amm.
and sends n2x amm to the latch circuit 18.

Next, the signals Σ and n2x amm of the latch circuit 13 and this latch circuit 18 described above are added together by an adder 19 (
Actually, n2x amm-Σ is calculated) Correction amount S
get.

This correction amount S can be preset via a latch circuit 20 in a table random access memory (hereinafter referred to as rRAM).
It's called J. )21. As is well known, the tables R and AM 21 convert an input signal into an address signal, convert the input signal into a value corresponding to the address, and output the converted signal. In other words, for the correction amount S obtained as described above, the stored value of the address for the correction amount S is set in a manner that corresponds to the value of the correction amount S, is linear or nonlinear, and is free from the influence of the division described above. It is preset so that the correction value Sk obtained by multiplying the correction amount S by a correction coefficient k that takes compensation into account is output.

Therefore, the correction coefficients set corresponding to each of the input correction amounts S can be preset in advance by a processor (not shown). Therefore, when the correction amount S is input to this table RAM 21, it is possible to output in real time a correction value Sk that changes with the desired characteristics corresponding to the correction amount S and can compensate for the influence of division. The value Sk can be calculated at high speed.

The correction value Sk from the table RAM'21 is supplied to an adder/subtracter 3za for sharpening or smoothing the edge portion of the image via a launch circuit z2.

On the other hand, the sixth adder/subtracter 23 of the shift register 15
-9th stage The center image information amm is selected and supplied from the stage whose timing coincides with the correction value Sk obtained by the adder/subtractor 28 in the above-described manner among the stages M6 to M9. In this embodiment, the pixel information amm at the window center position obtained from the multiplier 17 is used to calculate the correction value and is latched by three latch circuits of 18, 20, and 2z until it reaches the adder/subtractor 23. Therefore, it is necessary to delay the pixel information amm to be corrected that is led to the adder/subtractor by the number of latch circuit stages.

Therefore, the second shift register 15 is set to (P/2+
3) When folded down, it is configured into 9 VC stages as shown in the figure. Then, another multiplexer 20a is added to the (n'+1)/2 + f3rd and subsequent registers M6 to M9 corresponding to the nxn pixel matrix of the arbitrarily set window size.
20d, and the output of a desired register stage in which image information of the center pixel within the window is stored among these registers M6 to M9 is selectively taken out by a command from a processor (not shown). do.

The center/image information ainm extracted in this way is supplied to the adder/subtracter 28 and added/subtracted with the above-mentioned correction value Sk to obtain an image signal in which the outline of the image is arbitrarily corrected. In this case, sharpening or smoothing can be switched by a command from an external processor;
Smoothing can be achieved by subtraction.

Next, the operation of image signal correction in the above embodiment will be explained in detail with reference to FIGS. 2 to 5.

FIG. 742 is an explanatory diagram for explaining a specific example where the window is fixedly set to a 5×5 pixel matrix. FIG. 4 shows the pixel arrangement within the window in this case.

In this embodiment, for convenience of explanation, lines from the line memory device during writing are omitted, and the second and second shift registers 9 and 9 are arranged in correspondence with the size of the pixel matrix of the set window. The number of 150 stages is changed to 6 stages, and the window switching multiplexer is omitted, and the other configurations are the same as in the case of FIG. 1, so a detailed explanation thereof will be omitted.

In this example, 5 lines of signals are a, b, c, and d.

The central image information is shown as C in the third stage, and is connected so as to be input to the second shift register 15.

FIG. 3 shows the holding state of the stored value 1 in each stage of the first shift register 9, the holding state of the center image information C in each stage of the shift register 15, and the latches for these stored values vi and center image information cK. FIG. 3 is an operation explanatory diagram showing the contents of the latch value Σ in the circuit 13 in a table form.

As shown in FIG. 3, the first register VIVc of the first shift register 9 is an adder? When the first addition value from is stored as the storage value v1, the second shift register 15
The image information CI of the third line is input to the first register M1. Next, the second addition value is the stored value v
2 is recorded in the register Vl, and at the same time, the first stored value 1 is shifted to the next register v2. Similarly, the stored value C1 of the first register M1 of the second shift register 15 is also shifted to the next register M2, and a new Ml
The next center image information c2 of the third line is stored in the register, and the latch value Σ becomes vl.

Thereafter, the data is stored sequentially in the same manner, and when the sixth addition value is obtained as the stored value v6, one shift register 9 and 15
It can be seen that all of the registers save the stored values, the latch value Σ also shows the correct value and reaches a steady state, and the correction amount S can be obtained in only 5 calculations.

Furthermore, the correction amount S is calculated from the table R as described above.
AM 21 immediately converts it into a linear or non-linear correction value Sk, so the calculation speed for emphasizing or smoothing the edges of the image to achieve the desired sharpness is much faster than that of conventional image signal correction equipment of this type. It can be significantly faster than.

For example, when the image information of the pixels in the window for the original image is arranged as shown in FIG. 4, the image information of the pixel at the center position is a33. The adder 7 calculates the addition value (aix + az
1+ a31 + a41+a51) or (alz
+ a22 + aa2 + a42 + asz), the added value ■ is sequentially sent to the first shift register 9.

Therefore, the correction value Sk in this case is Sk = k(25a83- (all + a12
+-・+als+a21-+-・-+a55)) (2
1, and the corrected image information X becomes x=a33+sk fal , and is corrected as described below with reference to FIG.

FIG. 5 (Al to fE) is a waveform chart for explaining the course of the above-mentioned correction.

FIG. 5 (A+ indicates the image signal amm having an edge portion to be corrected, and FIG. 5(B) shows the image signal amm
A correction value Sk obtained by multiplying the correction amount SIC by a correction coefficient k (in this case, k is a number less than 1) is shown. When this correction value Sk is added with a positive polarity to amm shown in FIG. 5, a waveform with sharp edges as shown in FIG. 5(D) is obtained.

Furthermore, for the image signal amm in FIG. 5(A), FIG.
When the correction value Sk shown in FIG. 1 is added with negative polarity,
As shown in FIG. 1, the waveform has smoothed edges.

Therefore, the thus corrected digitized image signal is added to the halftone image forming unit containing the D/A converter of the image scanning recording apparatus described with reference to FIG. The resulting signal is supplied to the light modulation driver 51 to modulate the S-polarized light from the recording laser 31, thereby allowing the recording device to record an image corrected to a desired sharpness. I can do it.

Note that when calculating the correction value Sk to be preset in the table RAM 21, the correction coefficient by which the correction amount S is multiplied can be easily and quickly changed by an external processor. In this case, the correction coefficient k can be selectively used to form a line or non-linearly depending on the nature of the original image.

Note that it is clear that the present invention is not limited only to the embodiments described above.

It is also clear that the image device to which this invention can be applied is not limited to the type of device shown in FIG.

(Effects of the Invention) As is clear from the above description, according to the method of the present invention, prior to calculating the predetermined calculation formula, each value all to ann of the predetermined calculation formula is divided in advance, After removing the lower bits of the digital value of the image information of each pixel, (ait + a12 +...→-aln+a2
1 → -... 10 ann), and the resulting correction amount S is multiplied by a correction coefficient k that takes into account the divisor used in the above-mentioned division, and the influence of the division is compensated for by 1 award. , it is possible to correct the image signal by +tli using a correction value Sk having a desired characteristic for the correction amount S, so it is possible to reduce the influence of noise contained in the teifthalized image signal of the original image. .

Furthermore, such high-speed processing can be carried out on a machine that is approximately the same size as conventional equipment.

Specification - RIT document (no change in content) Table 1 Engraving of the statement (no changes to the contents) Ki 2 table Engraving of the statement (no changes to the contents) Table 3 Engraving of statement (Contents → No changes) Table 4 Engraving of the statement (no changes to the contents) Table 5

[Brief explanation of the drawing]

11pfA) is a block diagram for explaining one embodiment of the image signal correction method of the present invention, and FIG. 1(B) is a block diagram for obtaining various signals used in the embodiment of FIG. Figure 2 is an explanatory diagram illustrating the image signal correction method when the window is set as a 5 x 5 pixel matrix, Figure 8 is a block diagram showing the outline of the configuration of the control unit of the invention. An explanatory diagram for explaining, Fig. 4 is 5×
A line diagram showing the pixel arrangement within the window of a 5-pixel matrix, Fig. 5 is a waveform diagram for explaining the process of correction of the center image 1 hour report by the method of the present invention, and Fig. 6 is an image to which the present invention can be applied. FIG. 1 is a configuration diagram showing an example of a scanning recording device. 1...Data signal input terminals 2a to 2p...Line memory device 8...Line memory 4, lOa-10d, 14, 16a to 1
6d-Multiplexer 5...control section 6a-6p mountain gate circuit? , 12.19...Ka J't'a 8a ~8
p Yama division field 9...first shift registers 10a to 10d, 14...multiplexer 11...
・Subtractions 13, 18, 20, 22 ・Latch circuit 15...
・Second shift register 17...Multiplication? S21...Table RAMz3...
Addition/subtraction 24...Line counter z5...First decoder 26/Second decoder 27...Read address counter 28...Write address counter. Patent applicant Fuji Photo Film Co., Ltd. (B) Harmful address Shib exit dress Figure 3 Figure 5 (E) - Procedural amendment (method) October 5, 1980 2 Title of the invention Image signal Amendment method 3 Relationship between the person making the amendment and the case Patent applicant address 210 Nakanuma, Minamiashigara City, Kanagawa Prefecture Name (520)
Fuji Photo Film Co., Ltd. Representative Onishi Sho 4 Agent 170-(988)5563 Address 905 Ikebukuro White House Building, 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Date of 5 Amendment Order September 25, 1988 6 Amendment Detailed explanation of the invention in the subject specification Column 7 Contents of amendment Procedural amendment as per the engraving and attachment of pages 28 to 32 of the specification originally attached to the application (no change in content) 1985 6 Manabu Shiga, Director General of the Japan Patent Office, June 6th 1988 Patent Application No. 118848 2 Name of the patent Image signal correction method 3 Relationship with the person making the correction Patent applicant address 210 Nakanuma, Minamiashigara City, Kanagawa Prefecture Name ( 520)
Fuji Photo Film Co., Ltd. Representative Onishi Award 4 Agent 170 1t (988) 5563 Address 805 Ikebukuro White House Building, 1-20-5 Higashiikebukuro, Toshima-ku, Tokyo Figure 7 Contents of amendment As attached (1), specification , page 4, line 7, "This scanning method" is corrected to 1, this scanning direction J. (2), page 14, lines 18 to 2'0 are corrected as follows. ``The output address is increased or decreased by +1 or -1 each time one pixel's data reading is completed or one pixel's data writing is completed using the write clock signal, and the readout is performed.'' (3), page 18, line 11, ``r lea to 18d'' is corrected to ``16a to led''. (4), page 18, line 16, "9x9 window" is corrected to "f9x9, IIXII window". (5), same page 25, line 20, "halftone image forming device 4 days" is corrected to read "r halftone image forming device 55J". (8), page 26, line 2, "driver 51" is corrected to "r driver 4G". (7), Table 3 on page 30 of the same is amended as follows. Table 8 (8) 0 The corrections are made as shown in the correction drawing attached to Figure 6.

Claims (1)

[Claims] 1. For the image signal obtained by scanning the original image, nXn
A window of a pixel matrix (where n is an odd number) is set, and a correction amount S for pixel information amm at the center position of the window is calculated using a predetermined formula based on all pixel information within the window, and the correction #S In the image signal correction method, the image information amm at the center position of the window is corrected according to the amount of correction S, in which the correction amount S is calculated using an added value obtained by adding all pixel information within the window. In doing so, prior to the addition process, the image information of each pixel within the window is divided by an appropriate divisor, and the correction value S is calculated by calculating the effect of the division on the correction value S. An image signal correction method comprising: converting a correction value 5klC obtained by multiplying by a correction coefficient k taking into consideration the correction value Sk, and correcting the image information a, mm using this correction value Sk.