JPS60263522A - Pattern collating circuit - Google Patents

Abstract

PURPOSE:To reduce the number of MOS transistors Trs by providing two kinds of clock and making the operation time of P channel (CH) MOS Trs and that of N CH MOS Trs different from each other. CONSTITUTION:When a clock signal A is changed from level ''1'' to level ''0'' in a pattern collating circuit of all zero detection, a P CH MOS Tr T10 is turned on, and a node 10 becomes v1 volt. Next, input signals A0-A3 are settled, and the signal A is changed from level ''0'' to level ''1'', and thereafter, a clock signal B is changed from level ''0'' to level ''1''. Then, N CH MOS Trs T20-T23 are turned on. If signals A0-A3 are all zero, N CH MOS Trs T30-T33 are all turned off, and the potential of the node 10 is not changed from v1 volt. If any signal, for example, the signal A0 out of signals A0-A3 is ''1'', the Tr T30 is turned on, and the charge of the node 10 is discharged to an earth potential v2 through Trs T20 and T30, and the node 10 becomes 0 volt.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field to which the invention pertains) The present invention relates to a pattern matching circuit using a CMO8 logic circuit in which the number of MOS transistors used is reduced.

(Prior Art) A CMO8 logic circuit always requires a logic gate when performing a logical OR because the power supply is short-circuited when a wired OR is performed. Even when a wired OR is performed using a transfer gate, two or more transfer gates must be operated at the same time, and a perfect OR cannot be obtained.

FIG. 1 shows an example of the configuration of a conventional all-zero detection circuit, and shows a circuit in which the output is ``1'' when all inputs are ``0'' for two types, 4 bits and 32 bits.

In the figure, A, -A, and □ are input signals, F4 and F3□ are output signals, R1tR21RLOQ to R111 are NOR circuits, and N1tNillllIN□. , is a NAND circuit, ■
□ and ■. . is an inverter circuit. All inputs of this circuit are NoR logic circuits, but due to the fan-in conditions of the CMO8 circuit and the conditions described above, in the case of 4 bits, 1
Four MOS transistors are required, and for 32 bits, 92 MoS transistors are required.

FIG. 2 shows the configuration of an example of a pattern matching circuit according to the conventional method, where A0 to A3 and 80 to B3 are input signals;
E1 to E are EX (exclusive) -N.

R circuit, N1 is NAND circuit, ■□ is inverter circuit,
M is the output signal.

This circuit receives input signal A. - Perform a slam check to compare whether the values of the bits of A3 and B0 to B3 are the same.

FIG. 3 shows a detailed circuit diagram of the EX-NOR circuit shown in FIG. 2, and ten MOS transistors are required to realize this.

Furthermore, in order to realize the 4-bit pattern matching circuit shown in FIG. Requires a large MoS transistor.

As described above, since the CMO8 logic circuit cannot realize a wired-OR logic circuit, there is a problem in that a large number of MOS transistors are required when attempting to configure a logic that requires an OR of a large number of bits.

(Object of the Invention) In order to solve the above-mentioned problem, the present invention provides two types of clocks to provide a P-channel Mos transistor and an N-channel Mos transistor.
By varying the operating times of the S transistors and controlling the power supply so that it does not short-circuit, it is intended to realize a pattern matching circuit that uses fewer MOS transistors.The drawings will be described in detail below.

(Structure and operation of the invention) FIG. 4 shows the circuit structure of a 4-bit all-zero detection circuit which is an embodiment of the invention, where T1° is a P-channel MOS transistor, T2° to Tz3°T, 0- T3
3 is an N-channel MoS transistor, clock A
, clock B is a clock signal, A, ~Aa is an input signal, F4 is an output signal, V, , V is a power supply terminal, here v2 is GND, VD voltage is applied to V,
10°20-23 are the node numbers of the wiring.

FIG. 5 is a time chart for operating the circuit of FIG. 4, and t1 to t3 indicate times.

4 and 5, first, at time t□, the clock signal clock A is +vD volts (hereinafter II I PI
) to 0 volts (hereinafter referred to as tIO''), MOS transistor meta a turns on and node 1
Charge is accumulated in the floating capacitance at 0, and the potential at node 10 becomes +■o volts. Next, by time t2, input signal A
. - Confirm A3, then clock A is II O
Change it from It to "1". clock at time t
B is changed from II 0F+ to 0 to u 1 n, thereby turning on the MOS transistors 0""r and 3.

Here, if the input signals A0 to A3 are all ``0'', the MOS transistors 11'=133 are all turned off, and the potential of the node 10 does not change from +vD volts.

If even one of the input signals A0 to A3 is
When it comes to II, for example, if the input signal is It I II, the MOS transistor meta. turns on, and the charge stored in node 10 is transferred to MOS transistor 72DI.
Ta. is discharged to the power supply terminal ■2 through the node l
The potential of O is 0 volts, which is the same as the power supply terminal v2, that is, "°0".
”.

As described above, the circuit of the present invention can realize an all-zero detection circuit using nine MOS transistors, which is smaller than the 14 MoS transistors required in FIG. Furthermore, even when the present invention is expanded to 32 bits, the number of MoS transistors that were conventionally required to be 92 can be reduced to 65.

Although Fig. 4 was explained as an all-zero detection circuit,
Input signal A. - By connecting an inverter in series to A3, it becomes possible to detect any pattern that can be realized by input and signal 〇 to A3. For example, input signal A
If input signals A and l are used instead of 3, the output signal F4 will be output only when the input signals 〇 to A are in the “OOO1” pattern.
It becomes possible to create a logic such that It I II.

FIG. 6 is a block diagram of an embodiment of the pattern matching circuit of the present invention having the same function as that of FIG. 2, and is T□. is a P-channel MoS transistor, T2°~La+T30-T,
1T40-T47 is N-channel MO8)-Rangemetal,
L O”x, t is an inverter circuit, clock A
.

clock B is a clock signal, A, ~A, ,B,
~B is the input signal, M is the output signal, V□+vg is the fourth
The same power supply terminals as in the figure, 10 and 20 to 31 are wiring node numbers.

Note that this circuit also operates according to the time chart shown in FIG.

First, the clock signal (Block A is 111”→”O
"→"1", charge is accumulated in the node 10 and the potential becomes +vo volts. Next, the clock signal clock
When B changes from °IO" to "1", the MOS transistor meta O""" T23 turns on. Here, node 20
．． MOS transistor meta++1T4゜tT31tT4
1. Inverter circuits 20, 24, power supply terminal v2 is 2
Human power (7) It constitutes an EX-OR circuit, and if input signal A. If and B agree, then A, = “O”, B, -
1", Mo8) - Langimeta T41.T
a□ is turned on, and conduction occurs between the node 20 and the power supply terminal 72.

If the four sets of EX-OR circuits are not conductive, that is, if the patterns of the input signals A0 to A3 and B0 to B3 match, the potential of the node IO does not change and the output signal M becomes 111''. In this way, the pattern matching circuit of the present invention is a MOS
This can be realized using 37 transistors, which is smaller than the conventional 50 transistors shown in FIG. Furthermore, even if this circuit is expanded to 32 bits, the number of MOS transistors will be reduced to 4, which was previously the case.
What used to require 0.06 pieces can now be realized with 289 pieces, significantly reducing the number of pieces used.

Although the present invention has the problem of requiring a clock signal, this does not pose a major problem as the logic device uses various clocks to achieve high speed and simplify the logic design.

In addition, in the above explanation, in FIGS. 4 and 6,
Although only one P-channel MoS transistor T111 is used, a plurality of P-channel MoS transistors can be used in parallel to increase speed.

Furthermore, the operations of the P-channel Mo8)-Rangemetal T1° and the others have been described as N-channel Mo8h transistors, but the Mo8)-Rangemetal Ti. It is also possible to make the terminals N-channel type and the others P-channel types. In this case, if the polarity of the power supply terminals V, , V is inverted and the logic value is considered as negative logic, the operation described above will be achieved. There is no need to explain that they are the same.

(Effects) As explained above, the present invention can realize a pattern matching circuit that requires logical OR of multiple inputs with a small number of MOS transistors, and its circuit configuration is simple, so it can be easily integrated into LSI. It has the advantage of being extremely effective.

[Brief explanation of drawings]

Figure 1 is a diagram showing an example of the configuration of an all-zero detection circuit according to the conventional method, Figure 2 is a diagram showing the configuration of an example of a slam verification circuit according to the conventional method, and Figure 3 is the same as shown in Figure 2. E
A detailed circuit diagram of the X-NOR circuit, FIG. 4 is a diagram showing the configuration of an all-zero detection circuit which is an embodiment of the present invention, and FIG. 5 is a time chart for operating the circuits of FIGS. 4 and 6. , FIG. 6 is a block diagram of an embodiment of the pattern matching circuit of the present invention. A, B...Input signal, F, M...Output signal, R
・” NOR circuit, N-NAN 1ml path, ■ ・・・
Inverter circuit, E...EX-NOR circuit, T
...MOS transistor, clock Cclock
B...Clock signal, ■...Power supply terminal, 10
．． 20-31... Node number of the wire assembly, t... Time. Patent applicant Nippon Telegraph and Telephone Public Corporation Figure 1 Figure 2 Figure 3 Figure 4 ヮ. Figure 5 Ll i! 3

Claims (1)

[Claims] In the CMO8 logic circuit, a first circuit in which a plurality of -channel MOS transistors are connected in series, a second circuit in which a plurality of the first circuits are connected in parallel, and the MO
The S transistor has a third circuit formed by connecting one or more MOS transistors of complementary channels in parallel, and the second circuit and the third circuit are connected in series, and both ends thereof are connected in series. The gate of one MOS transistor in the first circuit is connected to the power supply terminal, and the gate of one MOS transistor in the first circuit is connected to the second
1. A pattern matching circuit, wherein the same logical value is input to each of the circuits.