JPS60262449A - Lead frame for semiconductor - Google Patents

Lead frame for semiconductor

Info

Publication number
JPS60262449A
JPS60262449A JP59118679A JP11867984A JPS60262449A JP S60262449 A JPS60262449 A JP S60262449A JP 59118679 A JP59118679 A JP 59118679A JP 11867984 A JP11867984 A JP 11867984A JP S60262449 A JPS60262449 A JP S60262449A
Authority
JP
Japan
Prior art keywords
alloy
lead frame
plating layer
layer
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59118679A
Other languages
Japanese (ja)
Inventor
Yoshiaki Wakashima
若島　喜昭
Osamu Yoshioka
修 吉岡
Ryozo Yamagishi
山岸　良三
Norio Okabe
則夫 岡部
Sadao Nagayama
長山　定夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Hitachi Ltd
Original Assignee
Hitachi Cable Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd, Hitachi Ltd filed Critical Hitachi Cable Ltd
Priority to JP59118679A priority Critical patent/JPS60262449A/en
Publication of JPS60262449A publication Critical patent/JPS60262449A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/291—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/485—Material
    • H01L2224/48505—Material at the bonding interface
    • H01L2224/48599—Principal constituent of the connecting portion of the wire connector being Gold (Au)
    • H01L2224/486—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/48638—Principal constituent of the connecting portion of the wire connector being Gold (Au) with a principal constituent of the bonding area being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/48644—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83801—Soldering or alloying
    • H01L2224/83805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H01L2224/854—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/85438—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/85444—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To improve heat-dissipating properties and resin sealing properties by forming an alloy plating layer having excellent oxidation resistance and adhesive properties with a resin onto a base body for a lead frame and partially shaping an Au plating layer onto said layer. CONSTITUTION:An Ni-Sn alloy plating layer 13 is shaped onto a base body 1 consisting of a band plate made of Cu as a foundation layer, and Au plating layers 2 are formed partially to a semiconductor element fixing section 4 in the upper section of the alloy plating layer 13 and functioning sections containing internal lead terminal sections. When an AC package is manufactured by using such a lead frame, an Si pellet 3 is placed on the layer 2 on the element fixing section 4, and Au and Si are joined in a eutectic manner. The pellet 3 and the internal lead terminal sections are connected and wired by gold wires 5, and the whole is sealed by a molding resin 21. Either one of a Co-Sn or Ni-Co-Sn alloy may also be employed as the layer 13. According to the constitution, adhesive properties with the resin can be improved even when a Cu group metal is used as the base body.

Description

【発明の詳細な説明】 〔発明の背景と目的〕 本発明はＩＣ，、）ランシスター等半導体装置の組立て
に用いられる半導体用リードフレームに関する。DETAILED DESCRIPTION OF THE INVENTION [Background and Objectives of the Invention] The present invention relates to a semiconductor lead frame used for assembling semiconductor devices such as ICs, Runsisters, etc.

従来、ＩＣなどの半導体装置用リードフレームの素材と
しては、熱膨張係数が低くガラスあるいはセラミックと
の封着性が良好なコバール（ｐｅ−２９％Ｎｉ−１６％
ＣＯ）、４２合金（Ｆｅ−４２％Ｎｉ）などのｐｅ−Ｎ
ｉ系合金、あるいは安価で熱放散性に優れた銅系金属が
使用される。Traditionally, Kovar (PE-29% Ni-16%) has been used as a material for lead frames for semiconductor devices such as ICs, as it has a low coefficient of thermal expansion and good sealing properties with glass or ceramic.
CO), pe-N such as 42 alloy (Fe-42%Ni)
An i-based alloy or a copper-based metal that is inexpensive and has excellent heat dissipation properties is used.

このような素材は、一般にスタンピングあるいはエツチ
ングにより例えば第１図のようなパターン形状にされた
あと、機能部と呼ばれるシリコンチップ等半導体素子を
接合する半導体素子固定部及び半導体素子とＡＵ又はＡ
４細線で接続配線される内部リード端子部にそれぞね部
分Ａｕめつき又は部分Ａグめっきが施され、これにより
所望の半導体用リードフレームに仕上げられる。Such a material is generally stamped or etched into a pattern shape as shown in FIG.
The internal lead terminal portions to be connected and wired using four thin wires are partially Au-plated or partially A-plated, thereby completing the desired semiconductor lead frame.

このような構成のリードフレームとしては、一般に素材
として銅系金属が使用された場合にはＡＩｉ＋めっきし
たリードフレームが安価なリードフレームとして広く使
用される。この場合Ａｕｔ６つきも可能であるが、Ａｕ
めっきは銅素地と十分熱拡散しやすいために厚めつきし
なければならず高価となる。As a lead frame having such a configuration, when a copper-based metal is generally used as a material, an AIi+ plated lead frame is widely used as an inexpensive lead frame. In this case, it is also possible to use Au6, but Au
Since the plating easily diffuses heat with the copper base, it must be thick and expensive.

一方、素材としてＦｅ−ＮＩ系合金が使用された場合に
はＡ、ＬＪめっきあるいはＡ２めっきしたリードフレー
ムがそれぞｈ信頼性に優れたリードフレームとして使用
される。特に高信頼性が要求される半導体装置について
は、ｌ；’ｅ−Ｎｉ系合金にＡ、ｕめっきしたリードフ
レームが使用される。On the other hand, when Fe--NI alloy is used as the material, A-, LJ-plated, or A2-plated lead frames are used as lead frames with excellent reliability. Particularly for semiconductor devices that require high reliability, lead frames made of l;'e-Ni alloy plated with A and U are used.

近年半導体装置の低コスト化を図るだめ、封止材料とし
てガラス、セラミックに代わるプラスチックの使用が多
くなりつつある。プラスチックは安価であるが、熱伝導
性がセラミックスなどと比較して劣る欠点がある。又、
半導体装置の高集積化が進み、消費電力の増加により発
熱量が大きく／ なる傾向にある。したがって、Ｆｅ−Ｎｉ系合金からな
るリードフレームを用いてプラスチック封止した半導体
装置では熱放散性が悪いため、放熱−が不足してチップ
温度が上昇し、故障発生率の増大あるいは計算スピ−ド
の遅延などを招く欠点がある。In recent years, in order to reduce the cost of semiconductor devices, plastics have been increasingly used as sealing materials instead of glass and ceramics. Although plastic is inexpensive, it has the disadvantage that its thermal conductivity is inferior to ceramics and the like. or,
As semiconductor devices become more highly integrated, the amount of heat generated tends to increase due to increased power consumption. Therefore, semiconductor devices encapsulated in plastic using lead frames made of Fe-Ni alloys have poor heat dissipation, resulting in insufficient heat dissipation and increased chip temperature, which may increase the failure rate or reduce calculation speed. There are drawbacks such as delays in

この欠点を解消するため、熱放散性に優れた銅系金属の
リードフレームを用いる方法がある。しかし銅系金属の
リードフレームには、これまでグイボンディングおよび
ワイヤボンティングの際の熱の影響により表面酸化が進
行し、この酸化膜が銅素地との密着性が弱いことから樹
脂封止後酸化膜と銅素地との隙間を通って水が侵入し、
腐食が発生しやすいという欠点がある。このだめ銅系金
属のリードフレームは、高信頼性になく低コスト化が要
求される半導体装置に適用され、高信頼性の半導体装置
に適用することは適当で々いとされていた。In order to overcome this drawback, there is a method of using a lead frame made of a copper-based metal that has excellent heat dissipation properties. However, surface oxidation of copper-based metal lead frames progresses due to the influence of heat during wire bonding and wire bonding, and this oxide film has poor adhesion to the copper base, so oxidation occurs after resin sealing. Water enters through the gap between the membrane and the copper base,
It has the disadvantage of being prone to corrosion. This copper-based metal lead frame was applied to semiconductor devices that lacked high reliability and required low cost, and was considered inappropriate for use in highly reliable semiconductor devices.

本発明の目的は、前記した従来技術の欠点を解消し、銅
系金属のリードフレームを使用する場合において半導体
装置の信頼性を損うことなく熱放散性を改良することに
より、半導体装置の低コスト化及び高集積化を図ること
ができる新規な構成の半導体用リードフレームを提供す
ることにある。An object of the present invention is to solve the above-mentioned drawbacks of the prior art and to improve the heat dissipation properties of semiconductor devices without impairing their reliability when using copper-based metal lead frames. It is an object of the present invention to provide a lead frame for a semiconductor with a novel configuration that can reduce costs and increase integration.

〔発明の概要〕[Summary of the invention]

すなわち本発明の要旨は、半導体用リードフレームの基
体上にＮｉ−Ｓｎ合金、Ｃｏ−Ｓｎ合金ある　）いはＮ
　ｉ　−Ｃｏ　−８ｎ合金のいずれか一つの合金めっき
層を下地層として設け、さらにその上の少なくとも半導
体素子固定部及び半導体素子と金属細線で接続配線され
る内部リード端子部にそれぞれ金めっき層を設けたこと
にある。That is, the gist of the present invention is that a Ni-Sn alloy, a Co-Sn alloy, or a N
An alloy plating layer of any one of the i-Co-8n alloy is provided as a base layer, and further a gold plating layer is provided on at least the semiconductor element fixing part and the internal lead terminal part connected to the semiconductor element with thin metal wires. This is because it was established.

Ｎｉ、Ｃｏ、Ｓｎの３元素からなるＳｎを含有する２元
又は３元合金においてＳｎ含有量は、合金の半田付性を
安定させる意味では多い方が優れているが、合金の耐熱
性を上げる意味ではあまり多くすることができない。In a binary or ternary alloy containing Sn, which is made up of the three elements Ni, Co, and Sn, a higher Sn content is better in terms of stabilizing the solderability of the alloy, but it also increases the heat resistance of the alloy. In a sense, you can't do too much.

〔実施例〕〔Example〕

本発明半導体用リードフレームの構成を従来のリードフ
レームとの対比で説明する。The structure of the semiconductor lead frame of the present invention will be explained in comparison with a conventional lead frame.

第１図は従来のＩＣ用リードフレームの一例を示す平面
図、第２図はその要部拡大断面図である。FIG. 1 is a plan view showing an example of a conventional IC lead frame, and FIG. 2 is an enlarged cross-sectional view of a main part thereof.

この例においては４２合金からなる基体１上に部分的に
Ａｕめっき層２を設けている。このＡＬＩめっき層２の
設けた位置は、す＝ドフレームの機能部と呼ばれる半導
体素子固定部４及び内部リード端子部８である。１０は
外部リード部である。このようなリードフレームを用い
てＩＣパッケージを作るには、その半導体素子固定部４
に例えばＡｕ−８ｉ共晶ろう材６を介してＳＩペレット
３を配設　５− しくグイボンディング）、このＳｉペレット３とリード
フレームの内部リード端子部８のＡｌｌめっき層２とを
金線５で接続配線しくワイヤボンディング）、これをモ
ールド樹脂（プラスチック）２１で封止する。In this example, an Au plating layer 2 is partially provided on a substrate 1 made of 42 alloy. The ALI plating layer 2 is provided at the semiconductor element fixing part 4 and the internal lead terminal part 8, which are called functional parts of the frame. 10 is an external lead portion. To make an IC package using such a lead frame, the semiconductor element fixing part 4 is
For example, an SI pellet 3 is placed through an Au-8i eutectic brazing filler material 6 (5-4 bonding), and this Si pellet 3 and the All plating layer 2 of the internal lead terminal portion 8 of the lead frame are connected with a gold wire 5. The connection wiring (wire bonding) is sealed with mold resin (plastic) 21.

第３図は従来のリードフレームの他の例を示す要部断面
図であって、銅の基体１１−ヒに部分的にＡ１めっき層
１２を設けている。この場合も前記と同様にＩＣパッケ
ージを構成する。FIG. 3 is a sectional view of a main part showing another example of a conventional lead frame, in which an A1 plating layer 12 is partially provided on a copper base 11-1. In this case as well, the IC package is constructed in the same manner as described above.

このような従来技術においては、上述した如き欠点があ
った。すなわち第２図の例では高集積度化した半導体素
子を用いた場合発熱量が大きく々るにも拘わらず、リー
ドフレームの基体として熱伝導性の低い４２合金を使用
しているだめ、半導体素子の温度が上昇して故障率の増
大あるいは計算スピードの遅延などの問題を招く欠点が
あった。Such conventional techniques have the drawbacks mentioned above. In other words, in the example shown in Figure 2, although the amount of heat generated is large when a highly integrated semiconductor element is used, the semiconductor element is The disadvantage is that the temperature rises, leading to problems such as an increase in the failure rate and a delay in calculation speed.

この対策として第３図のように、安価で熱伝導性の良い
銅のリードフレームを用いる例も見られるが、この場合
半導体装置組立時のグイボンディング及びワイヤボンデ
ィング工程における熱の影　６− 響により銅表面に銅素地との密着性の悪い酸化膜が形成
されるので、これによりモールド樹脂２１ト銅リードフ
レーＬ（基体）１１との間の密着性が低下して水の侵入
が容易となり、信頼性が低下するという欠点があった。As a countermeasure to this problem, as shown in Figure 3, there are examples of using copper lead frames that are inexpensive and have good thermal conductivity, but in this case, due to the influence of heat in the wire bonding and wire bonding processes during semiconductor device assembly. Since an oxide film with poor adhesion to the copper base is formed on the copper surface, this reduces the adhesion between the mold resin 21 and the copper lead frame L (substrate) 11, making it easy for water to enter. This had the disadvantage of reduced reliability.

本発明のり一部フｌ／−ムは上記欠点のない新規な構成
のリードフレームに関するものであって、第４にその一
例を示すように銅又は銅合金からなる基体上に耐酸化性
が良好かつ樹脂との密着性が良好なＮＩ−８μ合金、Ｑ
ｏ−８μ合金あるいはＮｉ−Ｃ０−８μ合金のいずれか
一つの合金めっき層１３を下地層と１〜で設け、さらに
その上に部分的にＡＬＩめっき層２を設けることにより
、熱放散性及び樹脂封止性を改良したものである。The adhesive film of the present invention relates to a lead frame with a novel structure that does not have the above-mentioned drawbacks, and fourthly, as shown in an example, it is formed on a substrate made of copper or copper alloy with good oxidation resistance. NI-8μ alloy with good adhesion to resin, Q
By providing an alloy plating layer 13 of either o-8μ alloy or Ni-C0-8μ alloy with the base layer 1 to 1, and further providing an ALI plating layer 2 partially on top of that, heat dissipation properties and resin It has improved sealing properties.

つぎに第４図にもとづいて本発明リードフレームの具体
例に説明する。厚さ０．２５４ｍｍの銅の帯板からなる
基体１１上に、電気めっき法によりＮｉ−８μ合金めっ
き浴（ピロＩＪン酸含有）から厚さ０．２　ＭのＮ　ｉ
　−３ｎ合金めっき層１３を下地層として基体全体に設
け、さらにその−ヒの半導体素子固定部４及び内部リー
ド端子部８を含む機能部に電気めっめ法により中性Ａｌ
ｌめっき浴から厚さ３μのＡ−ｕめっき層２を部分的に
設けた。Next, a specific example of the lead frame of the present invention will be explained based on FIG. On the substrate 11 consisting of a copper strip plate with a thickness of 0.254 mm, Ni with a thickness of 0.2 M is applied by electroplating from a Ni-8μ alloy plating bath (containing pyro-IJ acid).
A -3N alloy plating layer 13 is provided as a base layer over the entire base, and the functional parts including the semiconductor element fixing part 4 and the internal lead terminal part 8 are coated with neutral Al by electroplating.
An A-u plating layer 2 having a thickness of 3 μm was partially provided from a plating bath.

なお、このよう々リードフレームを用いてＡ、　Ｃパッ
ケージを作る場合は、従来例で説明したと同様に半導体
素子固定部のＡ−１１めっき層上にＳ１ペレツト３を３
５０℃を越える温度で押付け、Ａｕ−８Ｉ共共晶台を行
なう。又、この８１ペレツト３とリードフレームの内部
リード端子部８とを金線により接続配線し、全体をモー
ルド樹脂２１で封止し、ＩＣパッケージを構成する。In addition, when making A and C packages using lead frames like this, three S1 pellets 3 are placed on the A-11 plating layer of the semiconductor element fixing part as explained in the conventional example.
Au-8I eutectic stand is performed by pressing at a temperature exceeding 50°C. Further, this 81 pellet 3 and the internal lead terminal portion 8 of the lead frame are connected and wired using gold wire, and the whole is sealed with mold resin 21 to form an IC package.

ここで上記のように作成した本発明リードフレームと従
来例リードフレームについて、それぞれ大気中４００℃
×２分の加熱劣化を行い、それぞれ外部リード部に形成
された酸化膜の密着性を粘着テープピーリング法により
調べだ。判定はＯ：剥離しない、Ｘ：剥離した。　１ 又、大気中４００℃×２分の加熱劣化後のそれぞれのリ
ードフレームをモールド樹脂２１により封止した後、樹
脂とリードフレームとの密着性をそれぞハ引張強度をも
って調べた。この場合の判定はＯ：密層性良好〜酸化膜
がリードフレームから剥離しない、Ｘ　：　Ｗｊ着性不
良〜酸化膜がリードフレームから剥離した。Here, the lead frame of the present invention and the conventional example lead frame produced as described above were heated at 400°C in the atmosphere.
Heat deterioration was performed for 2 minutes, and the adhesion of the oxide film formed on each external lead was examined using an adhesive tape peeling method. The evaluation was O: not peeled off, X: peeled off. 1. In addition, each lead frame after being heated and deteriorated in the atmosphere at 400° C. for 2 minutes was sealed with mold resin 21, and then the adhesion between the resin and the lead frame was examined in terms of tensile strength. In this case, the evaluation was O: good layer density - the oxide film did not peel off from the lead frame, and X: poor Wj adhesion - the oxide film peeled off from the lead frame.

又、リードフレームの熱伝導度についてそれぞれ調べ、
判定は０　：　０．３ｍ／−／ｚ／ｓｅｃ／１？：以上
、Ｘ：０、３　Ｃ＊／ｄ／ｃｍ／ｓｅｃ／　℃未満して
区分した。In addition, we investigated the thermal conductivity of each lead frame.
Judgment is 0: 0.3m/-/z/sec/1? : above, X: 0, less than 3 C*/d/cm/sec/°C.

以上の判定結果をまとめて表に示すとつき゛のとおりで
ある。The above judgment results are summarized in the table below.

この表から明らかなように、本発明のリードフレームは
樹脂との密着性を改善し、熱放散性に優れた特性を示す
ことが認められる。As is clear from this table, it is recognized that the lead frame of the present invention has improved adhesion with resin and exhibits excellent heat dissipation properties.

なお、上記実施例においては下地めっき層上に直接Ａｕ
めっき層を部分的に設けたが、下地めっき層とＡｕめっ
き層の密着を安定化させるため、９− それらの間にＰａＸＲ，Ｊ　Ｉ　ｎ、　Ｒ，ｕ、　Ａ−
ｆ、Ｃｕなどの極薄いめっき層を設けてもよい。In addition, in the above example, Au was directly deposited on the base plating layer.
Although the plating layer was partially provided, in order to stabilize the adhesion between the base plating layer and the Au plating layer, 9- PaXR, J In, R, u, A- were placed between them.
An extremely thin plating layer of f, Cu, or the like may be provided.

又、本発明によればＡｌｌめっき層以外のリードフレー
ムの表面ばＮｉ−８μ合金、Ｃ０−８μ合金あるいはＮ
ｉ−Ｃｏ−８μ合金のめっき層で構成されるから、基体
としてはかかる合金めっき層との密着性を考慮して表面
にＮＩ又はＮ１合金をめっきしたものを使用することが
できる。Further, according to the present invention, the surface of the lead frame other than the All plating layer is coated with Ni-8μ alloy, C0-8μ alloy or N
Since it is composed of a plating layer of an i-Co-8μ alloy, a substrate whose surface is plated with NI or N1 alloy can be used in consideration of adhesion with the alloy plating layer.

〔発明の効果〕〔Effect of the invention〕

本発明のリードフレームは、基体上にＮｉ−８μ合金、
Ｃ０−８μ合金あるいはＮｉ−Ｃｏ−８μ合金のいずれ
か一つの合金めっき層を設け、さらにその上の機能部に
部分的にＡｕめっき層を設けたものであるから、Ａ、ｕ
めっき層以外は樹脂との密着性に優れた上記合金めっき
層が存在するだめ、このリードフレームを用いて樹脂封
止してＩＣパッケージを構成すれば、基体として銅系金
属を用いた場合でも樹脂との密着性が改善され信頼性に
優れた低コストの半導体装置を得ることができる。The lead frame of the present invention has a Ni-8μ alloy on the base,
An alloy plating layer of either C0-8μ alloy or Ni-Co-8μ alloy is provided, and furthermore, an Au plating layer is partially provided on the functional parts above it, so A, u
Except for the plating layer, there is the above-mentioned alloy plating layer that has excellent adhesion to the resin, so if this lead frame is used to seal the IC package with resin, even if a copper-based metal is used as the base material, the resin will remain intact. It is possible to obtain a low-cost semiconductor device with improved adhesion and excellent reliability.

又、本発明は半導体装置の信頼性を損うことな＝ｌ〇− 〈上記リードフレームの基体として銅系金属を用いるこ
とができるが、この場合はさらに熱放散性に優れたリー
ドフレームとして半導体装置の高集積化に応じることが
できる。Furthermore, the present invention can be used without impairing the reliability of the semiconductor device. It can respond to higher integration of devices.

以上のように本発明は半導体装置の低コスト化及び高集
積化を図ることができる新規な構成の半導体用リードフ
レームを提供したものであり、その工業的価値はきわめ
て太きい七いえる。As described above, the present invention provides a lead frame for a semiconductor having a novel structure that can reduce the cost and increase the integration of semiconductor devices, and its industrial value can be said to be extremely great.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のＩＣ用リードフレームの一例を示す平面
図、第２図は第１図Ａ、　−Ａ、’断面の拡大断面図、
第３図は従来のＩＣ用リードフレームの他の例を示す要
部断面図、第４図は本発明の一実施例に係るリードフレ
ームの要部断面図である。 に基体、２：ＡＬＩめっき層、３：ＳＩペレット、４：
半導体素子固定部、５：金線、６：Ａｕ−８ｉ共晶ろう
材、８：内部リード端子部、１２：Ａグめっき層、１３
　：　Ｎｉ−８ｎ合金めっき層、２１：樹脂１１− ＊４１Ｄ２１ ２５２FIG. 1 is a plan view showing an example of a conventional IC lead frame, and FIG. 2 is an enlarged sectional view of the cross section of FIG.
FIG. 3 is a sectional view of a main part showing another example of a conventional IC lead frame, and FIG. 4 is a sectional view of a main part of a lead frame according to an embodiment of the present invention. Substrate, 2: ALI plating layer, 3: SI pellet, 4:
Semiconductor element fixing part, 5: Gold wire, 6: Au-8i eutectic brazing material, 8: Internal lead terminal part, 12: A plated layer, 13
: Ni-8n alloy plating layer, 21: Resin 11- *41D21 252

Claims (1)

【特許請求の範囲】 １、　半導体用リードフレームの基体上にＮｉ−８ｎ合
金、Ｃｏ−８ｎ合金あるいはＮ１−ｃｏ−８ｎ合金のい
ずれか一つの合金めっき層を下地層として設け、さらに
その上の少なくとも半導体素子固定部及び半導体素子と
金属細線で接続配線される内部リード端子部にそれぞれ
金めっき層を設けてなることを特徴とする半体用リード
フレーム。 ２　基体が銅または銅合金からなることを特徴とする特
許請求の範囲第１項記載の半導体用リードフレーム。[Claims] 1. An alloy plating layer of any one of Ni-8n alloy, Co-8n alloy, or N1-co-8n alloy is provided as a base layer on the base of a semiconductor lead frame, and further A lead frame for a half body, characterized in that a gold plating layer is provided on at least a semiconductor element fixing part and an internal lead terminal part connected to the semiconductor element by a thin metal wire. 2. The lead frame for a semiconductor according to claim 1, wherein the base body is made of copper or a copper alloy.
JP59118679A 1984-06-08 1984-06-08 Lead frame for semiconductor Pending JPS60262449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59118679A JPS60262449A (en) 1984-06-08 1984-06-08 Lead frame for semiconductor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59118679A JPS60262449A (en) 1984-06-08 1984-06-08 Lead frame for semiconductor

Publications (1)

Publication Number Publication Date
JPS60262449A true JPS60262449A (en) 1985-12-25

Family

ID=14742518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59118679A Pending JPS60262449A (en) 1984-06-08 1984-06-08 Lead frame for semiconductor

Country Status (1)

Country Link
JP (1) JPS60262449A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1090392C (en) * 1996-10-30 2002-09-04 矢崎总业株式会社 Terminal material and terminal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1090392C (en) * 1996-10-30 2002-09-04 矢崎总业株式会社 Terminal material and terminal

Similar Documents

Publication Publication Date Title
US4736236A (en) Tape bonding material and structure for electronic circuit fabrication
US8450861B2 (en) Integrated circuit device with semiconductor device components embedded in plastic housing composition
JP2002299540A (en) Semiconductor device and manufacturing method therefor
JPS60262449A (en) Lead frame for semiconductor
JP2002064173A (en) Preplating of small-sized no-lead frame for semiconductors
JPS61139050A (en) Lead frame
JPH03191560A (en) Resin-sealed semiconductor device
JPS6232622B2 (en)
JPS63293963A (en) Resin-sealed semiconductor device
JPS5854507B2 (en) Lead frame manufacturing method
JPS61137352A (en) Semiconductor device
JPS639957A (en) Semiconductor lead frame
JPS60119765A (en) Resin-sealed semiconductor device and lead frame used therefor
JPS6329960A (en) Lead frame for resin seal type semiconductor device
JPH0567069B2 (en)
JPS6049657A (en) Semiconductor device
JPS62105457A (en) Semiconductor device
JPS6129139A (en) Semiconductor device
JPS62205650A (en) Substrate for semiconductor device
JPH03296250A (en) Semiconductor device sealed with resin
JP4123719B2 (en) Tape carrier and semiconductor device using the same
JPH0284744A (en) Manufacture of semiconductor device
JPS60147146A (en) Lead frame for semiconductor
JPH0519820B2 (en)
JPH0762273B2 (en) Electronic component manufacturing method