JPS60261221A - Analog digital convertor - Google Patents

Abstract

PURPOSE:To reduce the number of circuits that control switches by making reference potential of a capacitor array not equal in all capacity at the 2nd sampling of a convertor and thereby nearly halving the number of switches in the resistance array. CONSTITUTION:Analog signals are inputted to the capacitor array 14 and comparator 13 of an A/D convertor through switches 12, 15. A resistance array 31 is connected to another end of a capacitor connected in common of the array 14 through a switch. Switches 12, 15 are controlled by timing of a timing generator 16. Output of the comparator 13 is inputted to a decoder 32 for capacitor array signal and a decoder 33 for resistance array signal, and charging or discharging of the condenser is controlled by output of the capacitor that makes output of decoders 32, 33 input and resistance array control circuits 34, 35. Each capacity of reference potential of the capacitor array is made to unequal throughout, and the number of switches of the resistance array is halved, and constitution of the convertor is simplified.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to an analog-to-digital converter (hereinafter referred to as an AD converter), and particularly to a converter that converts bipolar analog input voltage into a digital signal using a unipolar reference voltage. This relates to an AD converter.

[Prior art]

Figure 1 shows the currently internationally determined μm of conventional AD converters.
255 is a diagram showing a capacitive connection as segment 1 using the H.255 rule as an example. FIG. In this Figure 1.

An analog input terminal 11 (this symbol is also used to mean input voltage) is connected to the positive side of a comparator 13 and a capacitor array 14 via a switch 12, as well as to a switch 15. The other connection of switch 15 is ground. 16 is a timing generator for controlling the switch circuits 1, 2 and 15;

The capacitances of the capacitors C1 to Cn of the capacitor array 14 are expressed as the capacitance C,
A capacity of 1 times, 2 times, ... 2yl-1 times is selected. Movable terminal d1 s dz + ""n is terminal a
l+a2 +...y via the first reference potential V
+bl+b2+...b while being connected to REFI
is connected to the resistor array 17 through the terminal (!1
+(!2+... is connected to the ground potential GND via cn. VREFI is connected to one end of the resistor array 17.

Further, the ground potential GND is connected to the other end of the resistor array 17. The negative side of the comparator 13 is connected to a second reference voltage VREF2 which is an auto-zero output for offset adjustment.

The output of comparator 13 is connected to register 21.

TI of the outputs of the register 21 is connected to the capacitor array switch control circuit 22 and the resistor array switch 23, and T2 to T4 of the outputs of the register 21 are connected to the capacitor array positive signal decoder 24 and It is connected to the array negative signal decoder 25. Furthermore, T5 to T8 of the outputs of the register 21 are connected to a resistor array positive signal decoder 26 and to a resistor array negative signal decoder 27.

The output of the capacitor array positive signal decoder 24 and the output of the capacitor negative signal decoder 25 are connected to the capacitor array switch circuit 22.

Further, the output of the resistor array positive signal decoder 26 and the output of the resistor array negative signal decoder 27 are connected to the resistor array switch control circuit 23. Output 28 of capacitor array switch control circuit 22 is connected to capacitor array 14 , and output 29 of resistor array switch control circuit 23 is connected to resistor array 17 .

Next, the operation of the AD converter shown in FIG. 1 will be explained. By turning on the switch 15, the positive potential of the comparator 13 is set to the ground potential GND, and the movable switches d and -dn are connected to the switches cl to cn for initial setting. Turn off switch 15 and switch 12
When turned on, the positive side potential of the comparator 13 is charged to the same potential as the input voltage 11 (referred to as first sampling).

Next, the switch 12 is turned off, and the comparator 13 determines the polarity.

If it is determined to be a positive sign, the signal 'ri stores the positive sign and becomes 2.
During the next second sampling, the movable switches di-dn and the switches a1-an are connected, and the switch 12 is turned on. By successively comparing these sampling voltages, parallel output signals T2 to T8 are obtained. This output T2
~ T4 is decoded by the positive signal decoder 24, and then the polarity signal T1 is decoded by the capacitor array switch control circuit 22.
The capacitor array]4 switches are controlled through the capacitor array.

In addition, if the signal is determined to be a negative signal in the second Zannor, the signal TI stores a negative sign and connects the movable switches dl-dn to the switches 01 to cn at the time of the second sampling.
Turn on switch 12.

Thereafter, the output of the negative signal decoder 25 is used to control the switches of the capacitor array 14 via the capacitor array switch control circuit 22 in the same manner as for the positive sign.

Further, the parallel signals T5 to T8 are pits that determine the number of steps within a segment, but if the first sample is determined to be a positive sign, the parallel signals T5 to T8 are sent to the output 29 of the resistor array switch control circuit 23 via the positive signal decoder 26. Resistor array 17-3
Select one switch among the four switches f1 to f34 and turn it on + VREFi to resistor array 1
A voltage corresponding to the step value of the PCM signal divided by 7 is supplied.

If the first sensor determines that it is a negative sign, the output 29 of the resistor array switch control circuit 23 selects one switch among the 34 switches of the resistor array 17 via the resistor array negative signal decoder 27. Turn which one on + V
A voltage corresponding to the step value of the PCM signal obtained by dividing REM by the resistor array 17 is supplied. Note that these switches f1 to f34 will be explained later.

In the case of FIG. 1, the signals that control the capacitor play] 4 and the resistor array 17 are the capacitor array positive signal decoder +24 and the capacitor array negative signal decoder 25.
Since the resistor array positive signal decoder 26 and the resistor array negative signal decoder 27 are separated, the circuit becomes large-scale and complicated due to the large number of switches in the resistor array. It had the disadvantage of not being suitable.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an AD converter with a reduced number of resistor arrays including a large number of switches and a circuit for controlling said switches.

[Structure of the invention]

In order to achieve the above object, the present invention distributes the potential applied to the lower terminal of the capacitor array differently from the conventional one. No, this is a capacitor array in which one end of each of these capacitors is commonly coupled.

Comparison means for comparing the potential difference between the potential of the capacitor array and one reference potential, and a register for storing a digital signal including a sign signal and an absolute value bit.

an analog-to-digital converter having a resistor array for charging or discharging an analog signal into said capacitor and generating a reference potential, ``!, at each other end of said capacitor, and means for first and second sampling; An analog-to-digital converter is obtained in which the reference potential of the capacitor play is not the same potential for all capacitors during two samplings.

〔Effect of the invention〕

With the above configuration, the AD converter according to the present invention requires approximately half the number of switches in the resistor array,
Accordingly, the circuit for controlling this switch can be reduced to about half, and the structure of the decoder can also be simplified.

〔Example〕

The AD conversion circuit of the present invention will be explained in detail below.

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention. In FIG. 2, components that overlap with those in FIG. 1 are given the same reference numerals. As you can see by comparing this Figure 2 with Figure 1,
The number of switches in the resistor array 31 is reduced to 19 compared to the conventional 34, and the capacitor array signal decoder 3
2 has a decoding function for the capacitor array as well as switching between positive and negative signals, and functions as two conventional decoders 24 and 25 in FIG. In addition to the decoding function for the array, it also performs positive/negative signal switching, and functions as two conventional decoders 26 and 27 in FIG. Furthermore, as the number of switches to be controlled by the capacitor play switch control circuit 34 and the resistor array switch control circuit 35 has decreased from 3 or 4 to 19,
That is, as the outputs 36 and 37 are reduced, the structure becomes correspondingly simpler. Other configurations are the first
Same as the figure.

FIG. 3 is a diagram showing an example of the configuration of the resistor array 31 of FIG. 2 according to the present invention together with the conventional resistor array 17 of FIG. 1. In fig.

VREF is the reference voltage VREF1 in Figures 1 and 2.
+el to e19 are the switches 01 to e19 in the resistor array 31 in FIG. 2 as they are.

It is assumed that the resistance values of many resistors without symbols are the same. Therefore, in a specific case, for example, in the system of the present invention shown on the right, if switch e2 is closed during positive input (described later), the output vsR of the resistor array 31 will be 1vRo if eI8 is closed, which is easily understood from the figure. Similarly, when the switches e3 to e16 are pressed, the output vsR of the resistor array 31 sequentially changes stepwise. Note that m represents the resistor connection step.

In Figure 4, before explaining the specific operation, it is necessary to connect a second
What voltage is in the sample (hereinafter referred to as lower voltage)
This is a diagram explaining how the front plate is applied.
(,) shows the conventional method, and (b) shows the method of the present invention. As can be seen from the figure, in the conventional case, the lower voltage of the capacitor array is sampled as a common voltage.

In the case of the present invention, whether the input is positive or negative.

The lower voltage of the capacitor C1, which is the smallest unit of the capacitor array, is different from the common lower voltage of the other capacitors C2 to Cn. More specifically, when there is a positive input, switch e2 is closed to set VREF to the minimum unit of 2, and other lower voltages are set to vREF, and when there is a negative input, switch e18 is closed and REF is set to the minimum of 2. The lower voltage of the unit is set as the lower voltage, and the other lower voltage is set as GND.In other words, the lower voltage of the minimum unit is different from the common lower voltage of other units by 2 VREF.IN is the input voltage I Vo is the array top voltage.

Next, the operation of the apparatus according to the present invention will be explained with reference to FIGS. 1 to 3. Similarly to FIG. 1, as an initial setting, the switch 15 is turned on and the capacitor array 14 is turned on.
The movable switches d1 to dn and the switches cl-'-cn are connected, and the switch 15 is turned off and the switch 12 is turned on as the second sampling, and the positive input terminal of the comparator 13 and the analog input terminal 11 are connected. Charge so that they are at the same potential. Next, the switch 12 is turned off, and the comparator 8 determines the polarity.

If the sign at the first sampling is determined to be positive, the signal T
l memorizes a positive sign, and at the time of the second sampling of the first order, connects the movable switches d and b, connects the movable switches d2 to dn and the switches c2 to Cn, and turns on the switch e2 in the resistor array 31. as resistor array 3
The output VsR of switch 1 is set to 32VREF, and the output of switch 1 is set to 32VREF.
Turn on 2. This output vsR can be said to be the third reference voltage.

If it is determined to be a negative sign, the signal T stores the negative sign, connects the movable switch d1 and the switch b during the second sampling, connects the movable switches d2 to dn and the switches a2 to an, and connects the movable switches d2 to dn to the switches a2 to an, and The switch e18 in the array 31 is turned on to output VSRt 32 vREF, and the switch 12 is also turned on.

After the second sampling, the switch 12 is turned off and the sampling voltages are successively compared to obtain output signals T2 to T8. The output signals T2 to T4 and the sign signal T1 are switched between positive and negative and decoded to switch the switch of the capacitor array 14 so that the output of the comparator 13 approaches the ground potential. The signal is connected to a decode circuit 33 for switching and decoding, and is further sent to a resistor array switch circuit 35.

Its output 37 controls the switches in the resistor array 31.

The following encoding is performed in the same manner as in Fig. 1, so that V2L
Encoding can be performed with only SB corrected, and the following encoding is l
By controlling the LSB, an AD conversion circuit based on the μm255 rule becomes possible.

To explain the above more specifically, in the conventional device shown in FIG. 1, in the case of positive input, the sampling standard is set to vREF
Therefore, the output VSR of the resistor array 17 (same as the potential at the connection point of the resistor array) and the capacitor array upper voltage V
. This is because the sampling standard is set to GND in the case of a negative input.

vSR"("" D 'vREF 2. There are 32 connection points for the resistances t and b, and the switching means requires 34 switches f, ~f34 including both ends. In addition, the configuration of the resistor array switch control circuit 23 is inadequate.Furthermore, four decoders 24 to 27 are required.

On the other hand, in the present invention, in the case of positive input, the first reference voltage of C, which is the minimum unit of the capacitor array, is set to 1...v88. and the reference potential of the other capacitor arrays is V
RKF. Therefore, 2m v =v −...■REF SRREF. In addition, in the case of negative input, the reference potential of C1, which is the minimum unit of the capacitor array, is set to -32 REF.

The reference potential of other capacitor plays is set to GND.

For this reason m “REF. 2 becomes. By changing the coefficient of vIN from the above.

It becomes equivalent to the conventional code string.

To simplify the above, in the case of positive input, the reference voltage of the second sample is 32 vREF, and in the case of negative input, it is 32 vREF.
Then, the encoding becomes simple and can be compared to a step of 1.9vREF, and the number of switches in the resistor array can be reduced from 32 to 19, and as the number of switches is reduced, the resistor array switch control circuit 35 can also be reduced accordingly. However, the decoder can also be switched between positive and negative in the same circuit, so instead of the conventional four (24 to 27), there are now two (32 and 33).
This is a simple method that is suitable for small-scale IC implementation without deteriorating accuracy. Furthermore, although the present invention has been described with respect to the effect of the μ-law, the effect becomes even more pronounced when the A-law and the μ-law are designed to be used in common. That is, A
In the case of the rule, the sampling standard is VREF at the time of positive input.
When r is a negative input, it can be grounded, and the A-law and μ-law can be easily switched on the same chip.

Easily switch between A and μ even outside the IC. pA
When switching functions frequently as a D converter.

By setting the reference voltage of the second step/glue appropriately,
It is possible to increase the number of common working parts and easily handle a wide variety of products.

Margin below

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing a conventional analog-to-digital conversion circuit, FIG. 2 is a circuit diagram showing an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of a resistor array for both the present invention and the conventional one. , FIG. 4 is a diagram showing the lower voltage of the capacitor array at the second normal time for both the present invention and the conventional method. Explanation of symbols: 11 is an analog signal input terminal. 13 is a comparator, 14 is a capacitor array, 16 is a timing generator, 17 is a resistor array, 21 is a capacitor/nostar, 2
2 and 23 are switch control circuits, 24 to 27 are decoders,
31 is a resistor array, 32 and 33' are decoders, 34 and 3
5 is a switch control circuit. VlF, (-, "-'Ro,) is the (first) reference voltage, VRY2 is the second reference voltage I, VSR is the resistor array output voltage (third/reference voltage), and GND is the ground voltage. ,el
-C18 and f] to f34 respectively represent switches. 3rd phase Figure 4 (Q) Positive input 2nd step 7L/ Negative input 77 Frcy42
Bun full (b) 2nd bun array at positive input 2nd +j of angle input 〉F7 sin public V/? FF VREF j4vg Cm.

Claims (1)

[Claims] 1. From a plurality of weighted capacitors. a capacitor array in which one end of each of the capacitors is commonly coupled; a comparison means for comparing the potential difference between the potential of the capacitor array and one reference potential; a register for storing a digital signal including a sign signal and an absolute value bit;
in an analog-to-digital converter having means for individually coupling an analog signal to each other end of said capacitor and for bringing each other end of said capacitor to another reference potential, or to ground potential, or for first and second sampling; . An analog-to-digital converter, wherein the reference potential of the capacitor array is not the same for all capacitors at the time of second sampling.