JPS60216630A - Step generator - Google Patents

Step generator

Info

Publication number
JPS60216630A
JPS60216630A JP6025685A JP6025685A JPS60216630A JP S60216630 A JPS60216630 A JP S60216630A JP 6025685 A JP6025685 A JP 6025685A JP 6025685 A JP6025685 A JP 6025685A JP S60216630 A JPS60216630 A JP S60216630A
Authority
JP
Japan
Prior art keywords
turned
resistor
changeover switch
mode changeover
segment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP6025685A
Other languages
Japanese (ja)
Other versions
JPS613135B2 (en
Inventor
Michinobu Ohata
大畑 道信
Masao Yamazawa
山沢 昌夫
Toshihiko Matsumura
俊彦 松村
Hisaki Tanaka
田中 久己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP6025685A priority Critical patent/JPS60216630A/en
Publication of JPS60216630A publication Critical patent/JPS60216630A/en
Publication of JPS613135B2 publication Critical patent/JPS613135B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/76Simultaneous conversion using switching tree
    • H03M1/765Simultaneous conversion using switching tree using a single level of switches which are controlled by unary decoded digital signals

Abstract

PURPOSE:To constitute a step generator with less number of resistors by controlling on/off of the 1st mode changeover switch and the 2nd mode changeover switch based on the mu rule designation signal or the A rule designation signal. CONSTITUTION:A mode changeover switch S22 is turned on normally, turned off at bit steal, a mode changeover switch S24 is turned off normally and turned on at bit steal based on the mu rule designation signal. The mode changeover switch S22 is turned on and the mode changeover switch S24 is turned on by the A rule designation signal. Switches SW0-SW16 are turned on/off by a low-order bit of a digital signal.

Description

【発明の詳細な説明】 本発明は、PCMで用いられる圧伸コーグ、デコーダの
ステップ発生器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a step generator for a companding cog and decoder used in PCM.

PCM伝送ではアナログ信号をコード化して伝送し、受
信側ではこれをデコードして元のアナログ信号にする。
In PCM transmission, an analog signal is encoded and transmitted, and on the receiving side, this is decoded into the original analog signal.

これに用いられるデコーダは通富第1図に示すように、
セグメント発生器SGGとステップ発生器STGからな
り、前者は第3図に示すセグメントSi (+=1.2
.・・・・・・8)の始点P1を示すアナログ電圧Aを
発生し、後者は該セクントの始、終端P1.P2間を分
割した電圧Bを発生ずる。PCMではコード化に当り小
振幅部分の忠実度を上げるため該部分を拡大しているの
で、符号化入力信号対復号出力信号の間には第3図に示
す如き飽和特性(8セグメント折れ線特性)がある。8
ビット入力信号DSが入ると制御回路CNTは、その上
位複数ビットをセグメント発生器SGCに与えて該複数
ビットにより定められる順位のセグメントSiの始端電
位Aを発生させ、またその下位複数ビットをステップ発
生器STGに与えて該複数ビットにより定められる分割
電位Bを発生させる。これらは加算されてその和が出力
アナログ信号AS2となる。
The decoder used for this is shown in Figure 1 of Tsutomi.
It consists of a segment generator SGG and a step generator STG, and the former has a segment Si (+=1.2
.. . . . 8) generates an analog voltage A indicating the starting point P1 of the sect, and the latter indicates the starting point P1, the ending point P1 . A voltage B is generated by dividing the voltage between P2. In PCM, when encoding, the small amplitude part is enlarged in order to increase the fidelity, so there is a saturation characteristic (8 segment polygonal line characteristic) between the encoded input signal and the decoded output signal as shown in Figure 3. There is. 8
When the bit input signal DS is input, the control circuit CNT supplies the upper bits thereof to the segment generator SGC to generate the starting end potential A of the segment Si in the order determined by the bits, and also generates the lower bits in steps. A divided potential B defined by the plurality of bits is generated. These are added and the sum becomes the output analog signal AS2.

具体的には第2図に示すようにセグメント発生器SGC
は可変コンデンサ01〜C3からなり、ステップ発生器
STGは可変抵抗R1,R2からなる。またコンデンサ
01〜C3は各々複数個のコンデンサと、デジタル入力
信号DSにより開閉されてそれを挿脱するスイッチとか
らなる。デジタル信号SD2によりスイッチが開閉され
てコンデンサC1,C2の値が変ると、これらによる基
準電圧Vrefの分割電位が変り、こうして上記電圧A
が出力される。可変抵抗R1,R2は多数の直列抵抗と
、それらの直列接続点と出力端との間に配設されデジタ
ル入力信号によりオンオフされるスイソヂ群からなり、
入力信号DS2により該スイッチをオンオフして基準電
圧Vrefの分割電圧B′を出力する。この電圧B′は
セグメント順位r (t−t+ 2・・・・・・8)に
は無関係な、信号DS2の下位ビットにより定まる電圧
であるが、第3図に示されるように各セグメントの傾斜
は異なり、従って所要ステップ電圧はセグメント順位に
応じて変るべきである。この修正はコンデンサC3が行
なう。このコンデンサC3の挿脱用スイッチ群も入力信
号DS2の上位ビットによりオンオフされ、該コンデン
サの容量を変えて電圧Aに加算される上記電圧B′をB
に修正する。
Specifically, as shown in Fig. 2, the segment generator SGC
consists of variable capacitors 01 to C3, and step generator STG consists of variable resistors R1 and R2. Each of the capacitors 01 to C3 includes a plurality of capacitors and a switch that is opened and closed by the digital input signal DS to insert and remove the capacitors. When the switch is opened and closed by the digital signal SD2 and the values of the capacitors C1 and C2 change, the divided potential of the reference voltage Vref by these changes, and thus the voltage A
is output. The variable resistors R1 and R2 consist of a large number of series resistors and a switchgear group arranged between their series connection point and the output end and turned on and off by a digital input signal.
The switch is turned on and off by the input signal DS2 to output a divided voltage B' of the reference voltage Vref. This voltage B' is a voltage determined by the lower bit of the signal DS2, which is unrelated to the segment order r (t-t+ 2...8), but is determined by the slope of each segment as shown in FIG. are different, and therefore the required step voltage should vary depending on the segment order. Capacitor C3 performs this correction. The switch group for inserting and removing the capacitor C3 is also turned on and off by the upper bits of the input signal DS2, changing the capacitance of the capacitor and controlling the voltage B' added to the voltage A.
Correct it to

PCM伝送に用いられるコーグは第4図に示すようにコ
ンパレータCOMPと逐次比較レジスタSCRと、局部
デコーダDECからなる。この局部デコーダDECは上
述のデコーダと同じ構造である。第5図に示す如き値の
入力信号As+’がコンパレータCOMPに入力すると
、デコーダDECは最初Ov二出出力ているので該コン
パレークはHレベル出 を生じ、レジスタSCRはこれ
を受けてフルスケールFの1/2の電圧を指令する8ビ
ットデジタル信号DS+をデコーダDECへ出力する。
As shown in FIG. 4, the COG used for PCM transmission consists of a comparator COMP, a successive approximation register SCR, and a local decoder DEC. This local decoder DEC has the same structure as the decoder described above. When an input signal As+' having a value as shown in FIG. 5 is input to the comparator COMP, the decoder DEC outputs Ov2 at first, so the comparator outputs an H level, and the register SCR receives this and outputs the full scale F. An 8-bit digital signal DS+ commanding 1/2 voltage is output to the decoder DEC.

従ってデコーダDECは0.5Fの電圧をコンパレータ
COMPへ出力し、0.5F>AS+であるからコンパ
レータの出力はLレベルになる。
Therefore, the decoder DEC outputs a voltage of 0.5F to the comparator COMP, and since 0.5F>AS+, the output of the comparator becomes L level.

これを受b)でレジスタSCRは0.5 Fの1/2の
電圧を指令するデジタル信号DS+を出力し、デコーダ
D 、E Cの出力は0.25 Fとなる。これはAS
lより低いのでコンパレータ出力はHレベルとなり、こ
れを受けてレジスタは0.25 F + 0.25F/
2の電圧を指令する出力を生じる。以下同様であり、こ
うしてデコーダ出力は入力アナログ電圧AS+に限りな
く接近し、そしてその間の各比較結果のH,L (1,
0)はアナログ信号AS+のデジタルコードを示してい
るから、これが入力信号のコード化出力となる。
In response to this (b), the register SCR outputs a digital signal DS+ commanding a voltage of 1/2 of 0.5 F, and the outputs of the decoders D and E C become 0.25 F. This is AS
Since it is lower than l, the comparator output becomes H level, and in response, the register changes to 0.25F + 0.25F/
produces an output commanding a voltage of 2. Similarly, the decoder output approaches the input analog voltage AS+ as much as possible, and the H, L (1,
Since 0) indicates the digital code of the analog signal AS+, this is the coded output of the input signal.

信号の圧伸にはA側(A Law )とμ則(μ La
w)がある。これらも勿論周知のことであるが、簡単に
説明するとA側では第6図fa)に示すようにフルスケ
ールFを1/2.1/4.1/、8・・・・・・にして
セグメントSe、St、36・旧・・slとする。また
μ則では最小セグメントs1の2倍をセグメントS2、
その2倍をセグメントs3、以下同様にしてセグメント
SBを作り、S + +S 2+・・・・・・+Seが
フルスケールFとなる。またその1セグメントの分割方
法も、A側とμ則では異なる。即ちA側では同図(C)
に示すように全体を32分割し、コーグの場合は2/3
2./4/32. 6/32・・・・・・の点をまたデ
コーダの場合はl/32.3/32.5/’32・・・
・・・の点を各ステップとする。μ則の場合は同図(d
lに示すように1セグメントを33分割し、コーグの場
合はl/33.3/33・旧・・の点をまたデコーダの
場合は0/33.2/33゜4/33・・・・・・の点
を各ステップとする。前記のステップ発生器STGはこ
れらの各ステップ電圧を出力するものである。以上を一
括して表1に示すと次の如くなる。
For signal companding, A side (A Law) and μ law (μ La
There is w). These are of course well-known, but to briefly explain, on the A side, the full scale F is set to 1/2.1/4.1/, 8, etc. as shown in Figure 6 fa). Segments Se, St, 36 old...sl. Also, according to the μ law, the segment S2 is twice the minimum segment s1,
Segment s3 is twice that, and segment SB is created in the same manner, and S + +S 2+ . . . +Se becomes full scale F. The method of dividing one segment is also different between the A side and the μ law. In other words, on the A side, the same figure (C)
The whole is divided into 32 parts as shown in the figure, and in the case of Korg it is 2/3.
2. /4/32. In the case of a decoder, the point 6/32... is 1/32.3/32.5/'32...
. . . is defined as each step. In the case of μ law, the same figure (d
One segment is divided into 33 as shown in l, and in the case of Korg, the point is l/33.3/33, old..., and in the case of decoder, it is 0/33.2/33°4/33... Let the point . . . be each step. The step generator STG described above outputs each of these step voltages. The above is summarized in Table 1 as follows.

表 1 コーグ デコーダ ところでか−るコーグ、デコーダのステップ発生器ST
Gは従来はA則用、μ則用と各々専用に作られ、共用さ
れることはなかった。しかしステップ発生器も現在はL
SI化されているが、集積回路は量産してコストダウン
が可能であるからなるべく汎用品として共通に製作し、
生産規模を上げるのが好ましい。
Table 1 Korg decoder By the way, Korg decoder step generator ST
Conventionally, G was created exclusively for the A-law and the μ-law, and was never shared. However, the step generator is also currently L
Although integrated circuits are integrated, they can be mass-produced to reduce costs, so they should be commonly manufactured as general-purpose products as much as possible.
It is preferable to increase the scale of production.

A 1111 、μ則両用ステップ発生器は1セグメン
トの分割数は上記表から明らかなように最大33である
から33個の抵抗を用い、これらを直列にして基準電圧
を加えればその各直列接続点からμ則の各ステップ電圧
が得られ、抵抗1個を除去して32個とすればその各直
列接続点からA則の各ステップ電圧が得られる。しかし
これでは33個の抵抗を用いて16111i1のステッ
プ電圧を得ているに過ぎず、抵抗数が多いから面積を多
く必要とし、ばら1きがあるので各抵抗値の相対精度を
上げにく\、歩留りを高めにくいという問題がある。
A 1111, the μ-law dual-use step generator uses 33 resistors because the number of divisions of one segment is 33 at maximum as is clear from the table above, and if they are connected in series and a reference voltage is applied, each series connection point If one resistor is removed to make 32 resistors, each step voltage of A-law can be obtained from each series connection point. However, this only uses 33 resistors to obtain a step voltage of 16111i1, and since there are many resistors, a large area is required, and there is variation, making it difficult to increase the relative accuracy of each resistance value. , there is a problem that it is difficult to increase the yield.

そこで本発明はタップ数の16個程度の可及的に少ない
抵抗でステップ発生器を構成し、上記欠点を除去しよう
とするものであり、その特徴とする所は、セグメントの
端点電位を発生するセグメント発生器と該セグメントの
両端点間の分割電位を発生ずるステップ発生器からなる
圧伸デコーダの該ステップ発生器において、電源端子と
アース端子との間に、同じ抵抗値の電源側付加抵抗とn
個(nは自然数)の抵抗を直列に接続してなる直列抵抗
群と、前記電源側付加抵抗と同し抵抗値のアース側付加
抵抗とを直列に接続し、前記電源側付加抵抗に該電源側
(す加抵抗と同し抵抗値の別の電源側付加抵抗を第1の
モード切替スイッチを介して並列に接続し、前記アース
側イ1加抵抗に該アース側(;J加抵抗と同じ抵抗値の
別のアース側(=J加低抵抗第2のモード切替スイッチ
を介して並列に接続し、前記直列抵抗群の各直列接続点
及びアースと共通出力端子との間に、ディジタル信号に
よってオンオフされる(n + 2)個の出カスイッチ
群を設け、μ則指定信号により、前記第1のモード切替
スイッチを通雷ばオン、ピットスティール時はオフ、前
記第2のモード切替スイッチを通電はオフ、ピットステ
ィール時はオンにし、またA則指定信号により、前記第
1のモード切替スイッチをオン、前記第2のモード切替
スイッチをオンにするようにしてなる点にある。次に実
施例を参照しながらこれを詳細に説明する。
Therefore, the present invention attempts to eliminate the above drawbacks by configuring a step generator with as few resistors as possible, about 16 taps.The present invention is characterized by generating the end point potential of the segment. In the step generator of the companding decoder, which is composed of a segment generator and a step generator that generates a divided potential between both end points of the segment, an additional resistor on the power supply side with the same resistance value is connected between the power terminal and the ground terminal. n
A series resistance group formed by connecting resistors in series (n is a natural number) and a ground side additional resistor having the same resistance value as the power source side additional resistor are connected in series, and the power source side additional resistor is connected to the power source side additional resistor. Connect another power supply side additional resistor with the same resistance value as the ground side resistor in parallel via the first mode selector switch, and connect the ground side A1 resistor to the ground side (; Another ground side of the resistance value (=J) is connected in parallel via a second mode selector switch, and a digital signal is connected between each series connection point of the series resistance group and between the ground and the common output terminal. A group of (n + 2) output switches that are turned on and off is provided, and according to the μ-law designation signal, the first mode changeover switch is turned on when the lightning is turned on, turned off during pit steal, and the second mode changeover switch is turned on. The energization is turned off and turned on during pit steal, and the first mode changeover switch is turned on and the second mode changeover switch is turned on by the A-law designation signal. This will be explained in detail with reference to an example.

第7図はA/μコンパチブル ステップ発生器のコーグ
用の接続を示し、第8図は本発明の実施例を示し、同発
生器のデコーダ用の接続を示す。
FIG. 7 shows the connections for the cog of an A/μ compatible step generator, and FIG. 8 shows an embodiment of the invention and shows the connections for the decoder of the same generator.

第7図のコーグ用の場合もまた第8図のデコーダ用の場
合も同し抵抗値Rの抵抗(やはりR又はR+。
Both the case for the Korg in FIG. 7 and the case for the decoder in FIG. 8 are the same resistors with a resistance value R (also R or R+).

R2・・・・・・Rnで示す)を本実施例では15本直
列に接続し、その両端に、コーグの場合はやはり抵抗値
Rの抵抗10および12と14を直列接続し、デコーダ
の場合は抵抗値Rの抵抗10と16および12と14を
直列接続する。従ってコーダ、デコーダ両用にするには
抵抗としては第8図の構成をとっておけばよい。15本
の直列抵抗Rの各直列接点と出力端子20との間には出
力スイッチSWl、SW2・・・・・・SW、6を接続
する。またこの直列抵抗群の両端の付加抵抗には、コー
グの場合抵抗10を短絡するモード切換スイッチS20
と抵抗12を切離するモード切換スイッチS22を、ま
たデコーダの場合抵抗16を切離するモード切換スイッ
チ324と上記スイッチS22と、出力端20をアース
するスイッチS W aを設ける。そしてコーダ、デコ
ーダとも両端付加抵抗の一方は切換スイッチS26を介
して、正、負基準電圧源±V refへ接続し、他端ば
アースする。コーグ。
In this embodiment, 15 resistors (represented by R2...Rn) are connected in series, and in the case of a Korg, resistors 10, 12, and 14, each having a resistance value R, are connected in series at both ends. connects resistors 10 and 16 and 12 and 14 of resistance value R in series. Therefore, if the resistor is to be used as both a coder and a decoder, it is sufficient to use the configuration shown in FIG. 8 as the resistor. Output switches SW1, SW2, . . . , SW, 6 are connected between each series contact of the 15 series resistors R and the output terminal 20. In addition, the additional resistors at both ends of this series resistor group include a mode changeover switch S20 that short-circuits the resistor 10 in the case of Korg.
In the case of a decoder, a mode changeover switch 324 which disconnects the resistor 16, a mode changeover switch S22 which disconnects the resistor 12, the switch S22, and a switch S W a which grounds the output terminal 20 are provided. In both the coder and the decoder, one end of the additional resistor is connected to the positive and negative reference voltage sources ±V ref via the changeover switch S26, and the other end is grounded. Coorg.

デコーダ両用の場合スイッチについてはこれらのスイッ
チS20.322.324.326 、SW。
For dual-use decoder switches, these switches S20.322.324.326, SW.

をすべて設けておけばよい。All you have to do is set them up.

このようなステップ発生器によれば、スイッチを次表2
に示すように操作することにより前記表1に示したすべ
てのステップ電圧を発生すること表 2 コーグ μ則 S22オン S20オフA則 S22オ
フ 320オン デターダ μ則 S22オフ 324オンμ則 322
オン 324オフ (bit 5teal) A則 S22オン 324オン 即ち、μ則コーダの場合に、スイッチ322を閉しると
抵抗12と14が並列になるからその合成抵抗はR/2
となり、これが15個直列接続抵抗群RGのアース側付
加抵抗となり、またスイッチ520を開くと抵抗値Rの
抵抗10が抵抗群RGの電源側イ」加抵抗となり、スイ
ッチSW1.SW2゜S W 3・・・・・・で取出さ
れる電圧はVref・/ (+16R) =Vrei 
−2233 Vrei (−+R) / (+16R) =νref
 ・−2233 Vref・(+2R) / (+16R) −Vref
・−2233 となり、これらは表1のμ則コーダのステップ電圧に他
ならない。A則コーダの場合はスイッチS22を開くか
ら抵抗12が切離されて抵抗群RGのアース側付加抵抗
は抵抗値Rの抵抗14となり、またスイッチS20がオ
ンとなって抵抗10が短絡されるから抵抗群RGの電源
側は(す加抵抗は零となる。この場合スイッチSWI、
SW2゜SW3・・・・・・で取出される電圧はとなり
、これらは表1のA則コーダのステップ電圧に他ならな
い。説明は省略するが、デコーダの場合も同様である。
According to such a step generator, the switch can be set as shown in Table 2 below.
All the step voltages shown in Table 1 are generated by operating as shown in Table 2. Korg μ law S22 ON S20 OFF A law S22 OFF 320 ON Deterder μ law S22 OFF 324 ON μ law 322
ON 324 OFF (bit 5teal) A-law S22 ON 324-ON In other words, in the case of μ-law coder, when switch 322 is closed, resistors 12 and 14 become parallel, so their combined resistance is R/2
This becomes the additional resistance on the ground side of the 15 series-connected resistor group RG, and when the switch 520 is opened, the resistor 10 with the resistance value R becomes the additional resistance on the power supply side of the resistor group RG, and the switches SW1. The voltage taken out by SW2゜SW3... is Vref・/ (+16R) =Vrei
-2233 Vrei (-+R) / (+16R) = νref
・-2233 Vref・(+2R) / (+16R) -Vref
-2233, and these are nothing but the step voltages of the μ-law coder in Table 1. In the case of the A-law coder, the switch S22 is opened, so the resistor 12 is disconnected, and the additional resistor on the ground side of the resistor group RG becomes the resistor 14 with the resistance value R. Also, the switch S20 is turned on, and the resistor 10 is short-circuited. On the power supply side of resistor group RG (additional resistance is zero. In this case, switch SWI,
The voltages taken out by SW2, SW3, . . . are as follows, and these are nothing but the step voltages of the A-law coder in Table 1. Although the explanation is omitted, the same applies to the decoder.

スイッチSWo、SW+。Switch SWo, SW+.

SW2・・・・・・5w16は前述のデジタル信号DS
2の下位ビットでオンオフし、スイッチS20 。
SW2...5w16 is the digital signal DS mentioned above.
Switch S20 is turned on and off by the lower bit of 2.

S22.S24はA、μ則およびコーグ、デコーダ指定
信号でオンオフする。スイッチ326はステップ発生器
が発生すべきステップ電圧が正か負かに応して正電fB
 + Vref、貫電、源−Vrefに切換わる。この
切換えはデジタル信号DS2に付加される極性指定ビッ
トで行なわれる。
S22. S24 is turned on and off by A, μ law, Korg, and decoder designation signals. The switch 326 selects a positive voltage fB depending on whether the step voltage to be generated by the step generator is positive or negative.
+Vref, through current, switched to source -Vref. This switching is performed by a polarity designation bit added to the digital signal DS2.

以上詳細に説明したように本発明によれば抵抗群および
スイッチ群からなるステップ発生器を汎用LSIとして
量産しておき、コーグ、デコーダ、A則、μ則を指定す
る外部信号によりスイッチをオンオフして各々に対応し
たステップ発生器とすることができるので量産、従って
コストダウンが可能であり、また使用抵抗数はステップ
数プラス付加抵抗4個の可及的少数であるので小型化、
高精度化等の点で極めて有利である。
As explained in detail above, according to the present invention, a step generator consisting of a group of resistors and a group of switches is mass-produced as a general-purpose LSI, and the switches are turned on and off by external signals specifying the Cog, decoder, A-law, and μ-law. Since step generators corresponding to each type can be made, mass production is possible, and therefore costs can be reduced.Also, the number of resistors used is as small as possible (the number of steps plus four additional resistors), so miniaturization is possible.
This is extremely advantageous in terms of high precision, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はPCM圧伸デコーダの構成説明図、第2図はそ
のハードウェアの概要を示す回路図、第3図は圧伸状態
等の説明用グラフ、第4図はpcM圧伸コーコー構成概
要を説明するブロック図、第5図はコーグの動作説明用
グラフ、第6図+a)〜(dlはセグメントおよびステ
ップの説明図、第7図はコーグ用の接続を示す回路図、
そして第8図ば本発明の実施例を示す回路図である。 図面でSGGはセグメント発生器、STGはステップ発
生器、DECはデコーダ、CODはコーグ、RGは直列
抵抗群、10,16,12.14は付加抵抗、S20 
、 S22 、 、S24はモード切換スイッチ、SW
n、SW+・・・・・・は出カスイッチである。 出願人 富士通株式会社 代理人弁理士 青 柳 稔 第2図 第3図 SGG STC,”” 入力
Figure 1 is an explanatory diagram of the configuration of the PCM companding decoder, Figure 2 is a circuit diagram showing an overview of its hardware, Figure 3 is a graph for explaining the companding state, etc., and Figure 4 is an overview of the pcM companding decoder configuration. 5 is a graph for explaining the operation of Korg, FIG. 6 +a) to (dl is an explanatory diagram of segments and steps, FIG. 7 is a circuit diagram showing connections for Korg,
FIG. 8 is a circuit diagram showing an embodiment of the present invention. In the drawing, SGG is a segment generator, STG is a step generator, DEC is a decoder, COD is a Korg, RG is a series resistor group, 10, 16, 12.14 are additional resistors, and S20
, S22, , S24 are mode changeover switches, SW
n, SW+... are output switches. Applicant Fujitsu Ltd. Representative Patent Attorney Minoru Aoyagi Figure 2 Figure 3 SGG STC, "" Input

Claims (1)

【特許請求の範囲】[Claims] セグメントの端点電位を発生するセグメント発生器と該
セグメントの両端点間の分割電位を発生するステップ発
生器からなる圧伸デコーダの該ステップ発生器において
、電源端子とアース端子との間に、同し抵抗値の電源側
付加抵抗(10)とn個(nは自然数)の抵抗を直列に
接続してなる直列抵抗群(R+〜Rn)と、前記電源側
付加抵抗と同じ抵抗値のアース側付加抵抗(14)とを
直列に接続し、前記電源側付加抵抗に該電源側付加抵抗
と同じ抵抗値の別の電源側付加抵抗(16)を第1のモ
ード切替スイッチ(S24)を介して並列に接続し、前
記アース側イχJ加抵抗に該アース側付加抵抗と同じ抵
抗値の別のアース側付力吋氏抗(12)を第2のモード
切替スイッチ(S22)を介して並列に接続し、前記直
列抵抗群の各直列接続点及びアースと共通出力端子との
間に、ディジタル信号によってオンオフされる(n+2
)個の出力スイッチ群(SWo”SW 16 )を設け
、μ則指定信号により、前記第1のモード切替スイッチ
を通常はオン、ピットスティール時はオフ、前記第2の
モード切替スイッチを通常はオフ、ピットスティール時
はオンにし、またA則指定信号により、前記第1のモー
ド切替スイッチをオン、前記第2のモード切替スイッチ
をオンにすることを特徴とするステップ発生器。
In the step generator of the companding decoder, which is composed of a segment generator that generates an end point potential of a segment and a step generator that generates a divided potential between both end points of the segment, the same voltage is connected between the power terminal and the ground terminal. A series resistance group (R+ to Rn) formed by connecting an additional resistance on the power supply side (10) in series with n resistors (n is a natural number), and an additional resistance on the earth side with the same resistance value as the additional resistance on the power supply side. A resistor (14) is connected in series, and another power supply side additional resistor (16) having the same resistance value as the power supply side additional resistor is connected in parallel with the power supply side additional resistor via a first mode changeover switch (S24). , and connect another ground side resistor (12) having the same resistance value as the ground side additional resistor to the ground side additional resistor (12) in parallel via the second mode changeover switch (S22). A signal (n+2
) output switch groups (SWo"SW 16 ) are provided, and according to the μ-law designation signal, the first mode selector switch is normally on, off during pit steal, and the second mode selector switch is normally off. , the step generator is turned on during a pit steal, and the first mode changeover switch is turned on and the second mode changeover switch is turned on in response to an A-law designation signal.
JP6025685A 1985-03-25 1985-03-25 Step generator Granted JPS60216630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6025685A JPS60216630A (en) 1985-03-25 1985-03-25 Step generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6025685A JPS60216630A (en) 1985-03-25 1985-03-25 Step generator

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP3796379A Division JPS6059774B2 (en) 1979-03-30 1979-03-30 step generator

Publications (2)

Publication Number Publication Date
JPS60216630A true JPS60216630A (en) 1985-10-30
JPS613135B2 JPS613135B2 (en) 1986-01-30

Family

ID=13136905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6025685A Granted JPS60216630A (en) 1985-03-25 1985-03-25 Step generator

Country Status (1)

Country Link
JP (1) JPS60216630A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62249529A (en) * 1986-04-22 1987-10-30 Nec Corp Reference voltage generating circuit
FR2642587A1 (en) * 1989-01-31 1990-08-03 Jaeger Enhancements to devices effecting a shaping of frequency analog signals
FR2642585A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals
FR2642586A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals, exhibiting useful pulses of positive or negative polarity
FR2642588A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals, with high dynamic range

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03124937U (en) * 1990-03-30 1991-12-18

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62249529A (en) * 1986-04-22 1987-10-30 Nec Corp Reference voltage generating circuit
FR2642587A1 (en) * 1989-01-31 1990-08-03 Jaeger Enhancements to devices effecting a shaping of frequency analog signals
FR2642585A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals
FR2642586A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals, exhibiting useful pulses of positive or negative polarity
FR2642588A1 (en) * 1989-01-31 1990-08-03 Jaeger Device for shaping frequency analog signals, with high dynamic range

Also Published As

Publication number Publication date
JPS613135B2 (en) 1986-01-30

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