JPS6059774B2 - step generator - Google Patents

step generator

Info

Publication number
JPS6059774B2
JPS6059774B2 JP3796379A JP3796379A JPS6059774B2 JP S6059774 B2 JPS6059774 B2 JP S6059774B2 JP 3796379 A JP3796379 A JP 3796379A JP 3796379 A JP3796379 A JP 3796379A JP S6059774 B2 JPS6059774 B2 JP S6059774B2
Authority
JP
Japan
Prior art keywords
resistor
segment
turned
changeover switch
law
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP3796379A
Other languages
Japanese (ja)
Other versions
JPS55130228A (en
Inventor
道信 大畑
昌夫 山沢
俊彦 松村
久巳 田中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3796379A priority Critical patent/JPS6059774B2/en
Publication of JPS55130228A publication Critical patent/JPS55130228A/en
Publication of JPS6059774B2 publication Critical patent/JPS6059774B2/en
Expired legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Description

【発明の詳細な説明】 本発明は、PCMで用いられる圧伸コータ、デコーダ
のステップ発生器に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a step generator for a companding coater and decoder used in PCM.

PCM伝送てはアナログ信号をコード化して伝 送し
、受信側ではこれをコードして元のアナログ信号にする
In PCM transmission, an analog signal is encoded and transmitted, and on the receiving side, this is encoded and converted into the original analog signal.

これに用いられるデコーダは通常第1図に示すように、
セグメント発生器SGGとステップ発生器STGからな
り、前者は第3図に示すセグメント5i(i=1、2・
・・・・・8)の始点P、を示すアナログ電圧Aを発生
し、後者は該セグメントの始、終端P、、P2間を分割
した電圧Bを発生する。PCMではコード化に当り小振
幅部分の忠実度を上げるため該部分を拡大しているので
、符号化入力信号対復合出力信号の間には第3図に示す
如き飽和特性(8セグメント折れ線特性)がある。8ビ
ット入力信号DSが入ると制御回路CNTは、その上位
複数ビットをセグメント発生器SGGに与えて該複数ヒ
ットにより定められる順位のセグメントSiの始端電位
Aを発生させ、またその下位複数ビットをセグメント発
生器STGに与えて該複数ビットにより定められる分割
電位Bを発生させる。
The decoder used for this is usually as shown in Figure 1.
It consists of a segment generator SGG and a step generator STG, and the former is composed of a segment 5i (i=1, 2,
...8) An analog voltage A indicating the starting point P is generated, and the latter generates a voltage B divided between the starting point P, the ending point P, and P2 of the segment. In PCM, when encoding, the small amplitude part is enlarged to increase the fidelity, so there is a saturation characteristic (8 segment polygonal line characteristic) between the encoded input signal and the decoded output signal as shown in Figure 3. There is. When the 8-bit input signal DS is input, the control circuit CNT supplies the higher-order bits to the segment generator SGG to generate the starting end potential A of the segment Si in the order determined by the hits, and also outputs the lower-order bits to the segment generator SGG. The divided potential B is applied to a generator STG to generate a divided potential B defined by the plurality of bits.

これらは加算されてその和が出力アナログ信号AS2と
なる。1 具体的には第2図に示すようにセグメント発
生器SGGは可変コンデンサC、〜C。
These are added and the sum becomes the output analog signal AS2. 1. Specifically, as shown in FIG. 2, the segment generator SGG has variable capacitors C, ~C.

からなり、ステップ発生 TGは可変抵初只、、R。か
らなる。またコンデンサC1〜C3は各々複数個のコン
デンサと、ディジタル入力信号DSにより開閉されてそ
・れを挿脱するスイッチとからなる。ディジタル信号D
S2によりスイッチが開閉されてコンデンサCl,C2
の値が変ると、これらによる基準電圧■Refの分割電
位が変り、こうして上記電圧Aが出力される。可変抵抗
Rl,R2は多数の直列抵抗と、それらの直列接続点と
出力端との間に配設されデジタル入力信号によりオンオ
フされるスイッチ群からなり、入力信号DS2により該
スイッチをオンオフして基準電圧Vrefの分割電圧B
″を出力する。この電圧B″はセグメント順位置(1=
1,2・・・・・8)には無関係な、信号DS2の下位
ビットにより定まる電圧であるが、第3図に示されるよ
うに各セグメントの傾斜は異なり、従つて所要ステップ
電圧はセグメント順位に応じて変るべきである。この修
正はコンデンサC3が行なう。このコンデンサC3の挿
脱用スイッチ群−も入力信号DS2の上位ビットにより
オンオフされ、該コンデンサの容量を変えて電圧Aに加
算される上記電圧B″をBに修正する。PCM伝送に用
いられるコータは第4図に示すようにコンパレータCO
MPと逐次比較レジスSCRと、局部デコーダDECか
らなる。
The step generation TG is only a variable resistor, R. Consisting of Each of the capacitors C1 to C3 includes a plurality of capacitors and a switch that is opened and closed by a digital input signal DS to insert and remove the capacitors. digital signal D
The switch is opened and closed by S2, and the capacitors Cl and C2
When the value of is changed, the divided potential of the reference voltage Ref is changed, and thus the voltage A is outputted. The variable resistors Rl and R2 consist of a large number of series resistors and a group of switches that are arranged between their series connection point and the output end and are turned on and off by a digital input signal.The switches are turned on and off by an input signal DS2 and used as a reference. Divided voltage B of voltage Vref
This voltage B″ outputs segment order position (1=
1, 2...8) is determined by the lower bit of the signal DS2, but as shown in FIG. 3, the slope of each segment is different, so the required step voltage depends on the segment order. should change accordingly. Capacitor C3 performs this correction. The switch group for insertion and removal of this capacitor C3 is also turned on and off by the upper bit of the input signal DS2, and the capacitance of the capacitor is changed to correct the voltage B'' added to the voltage A to B.A coater used in PCM transmission is the comparator CO as shown in Figure 4.
It consists of MP, successive approximation register SCR, and local decoder DEC.

この局部デコーダDECは上述のデコーダと同じ構造で
ある。第5図に示す如き値の入力信号ASlがコンパレ
ータCOMPに入力すると、デコーダDECは最初0v
を出力しているので該コンパレータはHレベル出力を生
じ、レジスタSCRはこれを受けてフルスケールFの1
12の電圧を指令する8ビットデジタル信号DSlをデ
コーダDECへ出力する。従つてデコーダDECは0.
5F′の電圧をコンパレータCOMPへ出力し、0.5
F>ASlてあるからコンパレータの出力はLレベルに
なる。これを受けてレジ水*スタSCRは0.5F′の
112の電圧を指令するデジタル信号DSlを出力し、
デコーダDECの出力は0.25Fとなる。これはAS
lより低いのでコンパレータ出力はHレベルとなり、こ
れを受けてレジスタは0.25F′+0.25F′/2
の電圧を指令する出力を生じる。以下同様であり、こう
してデコーダ出力は入力アナログ電圧ASlに限りなく
接近し、そしてその間の各比較結果のH,L(1.0)
はアナログ信号ASlのデジタルコードを示しているか
ら、これが入力信号のコード化出力となる。信号の圧伸
にはA則(ALlw)とμ則(μLiw)がある。
This local decoder DEC has the same structure as the decoder described above. When an input signal ASl having a value as shown in FIG. 5 is input to the comparator COMP, the decoder DEC initially outputs 0v
Therefore, the comparator generates an H level output, and in response to this, the register SCR outputs 1 of full scale F.
An 8-bit digital signal DSl commanding 12 voltages is output to the decoder DEC. Therefore, the decoder DEC is 0.
The voltage of 5F' is output to the comparator COMP, and the voltage of 0.5
Since F>ASl, the output of the comparator becomes L level. In response to this, the register water * star SCR outputs a digital signal DSl that commands a voltage of 112 of 0.5F'.
The output of the decoder DEC becomes 0.25F. This is AS
Since it is lower than l, the comparator output becomes H level, and in response, the register changes to 0.25F'+0.25F'/2
produces an output that commands the voltage of The same goes for the following, and in this way the decoder output approaches the input analog voltage ASl as much as possible, and the H, L (1.0) of each comparison result between them
represents the digital code of the analog signal ASl, so this is the coded output of the input signal. There are A-law (ALlw) and μ-law (μLiw) for signal companding.

これらも勿論周知のことであるが、簡単に説明するとA
則では第6図aに示すようにフルスケールFを112,
114,1ノ8・・・・・・にしてセグメントS8,S
7,S6・・・・・・S1とする。またμ則では最小セ
グメントS1の2倍をセグメントS2、その2倍をセグ
メントS3、以下同様にしてセグメントS8を作り、S
1+S2+・・・・・・S8がフルスケールFとなる。
またその1セグメントの分割方法も、A則とμ則では異
なる。即ちA則では同図cに示すように全体を32分割
し、コータの場合は2132,4132,6132・・
・・・・の点をまたデコーダの場合は1132,313
2,5132・・・・・・の点を各ステップとする。μ
則の場合は同図dに示すように1セグメントを3紛割し
、コータの場合は1133,313& ・・・・の点を
またデコーダの場合は0133,2133,4133・
・・・・・の点を各ステップとする。前記のステップ発
生器STGはこれらの各ステップ電圧を出力するもので
ある。以上を一括して表1に示すと次の如くなる。とこ
ろでか)るコータ、デコーダのステップ発生器STGは
従来はA則用μ則用と各々専用に作られ、共用されるこ
とはなかつた。しかしステップ発生器も現在はLSI化
されているが、集積回路は量産してコストダウンが可能
であるからなるべく汎用品として共通に製作し、生産規
模を上げるのが好ましい。A則,μ則両用ステップ発生
器は1セグメントの分割数は上記表から明らかなように
最大33であるから33個の抵抗を用い、これらを直列
にして基準電圧を加えれはその各直列接続点からμ則の
各ステップ電圧が得られ、抵抗1個を除去して32個と
すればその各直列接続点からA則の各ステップ電圧か得
られる。
These are, of course, well-known, but to briefly explain A.
According to the rule, the full scale F is 112, as shown in Figure 6a.
114,1 no 8... and segment S8,S
7, S6...S1. Also, according to the μ law, twice the minimum segment S1 is made into segment S2, twice that is made into segment S3, and so on, segment S8 is made in the same manner, and S
1+S2+...S8 becomes full scale F.
Furthermore, the method of dividing one segment is also different between the A-law and the μ-law. In other words, according to rule A, the whole is divided into 32 parts as shown in c in the same figure, and in the case of a coater, 2132, 4132, 6132, etc.
In the case of a decoder, the points of ... are 1132, 313
2,5132... points are each step. μ
In the case of the rule, one segment is divided into three as shown in figure d, and in the case of the coater, the points are 1133, 313 &..., and in the case of the decoder, the points are 0133, 2133, 4133, etc.
Each step is defined as a point. The step generator STG described above outputs each of these step voltages. The above is summarized in Table 1 as follows. By the way, the step generator STG of the coater and decoder has heretofore been made exclusively for the A-law and the μ-law, respectively, and has not been shared. However, although step generators are currently implemented as LSIs, integrated circuits can be mass-produced to reduce costs, so it is preferable to commonly manufacture them as general-purpose products to increase the scale of production. In the step generator for both A-law and μ-law, the maximum number of divisions of one segment is 33 as shown in the table above, so 33 resistors are used, and by connecting them in series and applying a reference voltage, each series connection point is used. If one resistor is removed to make 32 resistors, each step voltage of the A-law can be obtained from each series connection point.

しかしこれでは3鍮の抵抗を用いて1帽のステップ電圧
を得ているに過ぎず、抵抗数が多いから面積を多く必要
とし、ばらつきがあるので各抵抗値の相対精度を上げに
く)、歩留りを高めにくいという問題がある。そこて本
発明はタップ数の托個程度の可及的に少ない抵抗でステ
ップ発生器を構成し、上記欠点を除去しようとするもの
てあり、その特徴とする所はセグメントの端点電位を発
生するセグメント発生器と該セグメントの両端点間の分
割電位を発生するステップ発生器からなる圧伸コータの
該ステップ発生器において、電源端子とアース端子との
間に、同に抵抗値の電源側付加抵抗とn個(n自然数)
の抵抗を直列に接続して直列抵抗群と、前記電源側付加
抵抗と同じ抵抗値のアース側付加抵抗とを直列に接続し
、前記電源側付加抵抗に第1のモード切替スイッチを並
列に接続し、前記アース側付加抵抗に該アース側付加抵
抗と同じ抵抗値の別のアース側付加抵抗を第2のモード
切替スイッチを介して並列に接続し、前記直列抵抗群の
各直列接続点と共通出力端子との間に、デジタル信号に
よつてオンオフされる(n+1)個の出力スイッチ群を
設け、μ則指定信号により、前記第1のモード切替スイ
ッチをオフ、前記第2のモード切替スイッチをオンにし
、A則指定信号により、前記第1のモード切替スイッチ
をオン、前記第2のモード切替スイッチをオフにするよ
うにした点にある。
However, in this case, only one step voltage is obtained using three brass resistors, and since there are many resistors, a large area is required, and since there are variations, it is difficult to increase the relative accuracy of each resistance value). There is a problem that it is difficult to increase the yield. Therefore, the present invention attempts to eliminate the above drawbacks by configuring a step generator with as few resistors as possible, about the number of taps.The present invention is characterized by generating an end point potential of a segment. In the step generator of the companding coater, which is composed of a segment generator and a step generator that generates a divided potential between both end points of the segment, an additional resistor on the power supply side with the same resistance value is connected between the power terminal and the ground terminal. and n pieces (n natural numbers)
A series resistor group is connected in series with a ground-side additional resistor having the same resistance value as the power-supply-side additional resistor, and a first mode selector switch is connected in parallel to the power-supply-side additional resistor. Then, another ground-side additional resistor having the same resistance value as the ground-side additional resistor is connected in parallel to the ground-side additional resistor via a second mode selector switch, and is common to each series connection point of the series resistor group. A group of (n+1) output switches that are turned on and off by a digital signal are provided between the output terminal and the first mode changeover switch is turned off and the second mode changeover switch is turned off by a μ law designation signal. The first mode changeover switch is turned on and the second mode changeover switch is turned off by the A-law designation signal.

次に実施例を参照しながらこれを詳細に説明する。第7
図は本発明に係るA/μコンパチブルステツプ発生器の
コータ用の接続を示し、第8図は同発生器のデコーダの
接続を示す。
Next, this will be explained in detail with reference to examples. 7th
The figure shows the connections for the coater of the A/μ compatible step generator according to the invention, and FIG. 8 shows the connections for the decoder of the same generator.

第7図のコータ用の場合もまた第8図のデコーダ用の場
合も同じ抵抗値Rの抵抗(やはりRで又はRl,R2・
・・・・・Rnで示す)を本実施例では15本直列に接
続し、その両端に、コータの場合はやはり抵抗値Rの抵
抗10および12と14を直列接続し、デコーダの場合
は抵抗値Rの抵抗10と16および12と14を直列接
続する。従つてコータ、デコーダ両用にするには抵抗と
しては第8図の構成をとつておけはよい。15本の直列
抵抗Rの各直列接点と出力端子20との間には出力スイ
ッチSWl,SW2・・・SWl6を接続する。
In the case of the coater in FIG. 7 and in the case of the decoder in FIG.
In this embodiment, 15 resistors (indicated by Rn) are connected in series, and in the case of a coater, resistors 10, 12, and 14 with a resistance value R are connected in series, and in the case of a decoder, resistors 10, 12, and 14 with a resistance value R are connected in series. Resistors 10 and 16 and 12 and 14 of value R are connected in series. Therefore, in order to use the resistor as both a coater and a decoder, it is better to use the configuration shown in FIG. 8 as the resistor. Output switches SWl, SW2 . . . SWl6 are connected between each series contact of the 15 series resistors R and the output terminal 20.

またこの直列抵抗群の両端の付加抵抗には、コータの場
合抵抗10を短絡するモード切換スイッチS2Oと抵抗
12を切離するモード切換スイッチS22を、またデコ
ーダの場合抵抗16を切離するモード切換スイッチS2
4と上記スイッチS2。と、出力端20をアースするス
イッチSWOを設ける。そしてコータ、デコーダとも両
端付加抵抗の一方は切換スイツチジを介して、正,負基
準電圧源士Vrefへ接続し、他端はアースする。コー
タ、デコーダ両用の場合スイッチについてはこれらのス
イッチS2O9S229S249S269SWOをすべ
て設けておけばよい。このようなステップ発生器によれ
ば、スイッチを次表2に示すように操作することにより
前記表1に示したすべてのステップ電圧を発生すること
ができる。
In addition, the additional resistors at both ends of this series resistor group include a mode changeover switch S2O that short-circuits the resistor 10 and a mode changeover switch S22 that disconnects the resistor 12 in the case of a coater, and a mode changeover switch S22 that disconnects the resistor 16 in the case of a decoder. switch S2
4 and the above switch S2. and a switch SWO that grounds the output end 20. One end of the additional resistor at both ends of both the coater and decoder is connected to the positive and negative reference voltage sources Vref via a changeover switch, and the other end is grounded. In the case of dual use as a coater and a decoder, all of these switches S2O9S229S249S269SWO may be provided. According to such a step generator, all the step voltages shown in Table 1 can be generated by operating the switches as shown in Table 2 below.

即ち、μ則コータの場合に、スイッチS22を閉じると
抵抗12と14が並列になるからその合成抵抗R/2と
なり、これが15個直列接続抵抗群RGのアース側付加
抵抗となり、またスイッチS2Oを開くと抵抗値Rの抵
抗10が抵抗群RGの電源側付加抵抗となり、スイッチ
SWl,SW2,SW3・・・・・て取出される電圧は
となり、これらは表1のμ則コータのステップ電圧に他
ならない。
That is, in the case of a μ-law coater, when switch S22 is closed, resistors 12 and 14 are placed in parallel, resulting in a combined resistance R/2, which becomes the additional resistance on the ground side of the 15 series-connected resistor group RG. When opened, the resistor 10 with resistance value R becomes an additional resistor on the power supply side of the resistor group RG, and the voltage taken out by the switches SWl, SW2, SW3, etc. is, and these are the step voltages of the μ-law coater in Table 1. None other than that.

A則コータの場合はスイツチジを開くから抵抗12が切
離されて抵抗群RGのアース側付加抵抗は抵抗値Rの抵
抗14となり、またスイッチS2Oがオンとなつて抵抗
10が短絡されるから抵抗群RGの電源側は付加抵抗は
零となる。この場合スイッチSWl,SW2,SW3・
・・・・・で取出される電圧はとなり、これらは表1の
A則コータのステップ電圧に他ならない。
In the case of an A-law coater, since the switch is opened, the resistor 12 is disconnected, and the additional resistor on the ground side of the resistor group RG becomes the resistor 14 with a resistance value R. Also, the switch S2O is turned on, and the resistor 10 is short-circuited, so the resistor 12 is disconnected. The additional resistance on the power supply side of group RG is zero. In this case, switches SWl, SW2, SW3・
The voltages taken out in ... are the step voltages of the A-law coater in Table 1.

説明は省略するが、デコーダの場合も同様てある。スイ
ッチSWO,SWl,SW2・・・・SW,6は前述の
デジタル信号DS2の下位ビットでオンオフし、スイッ
チS2O,S22,S24はA,μ則.およびコータ,
デコーダ指定信号でオンオフする。スイッチS26はス
テップ発生器が発生すべきステップ電圧が正か負かに応
じて正電源十Vref、負電源−Vrefに切換わる。
Although the explanation is omitted, the same applies to the decoder. The switches SWO, SWl, SW2, . and coater,
Turns on/off with decoder specified signal. The switch S26 is switched between the positive power source +Vref and the negative power source -Vref depending on whether the step voltage to be generated by the step generator is positive or negative.

この切換えはデジタル信号DS2に付加される極性指定
ビットで行なわれる。以上詳細に説明したように本発明
によれば抵抗群およびスイッチ群からなるステップ発生
器を汎用LS■として量産しておき、コータ,デコーダ
、ノA則,μ則を指定する外部信号によりスイッチをオ
ンオフして各々に対応したステップ発生器とすることが
できるので量産、従つてコストダウンが可能てあり、ま
た使用抵抗数はステップ数プラス付加抵抗4個の可及的
少数であるのて小型化、高精度化等の点で極めて有利て
ある。
This switching is performed by a polarity designation bit added to the digital signal DS2. As explained in detail above, according to the present invention, a step generator consisting of a group of resistors and a group of switches is mass-produced as a general-purpose LS, and the switches are activated by external signals specifying the coater, decoder, A law, and μ law. Since a step generator corresponding to each can be turned on and off, it is possible to mass produce and reduce costs, and the number of resistors used is as small as possible (the number of steps plus four additional resistors), making it more compact. , it is extremely advantageous in terms of high precision, etc.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はPCM圧伸デコーダの構成説明図、第2図はそ
のハードウェアの概要を示す回路図、第3図は圧伸状態
等の説明用グラフ、第4図はPCM圧伸コータの構成概
要を説明するブロック図、第5図はコータの動作説明用
グラフ、第6図a−dはセグメントおよびステップの説
明図、第7図は本発明の実施例を示す回路図、第8図は
デコーダとしての結線を示す回路図てある。 図面でSGGはセグメント発生器、STGはステップ発
生器、DECはデコーダ、CODはコータ、RGは直列
抵抗群、10,16,12,14は付加抵抗、S?f:
),S22,S24はモード切換スイッチ、SWO,S
Wl・・・・・・は出力スイッチである。
Fig. 1 is an explanatory diagram of the configuration of the PCM companding decoder, Fig. 2 is a circuit diagram showing an overview of its hardware, Fig. 3 is a graph for explaining the companding state, etc., and Fig. 4 is the configuration of the PCM companding coater. 5 is a graph for explaining the operation of the coater, FIG. 6 a to d is an explanatory diagram of segments and steps, FIG. 7 is a circuit diagram showing an embodiment of the present invention, and FIG. 8 is a graph for explaining the operation of the coater. This is a circuit diagram showing the wiring as a decoder. In the drawing, SGG is a segment generator, STG is a step generator, DEC is a decoder, COD is a coater, RG is a series resistor group, 10, 16, 12, 14 are additional resistors, S? f:
), S22, S24 are mode changeover switches, SWO, S
Wl... is an output switch.

Claims (1)

【特許請求の範囲】[Claims] 1 セグメントの端点電位を発生するセグメント発生器
と該セグメントの両端点間の分割電位を発生するステッ
プ発生器からなる圧伸コーダの該ステップ発生器におい
て、電源端子とアース端子との間に、同じ抵抗値の電源
側付加抵抗10とn個(nは自然数)の抵抗を直列に接
続してなる直列抵抗群(R_1〜R_n)と、前記電源
側付加抵抗と同じ抵抗値のアース側付加抵抗14とも直
列に接続し、前記電源側付加抵抗に第1のモード切替ス
イッチS_2_0を並列に接続し、前記アース側付加抵
抗に該アース側付加抵抗と同じ抵抗値の別のアース側付
加抵抗12を第2のモード切替スイッチS_2_2を介
して並列に接続し、前記直列抵抗群の各直列接続点と共
通出力端子との間に、ディジタル信号によつてオンオフ
される(n+1)個の出力スイッチ群SW_1〜SW_
1_6を設け、μ則指定信号により、前記第1のモード
切替スイッチをオフ、前記第2のモード切替スイッチを
オンにし、A則指定信号により、前記第1のモード切替
スイッチをオン、前記第2のモード切替スイッチをオフ
にすることを特徴とするステップ発生器。
1. In the step generator of a companding coder consisting of a segment generator that generates the end point potential of a segment and a step generator that generates a divided potential between both end points of the segment, the same A series resistance group (R_1 to R_n) formed by connecting an additional resistor 10 on the power supply side with a resistance value in series, and an additional resistor 14 on the earth side with the same resistance value as the additional resistor on the power supply side. A first mode selector switch S_2_0 is connected in parallel to the power supply side additional resistor, and another earth side additional resistor 12 having the same resistance value as the earth side additional resistor is connected to the ground side additional resistor. (n+1) output switch groups SW_1 to 2 connected in parallel via the mode changeover switch S_2_2 of No. 2 and turned on and off by a digital signal between each series connection point of the series resistor group and the common output terminal; SW_
1_6, the first mode changeover switch is turned off and the second mode changeover switch is turned on by the μ law designation signal, and the first mode changeover switch is turned on by the A law designation signal, and the second mode changeover switch is turned on by the A law designation signal. A step generator characterized by turning off a mode changeover switch.
JP3796379A 1979-03-30 1979-03-30 step generator Expired JPS6059774B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3796379A JPS6059774B2 (en) 1979-03-30 1979-03-30 step generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3796379A JPS6059774B2 (en) 1979-03-30 1979-03-30 step generator

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP6025685A Division JPS60216630A (en) 1985-03-25 1985-03-25 Step generator

Publications (2)

Publication Number Publication Date
JPS55130228A JPS55130228A (en) 1980-10-08
JPS6059774B2 true JPS6059774B2 (en) 1985-12-26

Family

ID=12512208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3796379A Expired JPS6059774B2 (en) 1979-03-30 1979-03-30 step generator

Country Status (1)

Country Link
JP (1) JPS6059774B2 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5792919A (en) * 1980-11-29 1982-06-09 Fujitsu Ltd Code converter
JPH0683074B2 (en) * 1985-06-25 1994-10-19 シャープ株式会社 Voltage generation circuit
JPH0323713Y2 (en) * 1986-11-20 1991-05-23

Also Published As

Publication number Publication date
JPS55130228A (en) 1980-10-08

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