JPS60258796A - Dynamic type semiconductor memory - Google Patents

Abstract

PURPOSE:To enlarge the degree of freedom of pattern designing of a large-scale memory element by arranging a control means belonging to one or plural complementary bit lines of repeated arrangement and a part or all of amplifying means alternately on both ends of complementary bit lines. CONSTITUTION:Wi and Wj are word lines to which a signal having amplitude larger than power source voltage is impressed An end of cumulative capacities 12, 12 is connected to complementary bit lines 2 and another end is connected to bit line 1 opposite to complementary bit lines through a source drain passage of a transfer gate 13 or 13' that selects a desired memory cell. The gate of the transfer gate 13 is connected to the word line Wi, and the gate of the transfer gate 13' is connected to the word line Wj. Thus, it becomes possible to make the repeated bit line pitch as small as possible, and the area of memory cell can be made very small maintaining sufficient operation allowance, and large scale dynamic memory element can be realized.

Description

[Detailed Description of the Invention] <Technical Field of the Invention> The present invention relates to improvement of a dynamic semiconductor memory device.
More specifically, the present invention relates to a dynamic semiconductor memory device having a novel configuration that enables high performance of Dynamisone Kenko.

<Technical Background of the Invention and its Problems> The memory cell configuration of the conventional Guinamisoku memory element has a limited operating margin due to manufacturing variations in the load capacitance of complementary bit lines used for inputting and outputting information. There were problems such as deterioration.

That is, the circuit of a conventionally used N-channel MOS dynamic memory element is configured as shown in FIG. 9, for example.

In FIG. 9, S is a sense amplifier, and 1 and 2 are complementary hit lines. Further, 3 and 3' are memory cells, and 4 and 4' are dummy cells. Wi and Wl
is a word line, WDO and WD+ are dummy word lines,
φP is a precharge signal.

5 and 5' are storage capacitors, and 6 and 6' are transfer gates for selecting desired storage capacitors 5 and 5' and electrically connecting them to bit lines 1 and 2.

Here, the capacitance values of 5 and 5' are assumed to be Cs.

7 and 7' are dummy storage capacitors, whose capacitance value is cD
shall be.

8 and 8' are transfer gates for selectively connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2, and 9 and 9' are transfer gates for connecting the dummy storage capacitors 7 and 7' to the bit lines 1 and 2 during the precharge period.
and 7'.

10 and 10' are bit line capacitances, and their capacitance values are expressed as c
Let it be B.

FIG. 10 is a timing diagram for explaining the operation of FIG. 9.

In FIG. 9, when the memory cell on the bit line 1 side is selected, the dummy cell 4' on the bit line 2 side is selected;
Furthermore, when the memory cell on the bit line 2 side is selected, the dummy cell 4 on the bit line 1 side is selected.

Here, a case will be described in which the word line Wi and dummy word line WDO are at a high potential and the memory cell 3 and dummy cell 4' are selected.

Here, it is assumed that a voltage boosted to a power supply voltage (Vcc) or higher is applied to the word line W1 and the dummy word line WDo. It is also assumed that bit lines 1 and 2 are precharged to the power supply voltage (Vcc) during the precharge period in which the precharge signal φP is at a high potential. For convenience of explanation, the bit line 1 is assumed to be B, the bit line 2 is assumed to be B, and the logic of B: high potential and B: low potential is set to 11111, and the logic of B: low potential and B: high potential is set to logic +1011.

■When the ground potential (GND) is stored in the storage capacitor 5 of the memory cell 3, the precharge signal φP falls to a low potential and enters the active period, and when a word line signal is input at time t1, the bit line 1 side The potential VBI is as follows.

On the other hand, the potential VB2 of the bit line 2 on the dummy cell side is as follows.

Therefore, the differential potential ΔV1 input to the sense amplifier S is becomes.

(2) When the power supply potential (Vcc) is stored in the storage capacitor 5 of the memory cell 3 In this case, the potential VBI on the bit line I side does not change and remains VBI''''VCC.

On the other hand, the potential VB2 of the bit line 2 on the dummy cell side is as follows.

Therefore, it becomes a differential potential input to the sense amplifier S.

Here, in both cases of ■ and ■ above, if the storage capacitance value cD of the dummy cell is determined so that the differential potential input to the sense amplifier S is the same, then the differential potential input to the sense amplifier ΔV is as follows.

The differential potential is amplified to a desired value by activating the sense amplifier S after time t2.

In such conventional systems, the load capacitance balance between bit lines 1 and 2 is very important, but due to manufacturing variations, etc., it is difficult to maintain the capacitance balance between bit lines 1 and 2, which deteriorates the operating margin. There were drawbacks such as:

In addition, with recent advances in microfabrication technology, attempts have been made to realize large-scale memory devices, and as a result, the area of memory cells has inevitably become smaller, and therefore the storage capacity within memory cells has tended to decrease even further. A new problem has arisen: the differential voltage required to drive the amplifier cannot be obtained.

Furthermore, as the memory cell area is reduced, the bit line pinch becomes smaller, and it becomes difficult to accommodate the control circuits, sense amplifiers, etc. belonging to the bit lines within the above bit line pitch while maintaining the capacitance balance. It's becoming possible.

<Objects and Structure of the Invention> The present invention has been made in view of the above points, and the present invention is capable of controlling the differential voltage input to the sense amplifier using the conventional method even when the same storage capacitor as the conventional method is used. Or, to obtain the same differential voltage as in the conventional method, the memory cell area can be configured to be very small, and the stray capacitance of the complementary bit line required in the conventional method can be reduced. It is an object of the present invention to provide a dynamic semiconductor memory device which has the advantage that there is no need to carefully consider balance in design as in conventional methods, and the degree of freedom in pattern design of large-scale memory elements is therefore greatly increased. To achieve this objective, the dynamic semiconductor memory device of the present invention provides complementary bit lines for inputting and outputting information, storage capacitor means for storing information, and selection for specifying this storage capacitor means. one end of the storage capacitor means for storing the information is connected to one end of the complementary bit line for inputting/outputting the information, and the other end of the storage capacitor means is connected to the other end of the storage capacitor means via the selection means. a memory cell configuration connected to the other end of the complementary bit line; amplifying means for amplifying a signal output to the complementary bit line; and control means belonging to the complementary bit line. In the dynamic semiconductor memory device comprising: a part or all of the control means and the amplification means belonging to the single complementary bit line or the plural complementary bit lines arranged repeatedly, the complementary bit line ) are arranged alternately at both ends of the line.

<Embodiments of the invention> A detailed description will be given below with reference to the drawings.

FIG. 1 is a diagram showing a circuit configuration of an embodiment of a dynamic semiconductor memory device according to the present invention, and is composed of an N-channel MO8 circuit.

In FIG. 1, S is a sense amplifier, 1 and 2 are complementary bit lines similar to those in FIG. 9, and I+ and I
I' is a characteristic memory cell in the present invention.

Wi and Wl are word lines to which signals having an amplitude equal to or higher than the power supply voltage (Vcc) are applied.

12 and 12' are storage capacitors, one end of which is connected to the complementary bit line 2, and the other end connected to the complementary bit line 2 through the source-drain path of the transfer gate 13 or 13' that selects a desired memory cell. The bit line H on the opposite side is connected.

Further, the gate of the transfer gate 13 is connected to the word line W.
1, and the gate of the transfer gate 13' is connected to the word line W.

14 and 15 are stray capacitances of bit lines 1 and 2.

Here, the storage capacitance value of the storage capacitors 12 and 12 of the memory cells is Cs, the capacitance value on the bit line 1 side is CBI, and the capacitance value on the bit line 2 side is CB2. Also, this capacitance value CB
I, CB2 to clarify the characteristics of the present invention,
Suppose that they have different capacitance values (CBI\CB2).

16 is a dummy storage capacitor, one end of which is connected to the bit line I.
The other end is connected to the dummy control signal φD.

17 and 18 are sense input terminals of the sense amplifier S,
19 is MO8 field effect transistor (hereinafter MO5FE)
The source/drain path of the MOS FET 19 is interposed between the bit line 2 and the sense input terminal 18, and the voltage of the bit line 2 is controlled by the sense amplifier S by the second control signal LI/r2. The bit line 2 and the input end 18 of the sense amplifier are electrically connected only during the period when the input end 18 of the sense amplifier is applied manually.

20 is a MOSFET, and the source-drain path of the MO3FET 20 is interposed between the bit line 2 and the power supply Vcc, and the second precharge signal φP2 is used in the precharge period, write period, or active period of the sense amplifier S. Bit line 2 is held at power supply potential (Vcc).

Reference numeral 21 designates a conventionally used MO5FET for bit line precharging, which is interposed between the source drain path of the MO5FET 21 and the bit line 1 and the power supply VCC, and is activated during the precharge period by the first precharge signal φP1. Bit line 1 is held at power supply potential (Vcc). Reference numerals 22 and 23 are conventionally used transfer gates between the bit line and the sense amplifier, and the first control signal φTl+ temporarily disconnects the bit line and the sense amplifier at the beginning of driving the sense amplifier, thereby increasing the sense sensitivity. There is only work to do.

24 and 25 are column selection MOS FETs for selecting desired complementary bit lines, and the column selection signal C1
By electrically connecting a desired bit line pair and data buses D and D, information is output.

In addition, in the circuit shown in Fig. 1, 1 is indicated in the broken line block.
The portions marked 2 and 2 are complementary bit lines 1 and 2.
3 shows a control means portion for processing pairs of electrical information.

Here, for convenience, we assume that bit line 1 is B and bit line 2 is B, B: high potential and B: low potential is logic pin, and B: low potential is B: high potential is logic u OI+, and memory cell A case where II is selected will be explained.

(2) Writing of logic "'1'' or logic +10" A timing diagram for writing in the embodiment of the present invention is shown in FIG.

When the precharge period ends, the first and second precharge signals φPI and φP2 fall, and then the word line W1
rises above the power supply voltage (Vcc) and a read operation is started, but if it is the current active period or write cycle, the data to be written is output on the data bus D.

The second precharge signal φP2 is again applied to the power supply voltage (Vcc
), the MOSFET 20 turns on and the bit line 2 is fixed at the power supply potential (Vcc), and the second control signal φT2 falls to the ground potential (GND) and the MOSFET 20 turns on.
After FET+9 is turned off and the bit line 2 and sense amplifier S are disconnected, the column selection signal C1 is set to the power supply voltage (
Vcc), and MOSFETs 24 and 25 are turned on. At this point, the data bus D and the bit line 1 are electrically connected, so that the write data on the data bus D is output onto the bit line 1, and is passed through the transfer gate 13 to the node 26 of the memory cell 11.
is memorized.

In the case of writing the logic fl + 11, the power supply potential is output onto the data bus D, and therefore the power supply potential (Vcc) is stored in the node 26 of the memory cell 11. On the other hand, in the case of writing logic "0", the ground potential is output on the data bus D, and therefore the ground potential (GND) is stored in the node 26 of the memory cell 11.

Here, the other data bus D and bit line 2 are MO5FE
Since T+9 is in the off state, it is electrically disconnected, so the information on data bus D is not involved in writing to the memory cell.

(2) Reading of logic ``1'' A timing diagram for reading in the embodiment of the present invention is shown in FIG.

When the precharge period ends, the first precharge signal φPI goes to the ground potential (GND)! Furthermore, the second precharge signal φP2 drops to a predetermined potential that sufficiently turns off the MOSFET 20, and the bit lines 1 and 2 are disconnected from the power supply (Vcc) and placed in a floating state.

Next, the dummy drive signal φD is raised to the power supply potential (Vcc), and by capacitive coupling of the dummy storage capacitor 16, the potential on the bit/node line 1 side is slightly raised above the power supply voltage (Vcc).

Next, a selection signal higher than the power supply voltage (Vcc) is input to word line W1, and bit lines 1 and 2 are capacitively coupled by storage capacitor 12 via transfer gate 13.

Since the power supply potential (Vcc) was previously held at the node 26 of the memory cell 11, the potentials of the bit lines 1 and 2 only slightly change to the lower potential side. No reversal of potential occurs.

The differential voltage between bit lines 1 and 2 in this case is Δ
V, then... (Equation 2) The differential voltage ΔVl is input to the input terminals 17 and 18 of the sense amplifier S.

Next, the first control signal φT1 drops to a predetermined potential and disconnects the sense amplifier S and bit lines 1 and 2, and then
The second control signal φT2 falls to the ground potential (GND), and the second precharge signal -φP2 rises again to a potential higher than the power supply voltage (VC(:)), and MO8FET2
By turning on the second bit line 2, the second bit line 2 is fixed at the power supply potential (Vcc).

Next, the sense amplifier drive signal φS falls to the ground potential,
The differential voltage inputted to the sense amplifier S is amplified to a desired voltage. In this case, the node 26 of the memory cell 11 holds a high potential, and there is no need for rewriting.

(2) Reading of logic +1011 A timing diagram of the bit line and sense input signal in reading of logic +1011 is also shown in FIG.

The operation until the selection signal is input to the word line W1 is the same as that for reading the logic (I111). In the case of reading the logic "0", the ground potential (GND) is applied to the node 26 of the memory cell 11 in advance. Therefore, when the transfer gate 13 is turned on by the selection signal, the potential of the bit line 1 decreases, and conversely, the potential of the bit line 2 increases, and the potentials of the bit line 1 and bit line 2 are reversed. If the differential voltage between bit lines 1 and 2 in this case is Δ■2, then... (Formula 3) is input.

Next, the first control signal φ
After T+ drops to a predetermined potential and disconnects the sense amplifier S and bit lines I and 2, the second control signal φT2
falls to the ground potential (GND), and the second precharge signal φP2 rises again to a potential higher than the power supply potential (Vcc), turning on the MO5FET 20, thereby bringing the second bit line 2 to the power supply potential. (Vcc).

Next, the sense amplifier drive signal φS drops to the ground potential,
The differential voltage input to the sense amplifier S is amplified to a desired voltage, and the bit line 1 is discharged to the ground potential via the MO5FET 22, thereby rewriting the ground potential (GND) to the node 26 of the memory cell 11. Do the following.

Here, if the dummy storage capacitance value cD is set so that the differential voltages ΔV1 and ΔV2 between the human lines in reading the logic 11111 and the logic if OI+ are both equal, the dummy storage capacitance value CI) becomes ( Formula 2
) and (Equation 3) become as follows.

Here, in order to clarify the features of this method when compared with the conventional method, the differential signal voltage input to the sense amplifier under the condition of CB + + CB2 = 2CB is expressed as (Formula 4) and (Formula 4) l) The results are shown in FIGS. 4 and 5.

Figure 4 shows the present invention when CB/C3=IO.
The relationship between the differential signal voltage and the stray capacitance ratio CBI/CB2 of bit line 1 and bit line 2 in this embodiment is shown.

As is clear from the graph shown in Figure 4,
According to the present invention, if the sum of the stray capacitances "CBI and CB2" of complementary bit lines 1 and 2 is constant, CBI and C
The larger the difference in B2, the greater the differential signal voltage, so in order to take full advantage of the features of the present invention, one of B5. The stray capacitance of the line is made as small as possible, which results in a larger differential signal voltage.

This is a very significant feature of the present invention, and completely eliminates the restriction that complementary bit lines must have the same stray capacitance as in conventional systems.
The degree of freedom in pattern design is greatly increased.

FIG. 5 shows the conventional method and the embodiment according to the present invention under the condition that CBI + CB2 = 2CB.
The differential signal voltage characteristics when changing the CB/C5 ratio are shown.

28 is the differential signal voltage characteristic of the conventional system obtained by formula (1), and 27 is the differential signal voltage characteristic obtained by formula (4) in the embodiment according to the present invention.

In the embodiment according to the present invention, from FIG. 4, CBI/CB
It has been shown that the differential signal voltage becomes the smallest at a value of 2 or around 1.0, but even under such worst-case conditions, as shown in graph 28 in Figure 5, the differential signal voltage of 15 to 2 of the conventional method is
A differential signal voltage about twice as large is obtained, and the characteristics shown in graphs 29 and 30 can be realized by devising the distribution of the bit line stray capacitance described above.

This means that by adopting the method of the present invention, it is possible to increase the differential signal voltage without changing the storage capacity of the memory cell, which is very effective as a means for realizing large-scale memory devices. .

6 and 7 are diagrams showing the memory cell structure of the dynamic semiconductor memory device shown in FIG. 1, respectively.

FIG. 6 shows a cross-sectional structure taken along line A-A' in FIG.

FIG. 7 is a pattern diagram for four memory cells (Mo-Ma), and in an actual memory element, this pattern is repeatedly arranged as many times as necessary.

Next, the structure of the memory cell according to the present invention is shown in FIG.
The following explanation assumes a channel MOS process.

First, an element isolation region 32 is created on the surface of a P-type silicon substrate 31 by selective oxidation or the like, and then a portion 33 forming a word line and a transfer gate of a memory cell is formed by a first wiring means.

Next, diffusion regions 34 and 35 which will become the source and drain of the MOSFET are formed by ion implantation or the like.

Next, after opening a buried contact window 36 in the drain part 34 of the transfer gate part, one electrode 37 of the storage capacitor is formed by a second wiring means, and connected to the drain part 34 of the transfer gate part through the buried contact window 36. do.

Here, the electrode 37 formed by the second wiring means can also be formed on the upper surface of the first wiring means 33, contributing to an increase in the storage capacity of the memory cell. After forming a thin insulating film 38 for forming a storage capacitor on the upper surface of the second wiring means, the other electrode of the storage capacitor is formed by a third wiring means 39, and then an insulating film 40 is formed.

Next, after opening a normal contact window 50, a fourth wiring means 51 is formed, and the contact window 50 is connected to the source region 85 of the transfer gate portion.

Here, the first to third wiring means are generally made of ordinary polysilicon, silicide, high melting point metal, etc., and the fourth wiring means is generally made of aluminum, etc. .

The fourth wiring means 51 and the third wiring means 39 are shared by a plurality of memory cells, and constitute complementary bit lines. In other words, in the memory cell structure of the embodiment according to the present invention, complementary bit lines are formed with different wiring means in a multilayer structure, and therefore, complementary bit lines are formed with the same wiring means in the conventional method. In comparison, the memory cell area can be reduced. Also, the diffusion region 34
Since the area of the contact windows 36 and 35 is sufficient to form the contact windows 36 and 50, the diffusion area in the memory cell is smaller than in the conventional method, and the resistance to alpha rays is increased, resulting in a stable memory element. realizable.

FIG. 8 is a diagram showing an example of arrangement of a memory cell array according to the present invention.

It has already been mentioned that according to the memory cell configuration according to the present invention, the memory cell area can be significantly reduced. but,
Along with this, the control circuit Kl, 2, sense amplifier S, etc. of the bit line pair to which the memory cell is connected will require a relatively large area compared to the memory cell, and the above-mentioned repetitive bit line pitch A problem arises in that it becomes difficult to house the circuits in the interior.

In the present invention, such problems are solved by arranging the control circuits Kl, 2, sense amplifiers S, etc. belonging to a single or multiple bit line pairs at both ends of each bit line pair. are doing.

FIG. 8 shows an example of the arrangement of the memory array. In FIG. 8, -co'-C6a are complementary bit line pairs, and KO""K63 are complementary bit line pairs. Control circuit K for i to co-c63
1, 2, sense amplifiers, etc., and an example is shown in which they are arranged alternately at both ends of each bit line pair.

That is, in FIG. 8, the control means portions such as the control circuits K1 and 2 and the sense amplifiers S belonging to the first complementary bit line pair Co are connected to the bit line pair C.

Control means portions are arranged at the left end of each bit line pair, and control means portions are similarly arranged alternately at the right or left end of each bit line pair.

With this configuration, it is possible to minimize repeated pinching of bit lines without being affected by the control means belonging to each bit line pair, which requires a relatively large area compared to a memory cell, and as a whole, The memory cell area of the bit lines 1 and 2 can be divided into two ends, and the control means K I is provided with a circuit, or the bit lines 1 and 2 can be integrated into one end of the pair. It is also possible to configure a memory cell array, and the arrangement example of the memory cell array shown in FIG. 8 shows an arrangement example in this case.

In addition, in explaining the present invention, in the above-described embodiment, an example using an N-channel MOS process was explained.
The present invention does not limit the manufacturing process of the element,
P-channel MOS process.

It can be applied to CMOS process, SOI process, etc.

Further, in the above embodiment of the present invention, the control means portion may be divided as shown in FIG. 1 and sequentially arranged alternately at both left and right ends of each bit line pair. Furthermore, it goes without saying that the arrangement of the control means portion as described above may be done for a part of the control means.

<Effects of the Invention> As described above, according to the present invention, one end of the storage capacitor means for storing information is connected to one end of the complementary bit line used for inputting and outputting information, and the other end of the storage capacitor means is connected to the other end of the complementary bit line (1) through a selection means for specifying the storage capacitance means. Since some or all of the control means and amplification means belonging to the above-mentioned complementary bit lines which are repeatedly arranged are arranged alternately at both ends of the above-mentioned complementary bit lines, the repeating bit line pitch is As a result, the memory cell area can be made extremely small while maintaining a sufficient operating margin, and this can greatly contribute to the realization of large-scale memory devices.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the circuit configuration of an embodiment according to the present invention, and FIG.
The figure is a timing diagram in a write cycle to explain the operation in an embodiment according to the present invention, FIG. 3 is a timing diagram in a read cycle to explain the operation in an embodiment according to the present invention, and FIG. 4 is a timing diagram in a read cycle to explain the operation in an embodiment according to the present invention. FIG. 5 is a φ÷-characteristic diagram showing the relationship between the differential signal voltage during reading between complementary bit lines and the stray capacitance ratio of the complementary bit lines in an embodiment according to the present invention. A graph comparing the differential signal voltages between complementary bit lines in the embodiment, FIG. 6 is a cross-sectional view of the memory cell structure in the embodiment according to the present invention, and FIG. 7 is a plane view of the memory cell structure in the embodiment according to the present invention. 8 is a conceptual diagram for explaining the arrangement of complementary bit lines, control circuits, sense amplifiers, etc. in an embodiment according to the present invention, FIG. 9 is a circuit diagram of a dynamic memory element in a conventional system, and FIG.
The figure is a timing diagram for explaining the operation in the conventional system. Wi, Wj - Word line, WDO, WD+"' dummy word line, φP... precharge signal, φPI first precharge signal, φP2... second precharge signal, φD... dummy control signal, φT1...-first control signal, *2... second control signal, φS... sense drive signal, C1... column selection signal, D, D... data bus, CB. CBl, CB2・Bit line capacitance value, Cs...Storage capacitance value of memory cell, CD...Storage capacitance value for tummy, 1゜2, B, B ・Bit line, S-sense amplifier, 3゜3'
, 11. +1 memory cell, 4,4' dummy cell, I
2, + 2'...Storage capacity of memory cell, 13
゜13'... Transfer gate, 16... Storage capacitor for tammy, 32 - Element isolation region, 34.35 - Diffusion region, 36... Buried contact window, 33... First
wiring layer, 37... second wiring layer, 39... third wiring layer, 51... fourth wiring layer, 38... thin insulating film,
50 ・Contact window, Co-C 63 ・Complementary bit line pair, KO- 63 . . . Control means portion such as a control circuit and a sense amplifier belonging to the complementary bit line pair. Agent Patent attorney Aihiko Fuku (2 others) Cat/C
θ2 Fig. 4 188:3 Output n+ person Sharp Co., Ltd. agent Yoshihiko Fukushi (斂! 56 7 θ 9 10 /l /2 13 /4CB
/C5 ratio Figure 5 Figure 6

Claims (1)

[Claims] 1. Complementary bit lines for inputting and outputting information, storage capacitor means for storing information, and selection means for specifying the storage capacitor means, and a complementary bit line for inputting and outputting the information. One end of the storage capacitor means for storing the information is connected to one end of the bit line, and the other end of the storage capacitor means is connected to the other end of the complementary bit line via the selection means. a dynamic semiconductor memory device comprising: amplifying means for amplifying a signal output to the complementary bit line; and control means belonging to the complementary bit line; A dynamic semiconductor memory device characterized in that a part or all of the control means and the amplification means belonging to the complementary bit line are arranged alternately at both ends of the complementary bit line.