JPS60256290A - Pattern check device - Google Patents

Abstract

PURPOSE:To check a pattern at a fast processing speed by calculating in advance a normal directing value at each pattern edge position depending on raster scanning, and reading and checking the pattern linearity depending on the change. CONSTITUTION:An input picture is converted into a binary-coding picture 103 by a binary-coding circuit 102 and a pattern edge signal 105 is outputted by an edge detecting circuit 104. Further, the picture 103 is inputted to a picture segmenting circuit 106, where (2N+1)X(2N+1) picture elements 107 are segmented and a circle scanning circuit 108 extracts only a picture element 109 on a circle. The binary state of the picture element 109 is scanned sequentially from a prescribed position, two postions of ''0'' and ''1'' change positions are obtained from a counter circuit 111 and a mean value is outputted from a normal detecting circuit 112 as a normal direction value 113. The value 113 is stored in synchronizing with the scan position of a raster scanning to a memory line 114, the stored normal direction value 115 is read sequentially, fed to a check circuit 118, the change is calculated and compared with the reference and the linearity of the check object is checked and decided 119.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a pattern inspection apparatus, and particularly to a pattern inspection apparatus that inspects the pattern formation state of an inspection object obtained by scanning with a photoelectric conversion scanner.

[Prior art]

When a pattern formed on an object to be inspected is composed of a plurality of straight lines, conventional pattern inspection equipment inspects the linearity of each constituent straight line to determine whether the pattern formation condition is good or bad. First, the pattern edge position is detected from the input image of the inspection object obtained by scanning with photoelectric conversion scan, and the pattern edge position is sequentially traced by vector scan, and the pattern etch is determined based on the connection relationship of the position coordinates. A method of calculating the connection direction and testing linearity was used. In this case, in order to calculate the connection direction by sequentially tracing the pattern edge positions using vector scanning, the coordinates of the previous pattern etch position are extracted and determined from the relationship with the currently read pattern etch position coordinates. However, the drawback is that the processing speed for inspection is slow.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a pattern inspection apparatus that can improve processing speed for routine use.

That is, an object of the present invention is to provide a pattern inspection apparatus using rask scan in order to reduce the processing time, which was a drawback of the conventional pattern inspection apparatus using vector scan.

That is, an object of the present invention is to inspect the +Nll1i property of each constituent straight line when a pattern of an object to be inspected is composed of a plurality of straight lines, and to determine whether the pattern formation state is good or bad. , All pattern etch positions are sequentially detected by rusk scanning from a manual image of the inspection object obtained by scanning with a photoelectric conversion scanner, and the normal direction value at each pattern edge position is calculated in advance by rusk scanning. It is an object of the present invention to provide a pattern inspection apparatus that stores the values in a memory, then sequentially reads out the values, and inspects the linearity of the pattern based on the amount of change.

That is, an object of the present invention is to provide a pattern inspection device with high processing speed.

[Structure of the invention]

The pattern inspection device of the present invention scans and reads the pattern of the object to be inspected using a full photoelectric conversion scanner.
a binarization circuit that converts the binarized image into a binarized image; and a binarization circuit that scans the binarized image by Rask scan from IO1 to 111;
Alternatively, an edge detection circuit that sequentially detects the position changing from ll'' to MQu as a pattern edge position, and (2N+1)X centering on the detected pattern edge position.
An image cutting circuit that simultaneously outputs the binary states of (2N+1) pixels, and a circle that simultaneously outputs the binary states on a circumference of a radius N centered at the pattern edge position among the outputs of the image cutting circuit. The scanning circuit sequentially scans the binary state on the circumference of the scanned circle from a predetermined position, and detects two positions: the position where it changes from 101 to 111, and the position where it changes from 11' to 101. a counter circuit that detects each, a normal detection circuit that calculates an average value from the count values at these two locations and uses this as a value in the normal direction at the detected pattern etching position, and the normal direction value. a memory circuit for storing the normal direction value in synchronization with the scanning position of the rask scan, and a succession circuit for sequentially tracing and reading out the stored normal direction value based on the connection relationship of the stored position. and a testing circuit that tests the linearity of the object to be tested by sequentially determining the amount of change in the normal direction values that have been read out sequentially.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In the pattern inspection apparatus shown in FIG. 1, an input image 101 of an object to be inspected scanned by a photoelectric conversion scanner 100 is converted into a binarized image 103 by a binarization circuit 102 . For this binarized image, the edge detection circuit 1
04, the pattern edge position is detected and a pattern edge signal 105 is output. In addition, the binarized image 10
3 is input to the image cutting circuit 106 n, (2N+1
)x(2N+1) pixels 107 are extracted, and a circular scanning circuit 108 extracts only pixels 109 on the circumference. The binary state of the pixel 109 on this circumference is sequentially scanned from the predetermined position.
Two positions, the position where the value changes from 01 to 111 and the position where the value changes from 111 to 01, are determined by the counter circuit 110 and output as a count value 111. An average value is determined by the normal line detection circuit 112 from the count values at these two locations, and is output as a normal line direction value 113. This normal direction value 113 is stored in the memory circuit 114 as
It is stored in synchronization with the YANG position. Next, the stored normal direction values 115 are sequentially read out by a readout path 116 and sequentially traced based on the stored positional relationship. This sequentially read normal direction value 1
17 is added to the frugality circuit 118, the amount of change is calculated and compared with a reference value, the +1m characteristic of the object to be inspected is tested, and a determination signal 119 is output.

FIG. 2 is a block diagram showing an example of the image cutting circuit 106 shown in FIG. 1.

The image cutting circuit shown in FIG. 2 extracts (2N+l
)X (2N+1) The binary states of the pixels are output simultaneously. That is, the binarized image scanned and read out by Rask scan is input to the delay circuit 1. The output of delay circuit 1 can be input to delay circuit 2, and the output of delay circuit 2 can be input to delay circuit 3. This delay circuit is (2N+
1) are prepared, and the output of the Mth (M=1 to 2N) delay circuit M is the output of the M+1st (M=1 to 2N) delay circuit (M+
1) is added as an input signal. At the same time, the outputs of these delay circuits are added as input signals to a (2N+1) Bit length shift register, and output to the serially input 2(ll!) image parallel. In other words, as shown in FIG. By using the circuit configuration of the image cutting circuit w1106 as shown in the figure, an image of (2N+1) x (2N+1) pixels is generated from the binary image read out by rask scan from the four parallel outputs of the shift register. Output.

FIG. 3 is a configuration diagram showing an example of the edge detection circuit 104 shown in FIG. 1.

The etch detection circuit shown in FIG. 3 scans the input binarized image using a rask scan and sequentially detects positions where the pattern changes from 101 to Ill or from 111 to IQI as pattern edge positions.

In other words, multiple outputs are output from the image cutting circuit described above (
2N+1 )X (2N+1) pixels, BNl
*The CN+FNl signal is applied to the terminals 20, 21.22, respectively, and the pattern edge position changing from 10# to 11- and the pattern edge position changing from "11 to "Om" are detected by the gate element, and the output terminal 24 is output as a pattern etch signal.

FIG. 4 is an explanatory diagram illustrating the operation of the circular scanning circuit shown in FIG. 1. That is, among the outputs of the image cutting circuit,
FIG. 3 is a diagram for explaining a circular scanning circuit that simultaneously outputs binary states on a circumference of a radius (in the case of N=6) with the pattern etching position as the center;

(2N+
1) By extracting only the pixels on the circumference shown in Figure 4 from X(2N+1) pixels, -9 = Performing circular scanning on the isometrically input binarized image. become.

FIG. 5 is a configuration diagram showing an example of the counter circuit 110 shown in FIG. 1.

The counter circuit shown in FIG. 5 sequentially scans the binary state on the circumference of the scanned circle from predetermined positions, and the position changing from 'o' to 111.
Two positions where the value changes from '11 to IQI are detected. At the pattern edge position detected by the etch detection circuit 104 described above, the binary state on the circumference outputted multiple times by the circular scanning circuit 108 is inputted to the parallel input terminal 40 of the shift register 42 and is input by the shift clock 41. IBit
, the serial data 45 is sent to the gate element 44, '
Signal 47 changing from 11 to 101 and IQI to IIM
A signal 48 that changes to is output. Further, the shift clock 41 is input to a counter 49, and the distance from the smoothed position is counted and output as a count output 54.

This count value 54 is latched by the latch 50 with a signal 47 changing from 111 to 101, and a position signal 52 changing from 111 to 10@ is output.

Further, the count fli54 is set by the latch 51 to
Latched by signal 48 changing from QI to l11, IQ
A position signal 53 changing from I to l11 is output. That is, by using such a circuit configuration, the counter circuit 110 sequentially scans the binary states on the circumference of the scanned circle described above from a predetermined position, and changes from -〇- to 111K. Two locations are detected: the location where the IQIK changes from 111, and the location where the IQIK changes from 111.

FIG. 6 is a configuration diagram showing an example of the normal line detection circuit 112 shown in FIG. 1. That is, the counter circuit 110 described above
The position signal changing from 101 to 111 and the position signal changing from l11 to IQI detected by are input to input terminals 61 and 62 of an adder 62, respectively,
It is output as an added value 63. This addition 1-63 is shifted by 1 Bit by a shift register 64, an average value is calculated, and this value is outputted as a normal direction value 65 at the detected pattern edge position and stored in the memory.

FIG. 7 is an explanatory diagram for explaining the operation of the continuation circuit 116 shown in FIG. 1. That is, FIG. 7 is an explanatory diagram illustrating the operation of sequentially tracing and reading the normal direction values stored in the memory based on the connection relationship of the stored positions. The contents of the memory are cut out as 3×3 data 66 as shown in FIG. 7 by a circuit configuration similar to the image cutout circuit 106 described above, and the value of the center a is the normal direction value. It is scanned until it reaches the memorized position. Next, at this scanned position, eight peripheral data blC0d, e, f1g, h.

The memory address is controlled so that the position where the normal direction value is stored will be the center position when the next 3x3 data is cut out. Figure out the content. By repeating this process, the normal direction values stored in the memory are sequentially traced and read out based on the connection relationship of the stored positions.

FIG. 8 is a configuration diagram showing an example of the test circuit shown in FIG. 1.

That is, the inspection circuit shown in FIG. 8 sequentially determines the amount of change in the normal direction value of the drive pattern and inspects the ttst property of the pattern formed on the object to be inspected. The normal direction values sequentially read out by the aforementioned readout circuit 116 are input to the input terminal 70, latched by the n1 latch 71, and output as the normal direction value 73. Next, the straight line read out by tracing one normal direction value is latched by a latch 72 and output as a normal direction value 74. Differentiator 75
Then, the difference between the two normal direction values 73 and 74 latched alternately in this way is determined and compared with a preset reference value 78 in the comparator 77, and if the difference is larger than this reference value, , a judgment signal 79 indicating that the pattern deviates from the direct swelling property is output. FIG. 9 is a diagram illustrating the operation of calculating the above-mentioned normal direction value in the pattern inspection apparatus shown in FIG. 1. FIG. As described above, the etch detection circuit 104 detects the pattern edge position 81 from the input binarized image, and the circular scanning circuit 108 performs a nine-circle omnivorous scan centered on the detected pattern edge position, and the circumference 82 The above 211N state is output. 2 on this circumference
The value states are scanned sequentially from predetermined positions [83 to n, positions 84 and II changing from 'o' to 111.
The counter circuit 110 detects two locations at the position 84 where I changes to 101, calculates an average value from the count values at these two locations, and calculates the average value as the normal direction value at the detected pattern edge position. As, normal detection circuit 1
I was born at 12. This normal direction value is expressed as a numerical value, but in FIG. 9, it is shown as a pseudo vector quantity 85 as a distance on the circumference from the reference point 83. Such processing is performed at each pattern edge position, and the normal direction value at each pattern edge position is successively determined by rask scan.

14- FIG. 10 is an explanatory diagram for explaining the operation of inspecting the linearity of a pattern formed on an object to be inspected based on the normal direction value calculated at the valley pattern edge position. Similar to FIG. 9, in FIG. 10, the normal direction value calculated at each pattern edge position is represented by a vector quantity 91. As shown in the M2O diagram, this normal direction value 91 is
When linearity is maintained, the values are the same, but in the non-linear portion 92, the values change. Therefore, by detecting the amount of change in this normal direction value, it is possible to detect a location where linearity deviates.

〔Effect of the invention〕

The pattern inspection apparatus IT of the present invention determines the linearity of the pattern Kl- by determining the normal direction value at the pattern edge position of the input image of the inspection object, which is composed of several straight lines, by rask scanning. Since the quality of the pattern formation state is determined by performing the FI inspection, there is an effect that the processing time for inspection can be shortened.

That is, the pattern inspection apparatus of the present invention has the effect of increasing the processing speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of the image cutting circuit shown in FIG. 1, and FIG. 3 is a block diagram showing an example of the edge detection circuit shown in FIG. 1. 4 is an explanatory diagram for explaining the operation of the circular scanning circuit shown in FIG. 1, FIG. 5 is a construction diagram showing an example of the counter circuit shown in FIG. 1, and FIG. 6 is a diagram illustrating the operation of the circular scanning circuit shown in FIG. 7 is an explanation [F] for explaining the operation of the continuous circuit shown in FIG. 1, and FIG. 8 is an example of the inspection circuit shown in FIG. 1. FIG. 9 is an explanatory diagram for explaining the operation of outputting -)H in the normal direction in the embodiment shown in FIG. 1, and FIG. FIG. 3 is an explanatory diagram for explaining the operation of inspecting the linearity of a pattern that has been made. 10...Terminal, 11...Delay circuit, 1
2...Shift register, 20, 21.22...
...Terminal, 23...Gate element, 24...
...Output terminal, 30...(2N+1)X
(2N+1) pixels, 31...pixels on the circumference,
40...Parallel input terminal, 41...
Shift clock, 42...Shift register, 4
3...Flip-flop, 44...Gate element, 45...Serial data, 46...
...Flip-flop output, 47...signal, 48...signal, 49...counter,
50...Latch, 51...Latch, 5
2...Position signal, 53...Position signal,
54...Count output, 60...Input terminal, 61...Input terminal, 62...Adder, 63...Addition value, 64...Shift register, 65...Normal direction value, 66...
...3x3 data, 70...Input terminal, 71
...Latch, 72...Latch, 73.
...Normal direction value, 74...Normal direction value,
75...Differentiator, 76...Difference signal, 7
7...Comparator, 78...Reference value, 79
...Judgment signal, 80...Binarization image quality,
81...Pattern edge position, 82...
・Circumference, 83...Reference position, 84...
Change position, 85...Vector amount, 90...
...Binarized image, 91...Vector amount, 92.
...Non-linear portion, 100...Photoelectric conversion scanner, 101...Input image, 17-102...Binarization circuit, 103...・2
Valued image, 104...Edge detection circuit, 105
...Pattern edge signal, 106...
Image cutting circuit, 107... (2N+1)
X (2N+1) pixels, 108...Circular scanning circuit, 109...Pixels on the circumference, 110...
Counter circuit, 111...Count value, 112
... Normal detection circuit, 113 ... Normal direction value, 114 ... Memory circuit, 115 ...
...Normal direction value, 116...Continuous circuit, 117
...Normal direction value, 118...Test circuit, 11
9...Judgment signal. Representative Patent Attorney Shinichi Hara Nopa 18- Figure 3? 3 da L--J 5th leap 4th figure 553-

Claims (1)

[Claims] A binarization circuit converts the pattern read out by scanning the inspection object with a photoelectric conversion scanner into a binary image of 101, l11, and raster scans the 211f image from 101 to lII. Meri is 11' to 1
an edge detection circuit that sequentially detects a position changing to 01 as a pattern edge position; and an image cutting circuit that simultaneously outputs a binary state of (2N+1) x (2N+1) pixels centered on the detected pattern etch position. , a circular scanning circuit that simultaneously outputs binary states on a circumference of a radius N centered on the pattern etched position among the outputs of the image cutting circuit, and a circular scanning circuit that simultaneously outputs binary states on the circumference of the scanned circle. Scanning is performed sequentially from a predetermined position, and the position changes from 101 to 111 and from 111 to "Ol".
a counter circuit that detects two locations where the position changes, and a normal detection circuit that calculates the average value of the count values at these 2 m locations and uses this as the normal direction value at the detected pattern edge position. and a memory circuit for storing the normal direction value t in synchronization with the scan position of the raster scan, and sequentially tracing and reading out the stored normal direction value based on the connection relationship of the stored positions. 1. A pattern inspection device comprising: a successive output circuit; and an inspection circuit that inspects the linearity of an object to be inspected by sequentially determining the change sounds of the normal direction values read out sequentially.