JPS60256271A - Printer - Google Patents

Abstract

PURPOSE:To attain gradation recording with high quality by supplying a stable recording signal from a recording output circuit to a recording head at a section from an output set signal of a gate circuit to a reset signal of a control signal output circuit. CONSTITUTION:A picture signal A subjected to parallel conversion by a recording time setting circuit 5 is fed to a count circuit 1 and a gate circuit and the circuit 1 stores data (010) at the trailing of a load clock F, the circuit 2 ORs entirely parallel picture signals and outputs a set signal B to an F/F circuit 3 if even one signal of logical H level exists. The circuit 3 is set by the signal B to bring the recording signal B to the ''H'' level and the circuit 1 uses a transfer clock E to count down the signal. Similarly, a recording time setting circuit 6 applies a recording signal M to the recording head. Further, a peak value detecting circuit 4 compares (43) the picture signal stored in count circuits 41, 42, detects a maximum value and clears the count value other than the maximum value.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to printing devices such as facsimile machines and printers.

Conventional configurations and their problems Conventionally, devices that print with gradations, for example, recording using a thermal head, have problems such as (1) method of changing voltage, (2) pulse (application) width. There are methods to change the thermal energy, and each method records by increasing or decreasing thermal energy, but when changing the voltage, the thermal head itself has a voltage limit, and it is quite difficult to finely adjust the voltage. The method of changing the pulse width is to vary the applied pulse width using a timer (monostable multivibrator), but in this case, OR is used to adjust the pulse width, so the pulse width can be adjusted to match natural conditions and circuit conditions. It is very difficult to set the variable value to a constant time, and it is not very practical.

Objective of the Invention 3/\-7 An object of the present invention is to provide a printing device that can add gradation during printing, supply a stable printing pulse width, and provide a clear gradation image. The purpose is to

Structure of the Invention In order to achieve the above object, the present invention includes gate means for detecting the presence or absence of a parallel-converted image signal and outputting a set signal when this image signal is present, and a gate means for accumulating the image signal. The control signal output means is configured to output a control signal, and the recording signal output means is set by the output signal of the gate means and further reset by the output signal of the control signal output means. A stable recording signal can be supplied from the recording signal output means to the recording head in the period from the output set signal to the reset signal of the control signal output means, and high-quality gradation recording can be realized.

Description of examples The configuration of the present invention will be explained with reference to FIGS. 1 and 2.

1 is a counting circuit which accumulates a 1-bit analog image signal supplied as a digital parallel signal using a load clock F, counts down using a transfer lock E, and outputs a reset signal C as a termination signal. , reset the F/F circuit 3.

2. Check the above parallel picture signal with the gate circuit,
If all of them are "O", no output is made, and if there is even one "1'" in the parallel data, the set signal B is output.For example, O
This is the R gate. This output is supplied to the F/F circuit 3,
Turn F/p circuit 3 seven times.

3 is an F/F circuit, based on the above cent and set signals,
The recording time setting circuit 6 outputs a recording signal N, and the recording time setting circuit 6 outputs a recording signal M.

Reference numeral 4 denotes a peak value detection circuit which compares the maximum values of the respective parallel image signals and supplies a reset signal, which is the end pulse of maximum value transfer, to the F/F circuit 3.

41 and 42 are count circuits that accumulate the first image signal person (data 1D) and the second image signal person (data 2D).

5 Go to -1 43 is a comparator that compares the first image signal and the second image signal, compares the first>second, first>second, and selects the smaller one. A count circuit 41 or 42 that stores image signals is cleared by a reset signal R1 or R2.

44 is a gate circuit, which receives the reset signal of the signal from the count circuits 41 and 42 when the countdown has finished, and connects it to the F/F.
Supplied to circuit 3.

The specific operation of the present invention will be explained with reference to FIGS. 1 to 3.

First, the blocks of the recording time setting circuit 6 will be explained. The image signal of one pit is converted into parallel data through conversion such as MU/D conversion, and is processed as an image signal by the counting circuit 1.
and is supplied to the gate circuit 2. In count circuit 1,
Data (010) is accumulated at the falling edge a of the load clock F. Further, the gate circuit 2 ORs all the parallel image signals and outputs the set signal B C in FIG.

The F/F circuit 3 is set by the cent signal B and receives the recording signal N.
is set to H” level. Then, the count circuit 1 is counted down by the transfer lock E. For example, when HE
Since X"010"=DEC"2", when two transfer locks are input, the reset 1 signal C, which is a count end signal, is supplied to the F/F circuit 3. Then, the recording signal N of the F/F circuit 3 is reset and
Therefore, the output signal of the F/F circuit 3 becomes the recording signal N corresponding to the parallel image signal, and this signal becomes the recording time and is supplied to the recording head (not shown). The time setting circuit 6 also supplies the recording signal M to the recording head.By supplying the recording head with a signal corresponding to the input image signal in this way, it is possible to display gradations with high paper quality.However, this state remains unchanged. Now, if the input parallel image signal is 3 bits, the recording time is '0'.
It varies up to ~7''. Then, the recording time cannot move on to the next recording until the MAX '7'' is completed.

Therefore, another embodiment of the present invention will be described in which the next recording can be started immediately.

Go to 7-7 First, from FIGS. 2 and 3, the signal 1D in FIG. 3 is supplied to the first parallel image signal person, and the signal 2D in FIG. 3 is supplied to the second person. do.

The count circuit 41 uses a load clock F (a in FIG. 3).
Accordingly, the first signal 1D "Q10" is accumulated. Subsequently, the count circuit 42 accumulates the second signal 2D'"100'" using the load clock F (b in FIG. 3). The two accumulated signals 1D and 2D are then input to the comparator 43. The comparator 43 compares the sizes of the two data and outputs "ID<2D" and "ID>2D'".In the comparison of the two currently accumulated data,
ID is DEC = 2.2 D KaD IE Ci = 4
Of course, the ID (becomes 2D and the comparator 43 resets the count circuit 41) IR1 signal is given from the TEALCA to clear the image signal data 1D stored in the count circuit 41. And the count circuit 42 transfers the lock y
A countdown is started, and a reset signal, which is a count end signal, is simultaneously supplied to the recording time setting circuits 6 and F/F circuits in the recording time setting circuits 6 through the gate circuit 44, thereby resetting the recording signals N and V. As can be seen from the above explanation of the peak value detection circuit 4, the conventional recording time required to be ``7'' in the above explanation can be completed in ``4'', and the recording time can be significantly shortened and the recording head can be protected. Although the above explanation has been made using two systems of recording time setting circuits, the same applies even if multiple systems are used.

Effects of the Invention As described above, the present invention enables a stable pulse width to be freely supplied to the recording section and provides a high-quality floor with no time variation, compared to the conventional case where the recording time is set using an OR time constant, etc. Key recording is possible. Further, by detecting the peak value, the recording time can be significantly shortened, and the recording section is protected from being supplied with more recording time (pulse width) than necessary.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a printing device according to an embodiment of the present invention, FIG. 2 is a block diagram of essential parts of the embodiment, and FIG. 3 is a timing chart of the embodiment. 9 be. 1.41.42... Count circuit, 2,44.
...Gate circuit, 3...F/F circuit, 4
...Peak value detection circuit.

Claims (1)

[Claims] (1) gate means for detecting the presence or absence of a parallel-converted image signal and outputting a set signal when the image signal is present; control signal output means for accumulating the image signal and outputting a control signal; A printing device comprising recording signal output means that is set by the set signal and reset by the control signal and outputs a recording signal from the set time to the reset time. (Rumor) The printing device according to claim 1, wherein the control signal output means does not include a count circuit, and the recording signal output means includes a flip-flop circuit. A patent claim consisting of a comparing means for comparing image signals accumulated in a counting circuit to detect the maximum value and clearing the counting circuit other than the maximum value, and a gate circuit for gating the output from the counting circuit. 1. The printing device according to item 1.