JPH0238066A - Thermal recording apparatus - Google Patents

Abstract

PURPOSE:To perform high speed recording corresponding to the density of a pixel by detecting heating elements to be driven on the basis of the distribution of the pixel density of one row to be recorded to judge the heating elements drivable simultaneously and simultaneously driving the heating elements drivable simultaneously each other corresponding to the judge result and driving the heating elements undrivable simultaneously in a time differential manner. CONSTITUTION:A division judge circuit 15 is driven under control on the basis of the clock signal CK from a timing clock generation circuit 10 and the start signal from a CPU 24 to determine whether the respective groups G1-G4 constituting a thermal head 14 are driven by the supply of a current at the same time or in a time differential manner, on the basis of the distribution of the black pixel data during one scanning line and forms division judge data Ln indicating the combinations of groups at the times of simultaneous current supply driving and time differential current supply driving. A PIO 22 is controlled by the CPU 24 and inputs the division judge data Ln from the division judge circuit 15 to output a control signal Sb to a motor driver 18 for driving pulse motors 16, 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a thermal recording device that records information on recording paper by heating with electricity, for example in a digital copying machine or a facsimile machine.

(Prior Art) Generally, a digital copying machine or facsimile machine has an image reading device or an image data receiving device as an image information input means, and an image recording device as a recording means of image information manually inputted from the image information input means. It is composed of devices. As such an image recording apparatus, one employing a thermal recording method or a thermal transfer recording method is used.

Image reading devices such as digital copying machines and facsimile machines read the image of a document using a charge accumulation type image sensor (hereinafter referred to as "rCCD sensor") or a thin film deposition type image sensor for each scanning line. Image recording is performed by converting the read image into binary or multivalued image data and sending this to an image recording device.

Such an image recording apparatus has a recording head configured by arranging a number of heating elements in a line corresponding to the number of pixels to be recorded. Then, image data for one scanning line is supplied to the recording head, and electricity is supplied according to the pixel to selectively generate heat in the heating element, thereby performing recording.

However, since the recording head of the image recording apparatus described above has a limit on the current that can be applied simultaneously, the heating elements arranged in the - row are divided into a plurality of groups, and these stage groups are sequentially driven. (Staggered driving) suppresses the maximum instantaneous current consumption. Since groups of this number of stages are driven sequentially, it takes time to record one line.
The drawback was that high-speed recording was not possible.

(Problems to be Solved by the Invention) This invention suppresses the maximum instantaneous current consumption by dividing the heating elements arranged in a line into a plurality of groups as described above and performing staggered driving. This was developed in order to eliminate the disadvantage that it takes time to record one line and high-speed recording is not possible, and the object is to provide a thermal recording device capable of performing high-speed recording according to pixel density.

[Structure of the Invention] (Means for Solving the Problems) The thermal recording device of the present invention includes a recording head comprising a plurality of heating elements, and when recording with this recording head,
detection means for detecting a driving element among the plurality of heating elements;
A determination means for determining which heating elements can be driven simultaneously based on the distribution of the heating elements detected by the detection means, and
The heating elements determined by the determination means to be able to be driven simultaneously are driven simultaneously, and the heating elements determined to be unable to be driven simultaneously are driven sequentially at different times. There is.

(Function) The present invention detects the heating elements to be driven based on the distribution of pixel density of one column to be recorded and generates the heating elements that can be driven simultaneously when driving the heating elements provided corresponding to the pixels of the - column. The heating elements that can be driven simultaneously are driven simultaneously, and the heating elements that cannot be driven simultaneously are driven in a staggered manner according to the results of this determination. As a result, a large number of heating elements can be driven simultaneously in areas where the pixel density is low, so the number of times of staggered driving can be reduced, making high-speed recording possible.

(Example) An example of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an electric circuit of a thermal recording apparatus of the present invention. In the figure, a timing clock generation circuit 10 generates timing signals that define the operation of each part of the device. The CCD drive circuit 11 is
The CCD sensor 12 is driven in synchronization with the clock signal from the timing clock and clock generation circuit 10. Further, the CCD drive circuit 11 outputs an optical signal accumulation time signal SH that defines the light irradiation time of the CCD sensor 12, that is, the scanning time of one scanning line.

The CCD sensor 12 converts reflected light (not shown) from a document illuminated by a light source into an amount of charge corresponding to the amount of light, and outputs it as an analog voltage. The output voltage of this CCD sensor 12 reflects the read image, and is supplied to the image processing circuit 13 as an image signal Sa.

The image processing circuit 13 corrects low frequency distortion caused by the use of the reduction optical system and high frequency distortion specific to the CCD sensor 12 contained in the image signal Sa output from the CCD sensor 12;
After performing so-called shading correction, the signal is converted into a binary signal.

The binarized image signal VDATA output from the image processing circuit 13 is output to the thermal head 14 and the division determination circuit 15.

The thermal head 14 is a recording head composed of a total of 1728 heating elements, and is divided into four groups G1 to G4, each consisting of 432 heating elements. These four groups 61 to G4 each receive an enable signal EN from the PTC 23, which will be described later.
Each group is independently energized and driven by AI to ENA4. This thermal head 14 is
The image processing circuit 1 operates in synchronization with the clock signal CK from the timing clock generation circuit 10.
Of the image signal VDATA binarized in step 3, the portion corresponding to the heating element group to which the enable signals ENAI to ENA4 are supplied is energized, and the heat generated records an image on the recording paper. . The maximum number of elements that can be simultaneously energized in this thermal head 14 is 44.
8.

The division determination circuit 15 is driven and controlled by the clock signal CK from the timing clock generation circuit 10 and the start signal 5TART from the CPU 24, and divides the thermal head 1 based on the distribution of black pixel data in one scanning line.
In addition to determining whether each group 01 to G4 constituting G4 is to be energized simultaneously or driven in a staggered manner,
This is to generate division determination data Ln that instructs the combination of groups in the case of simultaneous energization drive or staggered energization drive. Details of this division determination circuit 15 will be described later.

The first pulse motor 16 is a drive motor for moving the document in the sub-scanning direction for scanning by the CCD sensor 12 . The second pulse motor 17 is a drive motor for transporting the recording paper recorded by the thermal head 14.

Further, the motor driver 18 is a drive circuit for controlling the drive power of the first pulse motor 16 and the second pulse motor 17.

Further, the rechargeable battery voltage detection circuit 19 detects the voltage of a rechargeable secondary battery, which is the main power source of this device. The thermal rad thermistor temperature detection circuit 20 detects the temperature of the thermal head 14 using a thermistor built into the thermal head 14. Further, the sub-scanning pixel density detection circuit 21 detects the pixel density of the document in the sub-scanning direction. For more information on these,
This will be explained later.

P I 022 is the CPU (central processing circuit) 24
It is a parallel I10 controlled by the input port which inputs each detection signal of the rechargeable battery voltage detection circuit 19, the thermal rad thermistor temperature detection circuit 20, and the sub-scanning pixel density detection circuit 21, and the input port from the division determination circuit 15. An input port for inputting division determination data Ln, an output port for outputting a gate signal for controlling an enable signal to the thermal head 14, a first pulse motor 16 and a second pulse motor.
It has an output port that outputs a control signal sb to a motor driver 18 that drives a pulse motor 17. This control signal sb consists of control commands such as forward rotation, reverse rotation, stop and normal rotation, speed control, etc. of the first pulse motor 16 and the second pulse motor 17.

The AND circuit 25 controls the enable signal of the thermal head 14 outputted by the PI022 according to the optical signal accumulation time SH, and outputs the output signal GATEI~GAT.
E4 is supplied to PTC23. Further, the optical signal accumulation time SH is supplied to an interrupt terminal INT of the CPU 24.

The PTC 23 is a programmable timer counter controlled by the CPU 24, and the AND circuit 25
The thermal head 1 inputs the output signals GATE 1 to GATE 4 and has a predetermined pulse width based on these.
Enable signal E that drives each group 01 to G4 of 4
It generates and sends NAI to ENA4.

FIG. 2 shows the configuration of the division determination circuit 15 in detail. In the figure, the print data transfer lock counter 30 counts the clock signal CK generated by the timing clock generation circuit 10, and starts counting in response to the start signal 5TART output from the CPU 24.
When 432 clock signals CK have been counted, a carry pulse S1 is outputted to return to the initial state, and the same counting operation is repeated. That is, when a number corresponding to 432 heating elements constituting each group of the thermal head 14 has been counted, a carry pulse S1 representing this fact is output.

The first black pixel data counter 32 counts the number of black pixel data included in the image signal VDATA binarized by the image processing circuit 13 at the timing of the clock signal CK. This black pixel data first counter 32 starts counting by the output signal of the three-man AND circuit 31, and outputs a carry pulse S2 when it has counted 448 pieces of black pixel data to stop counting. be. In other words, the maximum number of elements that can be simultaneously energized in the thermal head 14 is 44.
When counting 8, carry pulse S2 indicates that
This outputs the following. The AND circuit 31 includes CP
5TART signal output from U24, NAN described later
Output signal Sll of D circuit 39 and NAND circuit 42
The output signal S14 is inputted, and when any one of these signals is driven, a significant signal is output and the first black pixel data counter 32 starts counting.

The second black pixel data counter 34 is similar to the first black pixel data counter 32 described above.
The number of black pixel data included in the converted image signal VDATA is counted at the timing of the clock signal CK, but the conditions for starting counting are different. That is,
This black pixel data second counter 34 is a two-person AND operation.
Counting is started by the output signal of the circuit 33, and when 448 black pixel data have been counted, a carry pulse s3 is output and counting is stopped. That is, as above, the maximum number of elements that can be simultaneously energized in the thermal head 14 is 448.
When counted, a carry pulse S3 representing that fact is output.

” The first AND circuit 33 includes a NAND circuit 40, which will be described later.
The output signal S12 of the NAND circuit 41 and the output signal 313 of the NAND circuit 41 are input, and when any of these signals is driven, a significant signal is output and the count of the second black pixel data counter 34 is controlled. It is designed to start.

The flip-flop circuit 35 is reset to the initial state by the output signal S16 of the AND circuit 48, and is set when the carry pulse S2 output from the black pixel data first counter 32 is output. In the above-mentioned reset state, the non-inverted output signal S7 is at a low level (hereinafter referred to as "
"L level". ), the inverted output signal S8 is at a high level (
Hereinafter, it will be referred to as "H level". ), and when the carry pulse S2 is supplied, the non-inverted output signal S
7 changes to H level, and the inverted output signal S8 changes to L level.

The flip-flop circuit 36 is reset to the initial state by the output signal S17 of the AND circuit 49, and is set when the carry pulse S3 output from the second black pixel data counter 34 is output. In the reset state, the non-inverted output signal S9 is at the L level and the inverted output signal SIO is at the H level. When the carry pulse S3 is supplied, the non-inverted output signal S9 is at the H level and the inverted output signal S9 is at the H level. The output signal SIO changes to L level.

The OR circuit 37 inputs the non-inverted output signals s7 and s9 of the flip-flop circuits 35 and 36, performs a logical sum, and outputs the result.

The output signal s4 of this OR circuit 37 is transmitted to the shift register 3.
8.

The shift register 38 has, for example, a 4-bit shift capacity, and its parallel output (division determination data) is expressed as Ln, and each bit is expressed as "Ll."

L2. L3. In the shift operation, when expressed as L4J, shift-in data is input to "Ll" and
The data of "L4" is shifted out. That is, the shift register 38 performs a shift operation using the output signal s4 of the OR circuit 37 as shift-in data and the carry pulse S1 of the print data transfer lock counter 30 as a shift pulse. Note that the data shifted out from bit "L4" is lost.

That is, the shift register 38 performs a shift operation and stores the output signal S4 of the OR circuit 37 as shift-in data at the time when the clock signal CK corresponding to the number of heating elements 432 in one group of the thermal head 14 is counted. It is something.

The parallel output of this shift register 38 is supplied to the PI022 as division determination data Ln. The data is then read into the CPU 24 every period of the optical signal accumulation time SH of the CCD sensor 12, and the distribution of black pixel data for each main scanning line is recognized.

The NAND AND circuit 39 inputs the non-inverted output signal S7 of the flip-flop circuit 35 and the output signal S5 of the AND circuit 46, and outputs the output signal Sll from the three-man power AND circuit 3.
1 and AND circuits 43 and 48. In addition, the inverted output signal S8 of the NAND AND circuit 40 and the flip-flop circuit 35 and the output signal S5 of the AND circuit 46 are manually input, and the output signal S12 is
The signal is supplied to the ND circuit 33 and the AND circuit 48.

The NAND circuit 41 inputs the non-inverted output signal S of the flip-flop circuit 36 and the output signal S6 of the AND circuit 47, and supplies the output signal S13 to the AND circuit 33 and the AND circuits 43 and 49. There is. Further, the inverted output signal S10 of the NAND AND circuit 42 and the flip-flop circuit 36 and the output signal S6 of the AND circuit 47 are input, and the output signal S14 is supplied to the three-man-powered AND circuit 31 and the four AND circuits. It has become.

The AND circuit 43 inputs the NAND AND circuit output signal Sll and the NAND circuit output signal S13, performs a logical sum at L level, and supplies the output signal S15 to the flip-flop circuits 44 and 45. It is. Further, the AND circuit 48 is connected to the above NAND
The AND circuit output signal Sll and the above NAND AND circuit output signal S12 are inputted, the logical sum at L level is taken, and the output signal S16 is supplied to the reset terminal of the flip-flop circuit 35, and the above flip-flop circuit 35 is reset. It restores the condition.

Furthermore, the AND circuit 49 outputs the NAND AND circuit output signal S1B and the NAND AND circuit output signal S14.
are input, the logic sum at L level is taken, and the output signal S17 is supplied to the reset terminal of the flip-flop circuit 36, thereby returning the flip-flop circuit 36 to the reset state.

The flip-flop circuit 44 performs a toggle operation based on the output signal S15 of the AND circuit 43, and its output signal is supplied to the AND circuit 46. This flip-flop circuit 44 has an H level as an initial state.
The level is now set. Similarly, the flip-flop circuit 45 performs a toggle operation based on the output signal S15 of the AND circuit 43, and its output signal is supplied to the AND circuit 47. This flip-flop circuit 45 is set to the L level as an initial state. Therefore, the flip-flops 44 and 45 always output signals of opposite levels.

The AND circuit 46 receives the carry pulse S1 of the print data transfer lock counter 30 and the output signal of the flip-flop circuit 44, and generates an output signal S5 by performing a logical product. This signal S5 is supplied to the NANDAND circuit and 40. The AND circuit 47 receives the carry pulse S1 of the print data transfer lock counter 30 and the output signal of the flip-flop circuit 45, and generates an output signal S6 by performing a logical product. This signal S6 is supplied to the NANDAND circuit and 42.

Next, the operation in the above configuration will be explained.

First, when an image reading device (not shown) starts reading and scanning a document, reflected light from the irradiated document is imaged on the CCD sensor 12 by an optical system (not shown). In such a state, the CCD sensor 12 outputs the amount of charge accumulated according to the amount of reflected light as an analog voltage.

As shown in FIG. 1, this analog voltage is converted into time-series data by a control signal from a COD drive circuit 11 that operates in synchronization with a timing signal supplied from a timing generation circuit 10, and is converted into time-series data as an image signal Sa. The signal is supplied to the processing circuit 13.

The image processing circuit 13 performs image correction such as shading correction on the received image signal Sa, and then converts it into binary data of white pixels and black pixels by slicing it at a predetermined slice level voltage. This binarized image signal VDATA is supplied to the division determination circuit 15 and the thermal head 14 in synchronization with the clock signal CK supplied from the timing clock generation circuit 10.

Next, the operation of the division determination circuit 15 to which the image signal VDATA is supplied will be explained with reference to the timing charts of FIGS. 3 and 4. FIG. 3 is a timing chart showing the operation when the CCD sensor 12 reads all black data, and FIG. 4 is a timing chart showing the operation when black data is concentrated in the center of the document. be.

First, the operation when all black data shown in FIG. 3 is read will be described. As shown in FIG. 2(a), the CPU 24
The 5TART signal is output from the print data transfer lock counter 30, whereby the print data transfer lock counter 30 starts counting the number of pulses of the clock signal GK (see FIG. 3(b)). . At the same time, the 5TART signal is supplied to the black pixel data first counter 32 via the three-man AND circuit 31, so that the black pixel data first counter 32 receives the image that is supplied in synchronization with the clock signal CK. Counting of black pixel data in the signal VDATA (see FIG. 3(c)) is started.

Incidentally, in the example shown in FIG. 3, the input image signal V
Since all DATA is black pixel data (indicated by diagonal lines), the same counting as that of the print data transfer lock counter 30 is performed. Incidentally, FIG. 3(e) shows the time zone in which the first black pixel data counter 32 is performing a counting operation with an H level signal.

As described above, when the print data transfer lock counter 30 counts 432 clock signals CK, it outputs a carry pulse S1 and sets the count value to the initial value, as shown in FIG. 3(d). and restart the counting operation similar to the above.

In other words, the operation of generating a pulse every time 432 clock signals CK are counted is repeated. Since the number of pixels in one scanning line is 1728, the print data transfer lock counter 30 generates four pulses while transferring the image signal VDATA of one scanning line.

Here, the operation at point A in FIG. 3, that is, when the first carry pulse S1 occurs, will be described. As described above, when the print data transfer lock counter 30 counts 432 clock signals CK, the carry pulse S1 is output, but at this time, the carry pulse S2 from the black pixel data first counter 32 is output. and black pixel data second
None of the carry pulses S3 from the counter 34 have been output yet, and the flip-flop circuits 35 and 36
Both are in a reset state. Therefore, the non-inverted output signal S of these flip-flop circuits 35 and 36
7 and S9 are both at the L level, and the OR circuit 37
The output signal S4 of is also at L level. Therefore, the shift register 38 uses the L level output signal S4 from the OR circuit 37 as shift-in data, and uses the carry pulse S4 as shift-in data.
Since a 1-bit shift operation is performed using 1 as a shift clock, the parallel output, that is, the division judgment data Ln
, 4-bit data of "Ln-L, *, *, *J" is output. Here, the symbol "*" indicates that an undefined value is output.

On the other hand, the carry pulse S1 is generated by the AND circuits 46 and 47.
is supplied to one input terminal of each. At this time, the flip-flop circuit 44, which maintains the initial state, is set to H level and the flip-flop circuit 45 is set to L level, so the AND circuit 46 passes the carry pulse S1 and outputs the signal S5. However, since the AND circuit 47 prevents the carry pulse S1 from passing, the signal S6 remains at the L level.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, as described above, the black pixel data first counter 32
The count value is the same count value as the print data transfer lock counter 30, and it has not yet counted 448 pieces, so the carry pulse S2 has not been output, and the flip-flop circuit 35 is also in the reset state. Therefore, the non-inverted output signal S7 remains at L level and the inverted output signal S8 remains at H level. Therefore, NAND circuit 3
The output signal S11 of No. 9 remains at H level,
This does not affect the operation of the circuits in the next stage and subsequent stages, and the set state of each flip-flop circuit 44, 45 and the operating state of the first black pixel data counter 32 do not change. on the other hand,
As the output signal S12 of the NAND circuit 40, a pulse signal S12 having substantially the same phase as the carry pulse S1 is output. By supplying this signal S12 to the second black pixel data counter 34 via the AND circuit 33, the second black pixel data counter 34 is reset to the initial value and then supplied in synchronization with the clock signal CK. Image signal VDAT
Start counting the black pixel data in A. That is, counting of black pixel data is started from the beginning of the area corresponding to the heating element group of group G2 of the thermal head 14. FIG. 3(g) shows a time period in which the second black pixel data counter 34 is performing counting operation by an H level signal.

Further, the signal S12 is supplied to the AND circuit 48, so that the carry pulse S16 is outputted from the AND circuit 48.
A pulse signal having substantially the same phase as 1 is output. Then, by supplying this signal S16 to the flip-flop circuit 35, the flip-flop circuit 35 is reset to the initial state.

Note that the reset operation at this point has no particular meaning since the flip-flop circuit 35 is already in the reset state.

Further, as described above, the output signal S6 of the AND circuit 47
remains at the L level, so the output signals 313 and S14 of the NAND circuits 41 and 42 remain at the H level, and do not affect the operation of the circuits in the next stage onward, and each flip-flop circuit 35.36
．． 44.45 set state and each counter 30.32
．． The operating state of 34 is subject to change.

Next, point B in FIG. 3, that is, the black pixel data first counter 3
The operation when the carry signal S2 from 2 is generated will be explained. The black pixel data first counter 32 starts counting at the same time as the print data transfer lock counter 30.
generates a carry pulse S2 as shown in FIG. 3(f) by counting 448 pieces of black pixel data in the manually inputted image signal VDATA. And Figure 3 (e
), stop the counting operation.

Then, by supplying the first carry pulse S2 to the flip-flop circuit 35, the flip-flop circuit 35 enters a set state, and its non-inverted output signal S7 is at H level, and its inverted output signal S8 is at L level. is output. This set state is maintained until the output signal S16 from the AND circuit 48 is driven.

At the time when the flip-flop circuit 35 is set, the second black pixel data counter 34 is in a counting state;
The 448 black pixel data have not yet been counted, and the output signal S3 remains at the L level. Therefore, the flip-flop circuit 36 maintains its initial state, that is, the reset state, and its non-inverted output signal S9 remains at L level and its inverted output signal S10 remains at H level.

Therefore, one input signal S7 of the OR circuit 37 changes to H level, and the other input signal S9 remains at L level, so that the output signal S4 is as shown in FIG. 3(i).
The signal changes to an H level as shown in FIG. At this time, the carry signal S1 remains at the L level, so the signals S5 and S6 also remain at the L level, and the output signals Sll, S12, and
Both S13 and S14 remain at the H level, and do not affect the operation of the circuits at the next stage and thereafter.

Therefore, each flip-flop 35.36, 44.4
5 does not change, and each counter 30, 32, 34 does not return to its initial state.

Next, an explanation will be given of the operation when the state changes as described above and reaches the 0 point in FIG. 3, that is, when the second carry pulse S1 occurs. When the print data transfer lock counter 30 counts 864 clock signals CK, the second carry pulse S1 is output, but at this time, the flip-flop circuit 35 is in the set state and the flip-flop circuit 36 is reset. in a state. Therefore, the non-inverted output signal S7 of the flip-flop circuit 35
is at the H level, and the non-inverted output signal S9 of the flip-flop circuit 36 is at the L level, so the output signal S4 of the OR circuit 37 is at the H level.

The shift register 38 uses the H level output signal S4 from the OR circuit 37 as shift-in data, performs a 1-bit shift operation using the carry pulse S1 as a shift clock, and outputs the parallel output, that is, the division determination data L.
rLn-H as n.

Outputs 4-bit data of L, *, *J. here·
, the information output as an H level signal to bit L1 is until the carry pulse S1 is output twice, that is, black pixel data is present in the range corresponding to the heating elements of groups G1 and G2 of the thermal head 14. This means that 448 or more heating elements have appeared, which means that the heating elements of group G1 and the heating elements of group G2 cannot be energized and driven at the same time.

On the other hand, the carry pulse S1 is generated by the AND circuits 46 and 47.
is supplied to one input terminal of each. At this time, the flip-flop circuit 44 is at H level, and the flip-flop circuit 45 is at H level.
remains in its initial state set to L level, so
The AND circuit 46 passes the carry pulse S1 and outputs the signal S5, but the AND circuit 47 prevents the carry pulse S1 from passing, so the signal S6 remains at L level.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, the flip-flop circuit 35 is in a set state,
Since the signal S7 is output at H level, the signal S5 is inverted and passes through the NAND circuit 39, and is output as the signal S11. This signal Sll is an AND circuit 3 powered by three people.
1 to the black pixel data first counter 32, the black pixel data first counter 32 returns its set state to the initial value, and then outputs the image supplied in synchronization with the clock signal CK. Counting of black pixel data in signal VDATA is restarted.

That is, counting of black pixel data is started from the beginning of the area corresponding to the heating element group of group G3 of the thermal head 14. Furthermore, the signal S11 is supplied to the flip-flop circuits 44 and 45 via the AND circuit 43, so that the flip-flop circuits 44 and 45 are inverted, respectively, and the flip-flop circuit 44 is at L level.
Flip-flop circuit 45 outputs an H level signal. Further, the signal Sll is supplied to the flip-flop circuit 35 via the AND circuit 48, so that the flip-flop circuit 35 is placed in a reset state.

On the other hand, since the inverted output signal S8 of the flip-flop circuit 35 is at the L level, the output of the NAND circuit 40 remains at the H level, and does not have any influence on the operation of the circuits in the subsequent stages.

Further, as described above, the output signal S6 of the AND circuit 47
remains at the L level, output signals S13 and S14 of the NAND circuits 41 and 42 remain at the H level, and do not affect the operation of the subsequent stages.

Next, the operation at point D in FIG. 3, that is, when the carry signal S3 from the black pixel data second counter 34 is generated, will be described. The second black pixel data counter 34, which started counting by the first carry pulse S1, counts 448 black pixels in the input image signal VDATA, as shown in FIG. 3(h). , a carry pulse S3 is generated. Then, as shown in FIG. 3(g), the counting operation is stopped.

Then, by supplying the first carry pulse S3 to the flip-flop circuit 36, the flip-flop circuit 36 enters a set state, and its non-inverted output signal S9 is at H level, and its inverted output signal SIO is at L level. is output. This set state is maintained until the output signal S17 from the AND circuit 49 is driven.

At the time when the flip-flop circuit 36 is set, the black pixel data first counter 32 is in the counting state;
The 448 black pixel data have not yet been counted, and the output signal S2 remains at the L level. Therefore, the flip-flop circuit 35 maintains the reset state,
The non-inverted output signal S7 is at L level, and the inverted output signal S8
is maintained at H level.

Therefore, one input signal S7 of the OR circuit 37 remains at the L level, and the other input signal S9 changes to the H level, so that the output signal S4 is as shown in FIG. 3(i). The signal changes to H level. At this time, the carry signal S1 remains at the L level, so the signal S1
5 and S6 also remain at L level, and the NAND circuit 3
9.40.41.42 each output signal Sll, S12, S
13 and S14 all remain at H level, and do not affect the operation of the circuits at the next stage and thereafter.

Therefore, each flip-flop 35.36.44.4
5 does not change, and each counter 30, 32', 34 does not return to its initial state.

Next, a description will be given of the operation when the state progresses as described above and reaches point E in FIG. 3, that is, when the third carry pulse S1 is generated. When the print data transfer lock counter 30 counts 1296 clock signals CK, the third carry pulse S1 is output, but at this time, the flip-flop circuit 35 is in the reset state and the flip-flop circuit 36 is in the set state. in a state. Therefore, the non-inverted output signal S of the flip-flop circuit 35
7 is at the L level, and the non-inverted output signal S9 of the flip-flop circuit 36 is at the H level, so the output signal S4 of the OR circuit 37 is at the H level. The shift register 38 uses the H level output signal S4 from the OR circuit 37 as shift-in data, performs a 1-bit shift operation using the carry pulse S1 as a shift clock, and uses its parallel output, that is, the division determination data Ln. As, rLn-
Outputs 4-bit data: H, H, L, *J. Here, the information output as an H level signal to bit L1 is from the time when the first carry pulse S1 is output until the third time when the carry pulse S1 is output, that is, the information between group G2 and group G3. This means that 448 or more black pixel data have appeared in the range corresponding to the heating element, and this means that the heating element group of group G2 and the heating element group of group G3 cannot be energized and driven at the same time. do.

On the other hand, the carry pulse S1 is generated by the AND circuits 46 and 47.
Sweat is supplied to each one input terminal. At this time, the flip-flop circuit 44 is at L level, and the flip-flop circuit 45 is at L level.
is set to H level, the AND circuit 47 passes the carry pulse S1 and outputs the signal S6, but the AND circuit 46 prevents the carry pulse S1 from passing, so the signal S5 goes to the L level. remains maintained.

The output signal S6 from the AND circuit 47 is supplied to one input terminal of each of the NAND circuits 41 and 42. At this time, the flip-flop circuit 36 is in a set state,
Since the signal S9 is output at H level, the signal S6 is inverted and passes through the NAND circuit 41, and is output as the signal S13. By supplying this signal 313 to the second black pixel data counter 34 via the AND circuit 33, the second black pixel data counter 34 returns its set state to the initial value and then synchronizes with the clock signal CK. Then, counting of black pixel data in the image signal VDATA that is supplied is restarted.

That is, counting of black pixel data is started from the beginning of the area corresponding to the heat generating element group of group 4 of the thermal head 14. Further, the signal S13 is supplied to the flip-flop circuits 44 and 45 via the AND circuit 43, so that they are inverted, and the flip-flop circuit 44 outputs an H-level signal, and the flip-flop circuit 45 outputs an L-level signal. Furthermore, the signal S13 is outputted to the AND circuit 49.
By being supplied to the flip-flop circuit 36 via the flip-flop circuit 36, the flip-flop circuit 36 is placed in a reset state.

On the other hand, since the inverted output signal SIO of the flip-flop circuit 36 is at the L level, the output of the NAND circuit 42 is high.
The level remains unchanged and does not affect the operation of subsequent circuits.

Further, as described above, the output signal S5 of the AND circuit 46
Since NAND circuits 39 and 40 maintain the L level, the outputs of the NAND circuits 39 and 40 remain at the H level, and do not affect the operation of the circuits in the subsequent stages.

Next, in the same manner as described above, a carry pulse S2 is output from the black pixel data first counter 32 which started counting operation with the second carry pulse S1, and the flip-flop circuit 3
The operation when the value 5 is set and reaches point F, that is, when the fourth carry pulse S1 is generated, will be described. Print data transfer lock counter 3o
counted 1728 clock signals CK, resulting in 4
The carry pulse S1 is output for the second time, but at this time, the flip-flop circuit 35 is in a set state and the flip-flop circuit 36 is in a reset state.

Therefore, the non-inverted output signal S7 of the flip-flop circuit 35 is at H level, the non-inverted output signal S9 of the flip-flop circuit 36 is at L level, and the OR circuit 3
The output signal s4 of No. 7 is at H level. shift register 3
8 uses the H level output signal S4 from the OR circuit 37 as shift-in data, performs a 1-bit shift operation using the carry pulse s1 as a shift clock, and outputs rLn as its parallel output, that is, division determination data Ln.
= Outputs 4-bit data of H, H, H, LJ. Here, the information output as a high level signal to bit L1 is from the time when the second carry pulse S1 is output until the fourth time when the carry pulse S1 is output, that is, when the thermal head 14 This means that 448 or more pieces of black pixel data have appeared in the range corresponding to the heating elements of groups G3 and G4, and this means that the heating elements of group G3 and the heating elements of group G4 are simultaneously energized and driven. means that it cannot be done.

On the other hand, the carry pulse S1 is generated by the AND circuits 46 and 47.
is supplied to one input terminal of each. At this time, the flip-flop circuit 44 is at H level, and the flip-flop circuit 45 is at H level.
is set to L level, the AND circuit 46 passes the carry pulse S1 and outputs the signal S5, but the AND circuit 47 blocks the pass of the carry pulse S1, so the signal S6 is It remains at L level.

The output signal S5 from the AND circuit 46 is supplied to one input terminal of each of the NAND circuits 39 and 40. At this time, the flip-flop circuit 35 is in a set state,
Since the signal S7 is output at H level, the signal S5 is inverted and passes through the NAND circuit 39, and is output as the signal Sll. This signal S11 is an AND circuit 3 powered by three people.
1 to the black pixel data first counter 32, the black pixel data first counter 32 returns its set state to the initial value, and then outputs the image supplied in synchronization with the clock signal CK. Counting of black pixel data in signal VDATA is restarted.

Furthermore, the signal Sll is supplied to the flip-flop circuits 44 and 45 via the AND circuit 43, so that they are inverted, and the flip-flop circuit 44 outputs an L level signal and the flip-flop circuit 44 outputs an H level signal. Further, the signal S11 is supplied to the flip-flop circuit 35 via the AND circuit 48, so that the flip-flop circuit 35 is placed in a reset state.

On the other hand, since the inverted output signal S8 of the flip-flop circuit 35 is at the L level, the output of the NAND circuit 40 remains at the H level and does not affect the operation of the circuits at the next stage and subsequent stages.

Further, as described above, the output signal S6 of the AND circuit 47
Since the NAND circuits 41 and 42 maintain the L level, the outputs of the NAND circuits 41 and 42 maintain the H level, and do not affect the operation of the circuits in the next stage and thereafter.

Through the above operations, the division determination circuit] 5 generates division determination data rLn-H, H,
H and LJ are obtained. Bit L4 of the division determination data Ln always has a value of L level and is meaningless as information.

Next, FIG. 4 shows a timing chart showing the operation when black data is concentrated in the center of the document. The operation of each circuit is based on carry pulses S2 and S from the black pixel data first counter 32 and the black pixel data second counter 34.
This is the same as the case of FIG. 3 described above, except that the timing at which 3 is generated is later than in the case of the all-black data, so the explanation will be omitted. Division determination data Ln in this case
As shown in the figure, rLn-L, H, L, and LJ are obtained. Similarly, the division determination data Ln for an all-white original is obtained as rLn-L, L, L, and LJ.

The division determination data Ln obtained from the division determination circuit 15 in this way represents information on the combinations of the groups 61 to G4 of heating elements that can be driven with electricity at the same time, and represents, for example, the division drive in the form shown in the table below. At the same time, the interval at which the document and recording paper are conveyed in the sub-scanning direction according to the number of divisions, that is, the interval at which the first pulse motor 16 and the second pulse motor 17 are driven is determined.

First, the operation when recording all-white data will be explained. When an all-white document is read, the division determination data Ln output from the division determination circuit 15 is rLn-L, L, L.
, becomes LJ. This division determination data Ln is PIO2'
) is supplied to the CPU 24. As shown in Table 1, the CPU 24 determines that the division determination data Ln corresponds to the division mode shown in FIG. 5, and determines that the conveyance interval of the recording paper in the sub-scanning direction is rTJ time.

Next, the CPU 24 simultaneously outputs the energization division control signals of all H level corresponding to the division determination data Ln to Pr022 via the data bus, and furthermore,
22 to one input of an AND circuit 25. AN
The other input of the D circuit 25 receives the optical signal accumulation time signal SH.
is input, and its output signal GATEI~GATE
4, as shown in FIG. 9, the optical signal accumulation time signal SH
The signal with the same phase appears as is. These signals GAT
By supplying EI to GATE4 to the gate terminal of the PTC 2B, the PTC 23 receives four enable signals E in the same phase and having a predetermined pulse width, as shown in FIG.
Outputs NAI to ENA4. This enable signal EN
By supplying AI to ENA4 to each group 01 to G4 of the full head 14, the heating elements of the thermal head 14 are energized all at once.

Further, the CPU 24 determines that the conveyance interval of the recording paper in the sub-scanning direction is rTJ time, and as shown in FIG.
By supplying the motor driver 18 via 2,
First pulse motor 16 and second pulse motor 17
The excitation switching control is performed to perform rotational drive.

Next, the operation when recording a document in which black pixel data is concentrated in the center of the document will be described.

In this case, as described above, the division determination data Ln output from the division determination circuit 15 is rLn-L, H, L,
Becomes LJ. This division determination data Ln is supplied to the CPU 24 via the PIO 22. As shown in Table 1, the CPU 24 determines that the division determination data Ln has the division mode shown in FIG. '2T
” is determined to be the time.

Next, the CPU 24 outputs the energization division control signal corresponding to the division determination data Ln to the PI 022 via the data bus, and further outputs the energization division control signal corresponding to the division determination data Ln to the AND circuit 2 from this PI 022.
5 to one input. At this time, since bit L1 is at L level, signals GATEI and GATE2 are simultaneously applied, and since bit L2 is at H level, signals GATE2 and GATE3 are time-shifted, and since bit L3 is at L level, signals GATE3 and GATE4 will be at the same time
Control the output timing as follows. The other input of the AND circuit 25 receives the signal SH, and the 10th
As shown in the figure, when the first signal SH is output, a signal with the same phase as the signal SH is output to GATEI and GATE2, and when the second signal SH is output, a signal with the same phase as the signal SH is output to GATEI and GATE2.
A signal having the same phase as the signal SH is output to TE3 and GATE4. These signals GATEI to GATE4 are PTC23
By being supplied to the gate terminal of PTC23,
As shown in FIG. 10, two enable signals ENAI and ENA2 of the same phase and having a predetermined pulse width, and two enable signals ENA3 and ENA4 of the same phase and having a predetermined pulse width different in phase from these are successively generated. Output with . By supplying these enable signals ENAI to ENA4 to the groups 01 to G4 of the thermal head 14, respectively, the heating elements of groups G1 and 62 of the thermal head 14 are activated simultaneously, and then after a time period of the signal SH, the thermal head is activated. The heating elements of 14 groups G3 and 04 are simultaneously driven with staggered energization.

Further, the CPU 24 determines that the conveyance interval of the recording paper in the sub-scanning direction is "2T" time, and as shown in FIG.
22 to the motor driver 18, the first pulse motor 16 and the second pulse motor 1
The excitation switching control of 7 is performed to perform rotational drive. This means that it takes twice as long to record one line as compared to the case of all white data.

Next, the division determination data Ln is rLn-H,H.

The operation in the case of L and LJ will be explained. The division determination data Ln output from the division determination circuit 15 is PI022
It is supplied to the CPU 24 via.

As shown in Table 1, the CPU 24 determines that the division determination data Ln has the division mode shown in FIG. It is determined that the time is "3T".

Next, the CPU 24 outputs the energization division control signal corresponding to the division determination data Ln to the PI 022 via the data bus, and further outputs the energization division control signal corresponding to the division determination data Ln to the AND circuit 2 from this PI 022.
5 to one input. At this time, since bit L1 is at H level, signals GATEI and GATE2 are time-shifted, and since bit L2 is at H level, signal G
Both ATE2 and GATE3 have different times, and bit L3
Since GATE3 and GATE4 are at the L level, the output timings are controlled so that the signals GATE3 and GATE4 are output at the same time.

The signal SR is input to the other input of the AND circuit 25, and as shown in FIG.
When H is output, only the GATEI signal is output, when the second signal SH is output, only the GATE2 signal is output, and when the third signal SH is output, the GATEI signal is output.
Signals of the same phase are output to ATE3 and GATE4.

By supplying these signals GATE 1 to GATE 4 to the gate terminal of PTC 23, PTC 2B
As shown in Figure 1, an enable signal ENAI having a predetermined pulse width, an enable signal ENA2 having a predetermined pulse width different in phase from this, and an enable signal ENA2 having a predetermined pulse width different in phase from the enable signal ENAI, and an enable signal ENAI having a predetermined pulse width different in phase from the enable signal ENAI. Two enable signals ENA3
and ENA4 are output one after another. These enable signals ENAI to ENA4 are applied to the thermal head 14, respectively.
are supplied to each group 61 to G4 of the thermal head 14, so that the heating elements of the group G1 of the thermal head 14 are simultaneously supplied, and then after the signal SH time, the heating elements of the group G2 are simultaneously supplied, and then after the signal SR time, the heating elements of the thermal head 14 are supplied. The heating elements of groups G3 and 04 are simultaneously driven with staggered energization.

Further, the CPU 24 determines that the conveyance interval of the recording paper in the sub-scanning direction is "3T" time, and as shown in FIG.
22 to the motor driver 18, the first pulse motor 16 and the second pulse motor 1
The excitation switching control of 7 is performed to perform rotational drive. This means that it takes three times as long to record one line as compared to the case of the blank space data.

Next, the operation when recording all black data will be explained. In this case, as described above, the division determination data Ln output from the division determination circuit 15 is rLn-H, H,
It becomes H, LJ. The division determination data Ln output from the division determination circuit 15 is sent to the CPU 24 via the PI022.
supplied to

As shown in Table 1, the CPU 24 determines that the division determination data Ln has the division mode shown in FIG. It is determined that the time is "4T".

Next, the CPU 24 sends the energization division control signal corresponding to the division determination data Ln to P1022+ via the data bus.
, : Output, and further 1. :, (7) P4O10 to AN
It is supplied to one input of the D circuit 25. At this time, bit L
1 is at H level, the signals GATEi and GATE2
Since bit L2 is at H level with a time shift, signals GATE2 and GATE3 are also time shifted and bit L3 is at an H level, so signals GATE3 and GATE3 are at a H level.
The timing of TE4 is also controlled so that the output is staggered. The other input of the AND circuit 25 receives the signal S
As shown in FIG. 12, when the first signal SH is output, only the GATEI signal is output, and when the second signal SH is output, the GATE2 signal is input.
When only the signal is output, when the third signal SH is output, only the GATE3 signal is output, and when the fourth signal SH is output, only the GATE4 signal is output. By supplying these signals GATEI to GATE4 to the gate terminal of the PTC 23, the PTC 23 receives an enable signal ENAI having a predetermined pulse width and a predetermined pulse having a different phase from this ENAI, as shown in FIG. an ENA 2 having a pulse width; an ENA 3 having a predetermined pulse width different in phase from the ENA 2;
Enable signals ENA4 having predetermined pulse widths with different phases are sequentially output. These enable signals EN
By supplying AI to ENA4 to each group 01 to G4 of the thermal head 14, each heating element of the groups G1, G2, G3, and G4 of the thermal head 14 is energized at different times by shifting the waiting time of the signal SH. Driven.

Further, the CPU 24 determines that the conveyance interval of the recording paper in the sub-scanning direction is "4T" time, and as shown in FIG.
22 to the motor driver 18, the first pulse motor 16 and the second pulse motor 1
The excitation switching control of 7 is performed to perform rotational drive. This means that it takes four times as long to record one line as compared to the case of all white data.

As explained above, when the thermal head 14 is energized and driven, it is possible to divide the thermal head 14 into four groups and drive the thermal head 14, while detecting the distribution of black pixel data in one scanning line. According to this detection result, the above groups are simultaneously driven within a range that does not exceed the maximum number of elements that can be simultaneously energized, and if the maximum number of elements that can be energized simultaneously is exceeded, staggered energization is performed at different times, so that the thermal head 14 It is possible to reduce the size and capacity of the drive power source, and to overcome the drawback that the recording speed (corresponding to the printing speed of all black areas in the above embodiment) cannot be improved by simple staggered energization as in the conventional method. This problem has been resolved, and high-speed printing is now possible depending on the pixel data that appears. Furthermore, since the division determination data is generated by hardware and the intervention of software is minimized, the time required for recording can be shortened.

In the above embodiment, a case has been described in which the thermal head 14 is divided into four groups and driven with staggered energization. However, the number of divisions is not limited to four, and any number of divisions other than the above may be used. also produces the same effect.

Next, details of the rechargeable battery voltage detection circuit 19 will be explained. In FIG. 13, a rechargeable secondary battery 40 is the main power source of the device and generates power to be supplied to each part of the device. The output of this rechargeable secondary battery 40 is supplied to a stabilizing circuit 41. Stabilization circuit 4
1 eliminates unstable voltage fluctuations specific to the rechargeable secondary battery 40 and enables stable voltage supply.

The voltage detection circuit 42 also includes an operational amplifier OPI and a resistor R.
1 and R2. This voltage detection circuit 4
The output of operational amplifier OPI No. 2 is supplied to an A/D converter 43.

The A/D converter 43 converts the analog signal output from the operational amplifier OPI into a digital signal and supplies the digital signal to the PIO 22.

The rechargeable battery voltage detection circuit 19 configured as described above operates as follows. That is, the rechargeable secondary battery 40
The output is supplied to the stabilizing circuit 41, while being divided by resistors R1 and R2 and supplied to the non-inverting input terminal of the operational amplifier OP1.

This operational amplifier OPI constitutes a voltage follower, removes the influence from the previous stage, and supplies the voltage divided by the resistors R1 and R2 to the A/D conversion circuit 43. The A/D conversion circuit 43 converts the above voltage into a digital signal and outputs it as PI0.
Output to 22. The signal from this PIO 22 is then supplied to the CPU 24 via the data bus. CPU2
4, for example, when it is detected that the voltage of the rechargeable secondary battery 40 has dropped, the time for energizing the heating element of the thermal head 14, that is, the pulse width of the enable signal, is lengthened in accordance with the voltage drop value. The printing density determined by the product of the applied voltage and the energization time is controlled to be kept constant.

Next, details of the thermistor temperature detection circuit 20 will be explained. In FIG. 13, a thermistor 50 is built into the thermal head 14 and indirectly detects the temperature of the heating element. The output of this thermistor 50 is supplied to the non-inverting input terminal of the operational amplifier OP2. The operational amplifier OP2 converts the amount of change in the resistance value of the thermistor 50 with respect to temperature into a voltage magnitude, and outputs the voltage to the A/D converter 51. The A/D converter 51 is
The analog signal output from the operational amplifier OP2 is converted into a digital signal and supplied to the PI022. The signal from this PIO 22 is supplied to the CPU 24 via the data bus, and is monitored by the CPU 24. The CPU 24 calculates the optimum energization time, that is, the pulse width of the enable signal, in accordance with the detected temperature of the heating element in the thermal head 14, and controls the moving speed of the recording paper in the sub-scanning direction based on this. It has become. That is, if the heat generating element is already at a temperature above a certain level, a temperature sufficient for recording can be obtained in a short energization time.

Conversely, if the temperature is below a certain level, the current application time must be increased to obtain a temperature sufficient for recording.

In this way, uneven printing can be prevented by controlling the energization time, that is, the pulse width of the enable signal, according to the temperature of the heating element of the thermal head 14, and when the heating element is in a high temperature state and the energization time can be shortened. is capable of high-speed recording.

Furthermore, details of the sub-scanning pixel density detection circuit 21 will be explained. In FIG. 13, the black pixel data counter 60
is for counting the image signal VDATA for one scanning line output from the image processing circuit 13 in synchronization with the clock signal CK.

The memory 61 is composed of, for example, a dual port RAM, and stores the value counted by the black pixel data counter 60, and at the same time outputs the already stored number of black pixel data of one line before to the comparator 62. It is something to do.

The comparator 62 inputs the number of black pixel data counted by the black pixel data counter 60 to one input terminal A, and inputs the number of black pixel data counted by the black pixel data counter 60 to the memory 61.
Manually input a small number of black pixel data from one line before output to the other input terminal B, and compare A>B, A-B,, A<B.
The three signals output from each terminal of the PI022 are supplied to the PI022.

Next, the operation of the sub-scanning pixel density detection circuit 21 will be explained. First, recording for one scanning line is started by sending out the 5TART signal from the CPU 24, and the black pixel data counter 60 receives the image signal sent out from the image processing circuit 13 in synchronization with the clock signal CK. Start counting the black pixel data included in VDATA. When the counting for one scanning line is completed, it is sent to the memory 61 and stored therein, and at the same time, it is supplied to the A input terminal of the comparator 62. On the other hand, the memory 61 outputs the number of black pixel data one line before, and is supplied to the B input terminal of the comparator 62.

From the output terminal of the comparator 62, the comparison result is A>B, A-
It is output as three signals of B and A<B and supplied to the CPU 24 via the PI022.

When the CPU 24 detects that the above comparison result is A>B, that is, the number of black pixel data in the current line is larger than the number of black pixel data in the previous line, it determines that the black pixel data in the image signal VDATA is increasing. , shorten the energization time to the thermal head 14. That is, the pulse width of the enable signals ENAI to ENA4 for driving the thermal head 14 is shortened.

Further, when it is detected that the above comparison result is A<B, that is, the number of black pixel data in the current line is smaller than the number of black pixel data in the previous line, it is determined that the black pixel data in the image signal VDATA is decreasing, To lengthen the energization time to the thermal head 14. In other words, the pulse width of the enable signals ENAI to ENA4 for driving the thermal head 14 is lengthened.

Also, if the above comparison result is A-B, that is, if the number of black pixel data in the current line is equal to the number of black pixel data in the previous line, it is determined that the black pixel data in the image signal VDATA has not changed. , the energization time to the thermal head 14 remains the same as before. In other words, the thermal head 14
The pulse widths of the driving enable signals ENAI to ENA4 are not changed.

In this way, by changing the energization time of the heating element of the thermal head 14 according to the change in pixel density in the sub-scanning direction, it is possible to provide the energization time corresponding to the image density, thereby preventing image density unevenness. -As well as being able to
Since excessive power is not supplied, efficient power control is possible. In addition, high-speed recording is possible if the energization time is short.

[Effects of the Invention] As detailed above, according to the present invention, since the thermal element group is driven in a staggered manner according to the pixel density, it is possible to provide a thermal recording device capable of high-speed recording. .

[Brief explanation of the drawing]

The figures show one embodiment of the present invention, in which FIG. 1 is a block diagram schematically showing the configuration of an electric circuit, FIG. 2 is a diagram showing the detailed circuit configuration of a division determination circuit, and FIGS. Figure 4 is a timing chart for explaining the operation of the division determination circuit, Figures 5 to 8 are explanatory diagrams for explaining divisional driving of the thermal head, and Figures 9 to 12 are diagrams for explaining divisional driving of the thermal head. FIG. 13 is a diagram showing detailed configurations of a rechargeable battery voltage detection circuit, a thermal head thermistor temperature detection circuit, and a sub-scanning pixel density detection circuit. 10...timing clock generation circuit, 12...C
CD sensor, 13... Image processing circuit, 14... Thermal head (recording head), 15... Division determination circuit (detection means, determination means), 16.17... Pulse motor,
18...Motor driver, 22...PIO123.
...PTC, 24...CPU (time difference drive means). Applicant's agent Patent attorney Takehiko Suzue SH Figure Figure SH Figure Figure Figure

Claims (1)

[Scope of Claims] A recording head comprising a plurality of heat generating elements; a detection means for detecting a drive element among the plurality of heat generating elements when recording is performed by the recording head; and heat generation detected by the detection means. A determining means for determining which heating elements can be driven simultaneously based on the distribution of the elements, and heating elements determined by this determining means to be able to be driven simultaneously are driven simultaneously, and heating elements determined to be unable to be driven simultaneously are driven simultaneously. 1. A thermal recording device comprising: a time difference drive means for sequentially driving the elements at different times.