JP2965350B2 - Error correction device for image sensor - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error correction device for an image sensor, and more particularly, to an image sensor for correcting errors of even and odd bits of an image sensor, errors caused by temperature changes, and the like. The present invention relates to a sensor error component correction device.

(Prior Art) The output of an image sensor includes a DC component offset and a dark output. If this image sensor output is processed by a DC coupling circuit and is used as image information,
Unless the DC component offset and dark output are removed, accurate image information cannot be obtained.

With reference to FIG. 7, a configuration of an example of a conventional image sensor will be described.

This image sensor includes a sensor unit 1 and two registers 2, 3, which are configured by ICs.

The sensor unit 1 includes a dummy area whose surface is treated so that light does not enter, and an effective area for reading image information of a document.

The register 2 collectively transfers the odd-numbered bits of the sensor unit 1 and serially reads out the odd-numbered pixels one bit at a time. The register 3 collectively transfers the even-numbered bits of the sensor unit 1. , And are read out serially as even-numbered pixels one bit at a time.

The dummy area of the sensor section 1 is used to remove the DC component offset and the dark output.

(Problems to be Solved by the Invention) Conventionally, a reference voltage is created by a variable resistor or the like, and the error component is removed by canceling the DC component offset and the dark output. However, this error component removing method has a problem that the error component cannot be sufficiently removed because the reference voltage fluctuates due to a power supply voltage fluctuation or the like, and a dark output component fluctuating at ambient temperature cannot be removed. was there.

In addition, the image sensor of the type shown in FIG. 7 has two registers 2 and 3 for odd and even numbers. Although an error occurs in the level as shown in FIG. 8, there is a problem that this cannot be eliminated by the above-mentioned method.

FIG. 8 is a view showing the dummy area of the sensor section 1.
FIG. 3 is a conceptual diagram showing waveforms of signal outputs of odd bits and even bits.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an image sensor error component correction apparatus capable of eliminating the problems of the conventional method and effectively removing the dark output component, the error between odd bits and even bits, and the like.

(Means and Actions for Solving the Problems) In order to achieve the above object, the present invention provides a first differential amplifier having an odd bit output of an error signal sequence from an image sensor as one input, and the pixel A second differential amplifier having an even-numbered output of the signal train as one input, an A / D converter for A / D converting outputs of the first and second differential amplifiers,
A 0 detection circuit that detects a 0 signal from the output of the D converter and operates only during a part of the dummy area of the pixel signal sequence, and when a 0 detection signal is output from the 0 detection circuit, Means for generating a pulse at the beginning of the pixel signal train of the line; and said odd bit triggered by said pulse;
First and second pulse generation circuits for generating pulses corresponding to even-numbered bits, and outputs of the first and second pulse generation circuits are integrated, and an integrated output is output from the first and second differential amplifiers. It is characterized in that it has first and second integration circuits which are supplied as the other inputs.

According to the present invention, the data read during a part of the dummy area of the image sensor is detected as zero by the zero detection circuit. When 0 is detected, the pulse generation circuit is triggered, a pulse is output from the pulse generation circuit, the pulse is integrated, and the pulse is output to the other input terminals of the first differential amplifier and the second differential amplifier. Apply.

When such an operation is performed, the level of the voltage input to the other input terminal of the first differential amplifier and the second input terminal of the second differential amplifier is changed to the level of the image sensor output input to one input terminal of the differential amplifier. Operate to be equal to

As a result, the dark-time output component of the image sensor can be corrected. In the present invention, the correction is performed on each of the odd bits and the even bits of the image sensor.
An error between the output of the odd bit and the output of the even bit can be removed at the same time.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

 FIG. 1 shows a block diagram of one embodiment of the present invention.

In the figure, reference numeral 11 denotes an image sensor, an example of which is shown in FIG. 12a and 12b are differential amplifiers, 13
Is an odd / even combiner, 14 is an amplifier, and 15 is an A / D converter.
16 is a 0 (zero) detection circuit, 17 is an odd / even selector, 18
a and 18b are pulse generating circuits, 19a and 19b are integrating circuits, 20 is an image processing circuit, and 21 is a control circuit.

Since the surface of the dummy area of the image sensor 11 is processed so that light does not enter as described above, the output from the dummy area is a DC component offset and a dark output.

The control circuit 21 outputs a signal for controlling the operation of the image sensor 11. As a result, the image sensor 11 controls operations such as light receiving time of the sensor unit 1, transfer of pixel data from the sensor unit 1 to the registers 2 and 3, reading of pixel data from the registers 2 and 3, and the like. Also, an odd / even synthesizer 1
3. The odd / even selector 17 is switched in synchronization with odd / even pixels read from the image sensor 11 by a control signal from the control circuit 21. The control circuit 21 also sends the trigger signals t1 and t1 to the pulse generation circuits 18a and 18b at appropriate timing.
Outputs t2.

The 0 detection circuit 16 is controlled so as to operate effectively only while a signal from a dummy portion in the dummy area of the image sensor 11 is being input. The dummy portion will be described with reference to FIG.

The differential amplifiers 12a and 12b are configured so that the voltage Va input to the inverting input terminal (-) is changed to the voltage input to the non-inverting input terminal (+).
When the voltage is lower than Vb and Vc, a 0V signal is output.

Further, the pulse generation circuits 18a and 18b include the control circuit
When the trigger signals t1 and t2 are input from 21, one pulse having an appropriate pulse width is output. Specifically, a mono-multi or the like can be used.

Further, as the integration circuits 19a and 19b, for example, those shown in FIG. 4 can be used.

 Next, the operation of this embodiment will be described.

From the image sensor 11, a pixel signal having a waveform as shown in FIG. 2 is output. This figure shows the sensor unit 1
FIG. 7 is a waveform diagram when line white image information is read. Solid line 11
a shows a waveform diagram of one line of image information including the DC component offset, dark output component, errors between odd bits and even bits, and a dotted line 11b shows an ideal waveform diagram containing no error component. In this waveform diagram, it is clear that the voltage for black image information is large and the voltage for white image information is small.

Now, when a signal having the waveform shown in FIG. 2 is read out from the image sensor 11 and input to the differential amplifiers 12a and 12b, the voltage applied to the non-inverting input terminals (+ terminals) of the differential amplifiers 12a and 12b becomes Initially it is almost 0V. On the other hand, a positive voltage Va (about 0.5 to 0.7 V) is input from the image sensor 11 (see FIG. 3A). As a result, a signal of 0 V is output from the differential amplifiers 12a and 12b.

The 0 V signal is alternately selected for each bit by the odd / even combiner 13 and input to the A / D converter 15 via the amplifier 14. A
The 0 detection circuit 16 determines whether the output signal of the / D converter 15 is 0 or not. Initially, 0V is A / D converter 1 as described above.
Therefore, the output of the A / D converter 15 becomes, for example, 0 for both 6 bits, and is detected by the 0 detection circuit 16 as 0. 0 detection circuit
The 0 detection output from 16 is sent to the control circuit 21 via the odd / even selector 17.

The operation of the control circuit 21 will be described with reference to FIGS. FIG. 5 is a waveform diagram of signals output from the image sensor 11 and signals input to and output from the control circuit 21;
FIG. 6 is a flowchart showing the function of the main part of the control circuit 21.

The image sensor 11 outputs a pixel signal having a waveform as shown in FIG. 2, more specifically, a signal having a waveform 11a in FIG. In this embodiment, the signal output from the dummy area (see FIG. 7) of the image sensor 11 is divided into an invalid part and a dummy part. The dummy portion is composed of pixels each having about 4 bits (8 bits in total).

From the control circuit 21, an odd / even combiner 13, an odd / even selector 17
Is output. In the illustrated example, when the odd / even selection signal p1 is at the H level, the even bit is selected, and when the odd / even selection signal p1 is at the L level, the odd bit is selected. s1 is a control signal for enabling the operation of the 0 detection circuit 16 only while the signal of the dummy portion is being output from the image sensor 11.

Further, q1 and q2 represent a 0 detection signal of the 0 detection circuit 16, and in the example shown in the figure, represent a signal in which the H level is detected as 0,
This shows a state in which the L level has not detected 0. t1,
t2 is a trigger signal output from the control circuit 21; a signal q1 that detects 0 in any one of the four bits in the dummy portion;
When the input of q2 is in the control circuit 21, the control circuit 21
The trigger signals t1 and t2 are output at the beginning of the invalid portion which is the head of line reading.

x1 and x2 are waveforms of pulses output from the pulse generation circuits 18a and 18b when the trigger signals t1 and t2 are input.

As shown in FIG. 6, when reading of a pixel signal from the image sensor 11 is started (step S1), the control circuit 21 determines whether or not this reading is a dummy portion. (Step S2). If it is a dummy portion, the process proceeds to step S3 to determine whether the bit is an even bit or an odd bit. Then, in each case, it is determined whether or not the 0 detection signals q1 and q2 have been input (steps S4 and S6).

If the determination in step S4 is affirmative, the process proceeds to step S5, where flag 1 is set. If the determination in step S6 is affirmative, the process proceeds to step S7, where flag 2 is set. On the other hand, if the determinations in steps S4 and S6 are negative, the process returns to step S2 to determine whether or not it is a dummy portion.

As described above, when a 0 signal is detected even for one bit in the dummy portion, a corresponding odd flag is set.

If step S2 is negative, the process proceeds to step S8, where it is determined whether the reading of the pixel signal from the image sensor 11 has been completed.
Then, it is determined whether or not the invalid portion has been reached. While reading of the pixel signal from the image sensor 11 is in the valid pixel area, the determination in step S9 is negative, and the next 1
If it is the first invalid portion of the line reading, the result is affirmative, and the process proceeds to step S10. In step S10, it is determined whether or not the flag 1 is set. If the determination is affirmative, the trigger signal t1 is sent to the even-numbered pulse generation circuits 18b (step S11). Next, the process proceeds to step S12, and it is determined whether the flag 2 is set. If this determination is affirmative, the trigger signal t is supplied to the odd pulse generation circuit 18a.
2 is sent (step S13).

Thereafter, the process proceeds to step S14, and an operation of resetting the flags 1 and 2 is performed. Then, the process proceeds to step S2 again, and the above-described operation is continued.

In steps S11 and S13, the pulse generation circuit 18a or 1
When the trigger signal t1 or t2 is output to 8b, the pulse generation circuit 18a or 18b outputs pulses x1 and x2. These pulses x1 and x2 are integrated by integrating circuits 19a and 19b, respectively. The output signals r1 and r2 of the integrating circuits 19a and 19b are differential amplifiers, respectively.
Input to the non-inverting input terminals (+) of 12b and 12a.

When the above operation is continued, the voltages Vb and Vc fed back to the non-inverting input terminals of the differential amplifiers 12a and 12b gradually increase,
As shown in FIG. 3 (b), the voltage approaches the voltage Va.

When the above operation further proceeds and the voltages Vb and Vc fed back to the non-inverting input terminals of the differential amplifiers 12a and 12b become higher than the voltage Va input to the inverting input terminals (see FIG. 3 (c)), Positive signals are output from the differential amplifiers 12a and 12b,
The A / D converter 15 outputs, for example, a 6-bit digital signal corresponding to the size. As a result, the 0 detection signal is not output from the 0 detection circuit 16 and the pulse generation circuit
No pulse is output from 18a and 18b. Therefore, the outputs of the integration circuits 19a and 19b gradually decrease.

When the above operation is continued, the voltages Vb and Vc rise and fall around the voltage Va, and the differential amplifiers 12a and 12b
Is a signal from which the dark output component, the error between the odd-numbered bits and the even-numbered bits, and the like have been removed.

Incidentally, the image information of one line from which the error component has been removed has a waveform 11a 'as shown in FIG. 3 (d). This waveform 1
1a 'is the waveform of the output signal of the amplifier 11 of FIG.

Although the odd / even selector 17 is provided in FIG. 1, this is not always necessary and may be deleted. That is, the output of the 0 detection circuit 16 is directly led to the control circuit 21 and the control circuit 21 determines whether or not the bit is an even-numbered bit (the above-described step).
S3), determining whether a 0 detection signal is input (step S
4, S6) and the process of setting flags 1 and 2 (step S6)
5, S7) may be performed.

(Effects of the Invention) According to the present invention, a DC offset component, a dark output component, and an output level of odd bits and even bits are separately detected using a dummy area of an image sensor, and a correction value obtained by the detection is detected. Is maintained and corrected during the reading period of the document information, so that the error of the output level of the odd and even bits, the DC offset component, and the dark output component can be effectively removed.

[Brief description of the drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG. 2 is a waveform diagram of a signal of one line output from an image sensor, and FIG. 3 is a diagram showing a transition of an output voltage of an integrating circuit of the present embodiment. ,
FIG. 4 is a circuit diagram showing a specific example of the integration circuit, FIG. 5 is a waveform diagram of a signal of a main part of FIG. 1, and FIG. 6 explains an operation of a main part of the control circuit of FIG. Flowchart for the seventh
FIG. 8 is a schematic configuration diagram of the image sensor, and FIG. 8 is a waveform diagram of the output of the odd bits and the even bits of the dummy area. 11 ... Image sensor, 12a, 12b ... Differential amplifier, 15 ...
... A / D converter, 16 ... 0 (zero) detection circuit, 18a, 18b ...
... Pulse generation circuits, 19a, 19b ... Integration circuits.

Claims (1)

(57) [Claims] 1. A first differential amplifier having an odd-numbered bit output of a pixel signal sequence from an image sensor as one input, and a second differential amplifier having an even-bit output of the pixel signal sequence as one input. An A / D converter for A / D-converting the outputs of the first and second differential amplifiers; detecting a 0 signal from the output of the A / D converter; A zero detection circuit that operates only in a part of the period, a means for generating a pulse at the beginning of a pixel signal sequence of the next line when a zero detection signal is output from the zero detection circuit, and a trigger by the pulse And first and second pulse generating circuits for generating pulses corresponding to the odd and even bits, integrating outputs of the first and second pulse generating circuits, and integrating outputs of the first and second pulses. First and second integrator circuits for supplying the other inputs of the two differential amplifiers Error component correction apparatus of the image sensor, characterized by comprising a.