JP3080466B2 - Image input device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates in particular relates to an image input device using a CCD, and to correct the variation in level occurring between the odd bits and even bits in the CCD output image
It relates to an image input device.

In an image input device using a CCD, the contrast of a video signal as a result of image reading is increased, and the S / N ratio is increased.
In order to improve the dynamic range, the dynamic range of the signal is set based on the black reference and the white reference. The black reference is built in the CCD and is output as a black reference bit (mask bit), so that it can be used. However, it is also possible to use the CCD output in a darkened state by turning off the illumination light source. The black level is set based on the value of the black reference bit, and is further corrected to follow the black color in the document. The white reference is provided, for example, on a part of the document reading table and is read prior to the start of document reading, and the obtained white level is further corrected by following the ground color of the document.

In general, the line characteristics of the illumination light source and the CCD are not uniform, and the line distribution of the black level and the white level obtained by reading such a black reference and a white reference with the CCD can be uneven. The amount also depends on the position on the line.

SUMMARY OF THE INVENTION The present invention provides a means for effectively correcting the black level particularly for a CCD output signal at low cost.

[0005]

2. Description of the Related Art A conventional CCD level correcting method will be described with reference to FIGS. FIG. 7 shows that the black level correction is 1
FIG. 2 is a configuration diagram of a black level all bit correction circuit that performs a bit unit for all bits of a video signal for a line, wherein 1 is a one-channel CCD, 2 is an amplifier, 3 is an A / D converter, and 4 is A line memory for storing a black level of each bit for one line, a D / A converter 5, a comparator 6, and a black level correction algorithm ROM 7 are shown.

[0006] Analog video signal of the CCD output is amplified by the amplifier 2 is input to the video signal input terminal V _in the A / D converter 3 is converted into a digital signal, and output as digital video signals.

The black level at each bit position on the line is read out from the line memory 4 in the form of a digital signal in synchronization with the line scanning (raster) of the CCD, and the D / A (digital
A / D converter 5
(Analog / digital) black level input terminal B of converter 3
It is applied to the _in.

[0008] A / D converter 3 samples the signal of the difference between V _in and B _in the analog video signals input to the black level, and outputs the converted digital signal. Here, the illustration of the white level correction circuit is omitted for simplification.

The black level correction algorithm ROM 7 has a function table for generating a black level correction value based on the difference output from the comparator 6. This function table shows the difference between the black level stored in the line memory 4 and the black level in the analog video signal output from the CCD.
The black level of the line memory 4 is reflected at a certain rate so that the black level follow-up correction is performed more slowly than the actual black level change.

The correction of the black level of the line memory 4 is performed at the time of black reference reading before the reading of the original is started and during the reading of the original, and the black level of the line memory 4 updated for each line is determined by scanning the next line. Sometimes used and updated at the same time. The conventional circuit shown in FIG. 7 performs correction on a bit-by-bit basis for all bits on a line, but has high correction accuracy, but has the disadvantage of increasing the amount of circuits.

The conventional circuit shown in FIG. 8 has a simpler structure than the conventional circuit shown in FIG.
Correct evenly at the level. In the figure, 1 is a CCD, 2 is an amplifier, 3 is an A / D converter, and 8 is an M for performing black level correction processing.
PU, 9 is an input port for capturing a digital video signal,
Reference numeral 10 denotes an output port for setting black level data, and reference numeral 11 denotes a D / A converter for converting the black level data into an analog signal.

The MPU 8 sets an initial value of the black level in the output port 10 before starting the reading of the original, takes in the digital video signal at the time of the black reference reading from the input port 9 and updates the black level of the output port 10 to update the original. Start reading. It is also possible to detect the black level from the digital video signal line by line while reading the original, and thereby further update the black level. However, this conventional circuit has a drawback that it is impossible to correct the variation between the black levels of each bit on the line.

The cause of the black level fluctuation between bits is as follows.
If the duty of the clock applied to the CCD deviates from 50%, an error occurs in the sample / hold S / H timing between the odd bit and the even bit, and the output delay time from the rising (or falling) of the clock is constant. For this reason, the output levels of the odd and even bits may be different. FIG. 9 shows an example.

FIG. 9A shows a clock CCD of a CCD.
This shows a case where the duty of φ CLK is 50% and the CCD output levels of the odd and even bits are the same. FIG. 9B shows that the duty ratio of the clock CCD φ CLK becomes 60% and a difference occurs between the levels of the odd-numbered bits and the even-numbered bits. Such a change in duty occurs when the falling edge of the clock changes due to a difference in the characteristics of the clock generation circuit.

Another cause of the level difference between the odd bit and the even bit of the CCD output is that the CCD has different channels for the odd bit and the even bit, and the output of each channel is synthesized to produce one channel. In the case of the type that outputs the data as the above, there may be a case where the physical characteristics of each channel are shifted. When there is such a level difference between the odd and even bits, when the binarized image is generated by the tethering process, the image has a rough impression, and there is a problem that the image quality is deteriorated.

[0016]

SUMMARY OF THE INVENTION The present invention uses a CCD.
It is an object of the present invention to provide means for easily correcting a level difference between odd and even bits with a small amount of circuit in an image input device .

In particular, the present invention aims at eliminating the level difference between odd and even bits by focusing on the level difference.

[0018]

In order to solve the above-mentioned problems, the present invention comprises a CCD driven by a single clock.
The sequential H-level period and L-level period of the single clock
In the meantime, odd and accidental bit video signals are
In an image input device that reads data alternately,
Let the CCD perform black reference reading before starting reading,
Odd bits of the video signal output from the CCD at that time
Means for detecting the black level difference between bits
Due to the black level difference between the odd and even bits,
The duty of the single clock for driving the CD is
Means for changing the difference in the direction in which the difference
And even the odd and even bits of the video signal.
The means for detecting the black level difference of the
Average of black level and average of multiple even-numbered black levels
A configuration for detecting a difference from a value is provided.

FIGS. 1A and 1B show the basic configuration of the present invention. FIG. 1A shows a configuration of a level correction method for separately performing black level correction for odd-numbered bits and even-numbered bits. In the figure, reference numeral 1 denotes a CCD, 2 denotes an amplifier for amplifying an analog video signal output from the CCD, Reference numeral 3 denotes an A / D (analog / digital) converter for converting an analog video signal into a digital video signal; 8, an MPU for controlling black level correction processing; 9, an input port for receiving a digital video signal; Reference numeral 11 denotes an output port for setting black level data for even-numbered bits and odd-numbered bits. _{Reference numeral} 12 denotes a selector for alternately selecting each black level data of the output ports 10 and 11 in _response to a clock _φck .

Before the document reading by the CCD 1 is started, the black
The reference black level from the digital video signal
And odd-numbered bits are alternately taken into input port 9 and MP
U8 sets the even-level black level to output port 1
0, the odd bit black level is set to the output port 10 '.
You. The selector 12 receives the clock φ_ckAt H level of
Black level data for even-numbered bits input to input terminal A
Clock φ _ckInput terminal B at L level
Select the black level for odd-numbered bits that is input to.
The black level selected by the selector 12 changes according to the D / A conversion.
Digital-to-analog conversion by the converter 11 and an A / D converter
3 black level input terminal B_inIs input to

[0021] In the A / D converter 3, it is synchronized with odd bits of analog video signal input to the analog video input terminal V _in, the black level of the even and odd input to the black level input terminal B _in The difference between the corresponding analog video signal and the black level at each timing is
It is converted from analog to digital and output.

The MPU 8 averages a certain number of even-numbered black levels as an even-numbered black level, and similarly averages a certain number of odd-numbered black levels as an odd-numbered black level. Each can be set to the output port 10 and the output port 10 '. Following the start of document reading, each black level can be tracked and corrected.

FIG. 1B shows a configuration of a level correction method for changing the duty of the clock.
CD, 2 is an amplifier, 3 is an A / D converter, 8 is an MPU for performing level correction control, 9 is an input port, 10 is an output port, 11 is a D / A converter, and 13 is a clock generator capable of changing the duty. Circuit.

In the level correction method shown in FIG.
The MPU 8 takes in the even-numbered bits and the odd-numbered bits of the digital video signal from the input port 9 from the input port 9 in the same manner as in FIG. Black level data to be averaged black levels of even and odd bits,
On the other hand, the duty control signal given to the clock generation circuit 13 is generated based on the difference between each black level of the even-numbered bits and the odd-numbered bits.

The clock generation circuit 13 generates a clock having a duty determined according to a duty control signal supplied from the MPU 8 and supplies the clock to the CCD 1. In the CCD 1, when the duty of the clock changes, the output levels of the even-bit and odd-bit analog video signals change accordingly. In this case, the duty control signal is
It is generated so as to change the duty of the clock in a direction to eliminate the level difference between the even bit and the odd bit detected from the digital video signal.

[0026]

The operation of the level correction method of the present invention shown in FIGS. 1A and 1B will be described with reference to the waveform diagrams shown in FIGS. 2A and 2B.

FIG. 2A is a waveform diagram corresponding to the configuration of FIG. 1A.
The example of a clock shifted to 40%, the odd bits, indicates the respective black level and level difference detected from the even and odd bits of the digital video signal.

1 shows respective corrected black levels for even-numbered bits and odd-numbered bits supplied to the analog-to-digital converter 3 in FIG. Represents the black level of a digital video signal obtained as a result of analog-to-digital conversion using the corrected black level in an analog format. As described above, the level variation between bits can be removed by a simple method of performing the black level correction for each group of the even-numbered bits and the odd-numbered bits.

FIG. 2 (b) is a waveform diagram corresponding to the configuration of FIG. 1 (a).
This is an example of a clock having a duty of 0% and 40%. As a result, when a level difference is detected between the even-numbered bits and the odd-numbered bits as indicated by 制 御, control is performed to change the duty of the clock as indicated by 点. As described above, the level fluctuation between bits can be removed by a simple method of detecting the level difference between the even-numbered bits and the odd-numbered bits and feeding back the duty difference of the clock.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 3 is an operation flow of the embodiment of the method of the present invention shown in FIG. 1 (a) and FIG. 2 (a). In the figure, (1) to (3) are operations before the start of document reading. In (1), the illumination light source is turned off, and in (2), the CCD output with the illumination dark is set as the black reference level. A / D conversion is performed, and the resulting digital video signal is read from the input port to the MPU for each of the even and odd bits. In (3), the MPU writes the even-numbered bit black level and the odd-numbered bit black level to different output ports. Subsequent operations (4) and (5) are for reading the original document. In (4), the illumination light source is turned on. Read in synchronization with even and odd bits of the video signal, D / A convert and input to the A / D converter,
Convert an analog video signal to a digital video signal. The operation of (5) is repeated for each line. Here, instead of (1) and (2), it is also possible to use the mask bit of the CCD output as a black reference and to connect to the operation after (3).

FIGS. 4 (b) and 2 (b)
5 is an operation flow of the embodiment of the method of the present invention shown in FIG.
(1) 'is the black reference bit (mask bit) of the CCD output
Is monitored with the digital video signal after A / D conversion, and odd bits (represented by ODD) and even bits (represented by EVEN) are separately detected. (2) ′ ODD the level difference A
-Determined by EVEN. (3) ′, A> 0, A =
0, A <0, and the process is separated. If A> 0, control is performed to increase the duty in (4) ′, and A <0
In the case of 0, control for reducing the duty is performed in (5) '. If A = 0, there is no need to change the duty, so the process ends. When A> 0 and A <0, the operations of (1) ′ to (5) ′ are repeated, and the operation ends when A = 0. After A = 0, document reading can be started.

FIG. 5 shows an embodiment of the duty correction circuit provided in the clock generation circuit 13 in FIG. 1B, and FIG. 6 is an operation waveform diagram thereof. In FIG. 5, reference numeral 14 denotes a multi-stage delay circuit, which includes clocks φ _{ck1 to} φ _ck1 which slightly delay the input basic clock φ _ck0.
ckn is output together with φ _ck0 . Reference _numeral 15 denotes a selector, which is any one of the clocks φ _{ck0 to} φ ckn.
_cki is selected based on the duty control signal. An AND gate 16 _matches the clock φ _cki output from the selector 15 with the original basic clock φ _ck0 ,
The result is output as clock _φck . Each clock φ _ck0 ~φ _cki ~φ _ckn of Figure 6, the mutual timing relationships phi _ck is illustrated.

In the duty correction circuit of FIG. 5, the duty control signal is A> 0 in accordance with (4) 'and (5)' of FIG.
In the case of (1), a step increment instruction is performed, and in the case of A <0, a step increment instruction is performed. The selector 15 operates to update the current selected position forward or backward according to the instruction of +1 or -1.

As another embodiment for correcting the duty, a register and a programmable counter whose set value is updated by the register can be used. In this case, the full count value of the counter is set in a register so that it can be increased or decreased by a duty control signal, and the counter is used to count the high-speed clock. Let it.

[0035]

According to the present invention, the level variation between odd and even bits can be corrected with a much smaller circuit amount than the conventional black level all bit correction method, and the quality of an input image can be improved at low cost. Can be planned.

[Brief description of the drawings]

FIG. 1 is a diagram showing the basic configuration of the present invention.

FIG. 2 is an operation waveform diagram illustrating an operation of the present invention.

FIG. 3 is an operation flowchart of an embodiment of the method of the present invention for performing black level correction for odd and even bits.

FIG. 4 is an operation flowchart of an embodiment of a method of the present invention for performing black level correction by changing the duty of a clock.

FIG. 5 is a configuration diagram of an embodiment of a clock duty correction circuit.

FIG. 6 is an operation waveform diagram of the embodiment of the clock duty correction circuit.

FIG. 7 is a configuration diagram of a conventional black level all bit correction circuit.

FIG. 8 is a configuration diagram of a conventional black level DC level correction circuit.

FIG. 9 is an operation waveform diagram illustrating a level change due to a clock duty.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CCD 2 amplifier 3 A / D converter 8 MPU 9 input port 10, 10 'output port 11 D / A converter 12 selector 13 clock generation circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-3-184469 (JP, A) JP-A-2-174465 (JP, A) JP-A-62-183671 (JP, A) JP-A-61-186 142861 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04N 1/40-1/409 H04N 1/46 H04N 1/60

Claims (2)

(57) [Claims] 1. A CCD which is driven by a single clock.
The sequential H-level period and L-level period of the single clock
In the meantime, odd and accidental bit video signals are
In an image input device that reads data alternately, black reference reading is performed on the CCD before starting reading the document.
The odd-numbered video signal output from the CCD at that time.
Means for detecting the black level difference between the odd bit and the even bit, and the means for detecting the black level difference between the odd bit and the even bit.
The duty of a single clock to drive the CCD
Means for changing the black level difference in a direction in which the black level difference becomes smaller.
An image input device comprising: 2. An odd-numbered video signal according to claim 1,
There are multiple means to detect the black level difference between the bit and the even bit.
The average of the black level of the odd-numbered bits and the
Specially, it detects the difference from the average black level.
Image input device.