JPS60256219A - Radio receiver of frequency synthesizer system - Google Patents

Abstract

PURPOSE:To attain easy tuning operation by changing the tuning sweep time in response to a frequency so that the relation between a tuning voltage and a tuning sweep time at a frequency sweep band is linear thereby making the change in the array display constant independently of the value of a reception frequency. CONSTITUTION:An output signal of a reference signal oscillator 9 is given to an up-down counter 8 as a clock signal, and a means 12 frequency-dividing the clock signal with a prescribed ratio and a switch 13 switching the clock signal into the clock signal as it is and a frequency-divided clock signal are inserted between them. A frequency dividing ratio signal of the counter 8 is inputted to a programmable frequency divider 5 and a subtractor 14, the subtractor 14 operates a difference N-Nx between the output frequency dividing ratio N and the frequency dividing ratio Nx corresponding to a prescribed reference frequency, outputs a carry signal with N-Nx<0, sets the switch 13 to the position of a terminal 1 and drives the counter 8 at the normal speed. Further, the switch 13 is thrown to the position of a terminal 2 at N-Nx>=0 so as to drive the counter 8 at a speed lower than the normal speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a one-frequency synthesizer type radio receiver.

<Prior Art> Conventionally, this type of radio receiver generally changes the frequency division ratio of the frequency divider in the phase-locked loop a in response to the operation on the tuning operation key C, as shown in FIG. By changing the frequency division ratio signal given from the up/down counter d,
By changing the tuning voltage applied to the local oscillation signal, the frequency of the local oscillation signal output from the local oscillation circuit e is swept, and the tuning voltage from the phase-locked loop a is applied to the array display. By also giving f, the received frequencies are displayed in an array.

However, since the configuration is such that a constant clock signal is always given from the up/down counter dK and the reference signal oscillator g, the tuning frequency cannot be swept and the clock speed is always constant (for example, a constant channel span in units of 100 KHz). ) will result in a line ft b, so,
The relationship between the frequency change and the corresponding change in the tuning voltage is not necessarily constant, and forms a curve as shown in FIG. 2, for example.

In other words, in a low frequency area (for example, the reception frequency is 98M)
H2 or less), the change in the tuning voltage with respect to a constant frequency change is small, and in the high frequency region (98 MHz or more), the change in the tuning voltage with respect to a constant frequency change is about twice as large as the former.

Therefore, in the array display f, which is a linear type that operates in proportion to the applied voltage,
The disadvantage is that the display of the array changes faster in a high frequency region than in a low frequency region, making it difficult to perform a tuning operation in a high frequency region.

Purpose of the present invention The present invention has been made in view of the above-mentioned conventional situation, and its purpose is to make the array display on the array display always change at a constant speed regardless of the high or low reception frequency. The object of the present invention is to facilitate the tuning operation.

<Embodiment> First, an embodiment of a frequency synthesizer type radio receiver according to the present invention will be described with reference to FIGS. 1 and 2.

In the basic block circuit diagram of FIG. 1, N=;j is the flow/l-end that receives radio waves received by the antenna 2, and as is well known, the local oscillator circuit 3 is connected to the RF amplifier circuit, MIX circuit, etc. Integration is 11. A is a phase-locked loop, which is constructed by loop-connecting the local oscillation circuit 3, a prescaler 4 having a predetermined frequency division ratio, a programmable frequency divider 5, and a phase comparator 6 in this order. 7・j for operation on synchronization operation key 7 for vR
Accordingly, by changing the frequency division ratio of the divider 5 by multiplying the frequency division ratio given by the up/down counter 8, the phase of the resulting frequency-divided signal and the phase of the reference oscillation signal, which will be described later, can be compared. Based on this, the tuning voltage output from the phase comparator 6 to the local oscillation circuit 3 is changed, thereby sweeping the frequency of the local oscillation signal output from the local oscillation circuit 3. 9 is a reference signal oscillator, and a reference oscillation signal outputted by the reference signal oscillator is inputted to the phase comparator 6. Furthermore, the phase-locked loop A
The tuning voltage outputted from the phase comparator 6 is also applied to a drive circuit 11 for a linear type array display 10, so that the reception frequency is displayed in an array.

The output signal from the reference signal oscillator 9 is also given to the up/down counter 8 as a clock signal. A frequency divider 12 that divides the frequency, a state in which the clock signal from the reference signal oscillator 9 is directly applied to the up/down counter 8 (terminal l side), and a state in which the clock signal frequency-divided by the frequency divider 12 by 2 is applied to the up/down counter 8. A switch 13 is provided which is controlled to switch between the state (terminal 2 side) and the state applied to the down counter 8 (terminal 2 side).

The frequency division ratio signal output from the up/down counter 8 is input to the programmable frequency divider 5 and also to the subtracter 14, in which:
The output frequency division ratio N and a predetermined reference frequency (for example, 98MH
The difference (N-Nx) from the branching ratio Nx corresponding to Set and drive up/down/counter 8 at normal speed, N-
Nx? At O, the carry signal is not output, the control switch 13 is set to the end f2, and the up/down counter 8 is driven at a speed lower (half) than the normal speed.

According to the above configuration, a predetermined reference frequency (for example, 98M
H2) Sweep according to frequency so that in lower frequency bands, the frequency is swept at the normal speed, and in the higher frequency bands, the frequency is swept at a lower (half) speed than the normal speed. Since the time changes automatically, the relationship between the tuning voltage change and the receiving frequency change appears to be approximately linear, as shown in FIG. In other words, the relationship between the tuning voltage and the tuning sweep time can be approximately IJ air, so the play display on the play display 10 always changes at a constant speed regardless of the high or low reception frequency. be able to.

Effect> In summary, the radio receiver with one type of frequency synthesizer according to the present invention has the following effects: By changing the frequency division ratio of the frequency divider in the phase-locked loop and changing the tuning voltage applied to the local oscillator circuit, the local oscillation can be achieved. The circuit is configured to sweep the frequency of a local oscillation signal output from the circuit.

The tuning voltage from the phase-locked loop is also applied to an array display to display the reception frequency in an array, and the relationship between the tuning voltage and the tuning sweep time within the frequency sweep band is approximately linear. As described in detail in the description of the embodiment, regardless of the high or low reception frequency, The tuning voltage will always change at a constant speed,
Therefore, it has become possible to change the array display on the array display at a constant speed, thereby making it possible to perform tuning operations easily.

[Brief explanation of drawings]

FIG. 1 is a schematic block circuit diagram of the main parts of a conventional frequency/sensizer type radio receiver, and FIG. 2 is a graph showing the frequency characteristics of its tuning voltage. 3 and 4 show an embodiment of a frequency synthesizer type radio receiver according to the present invention, FIG. 3 is a schematic block circuit diagram of the main part, and FIG. 4 is a tuning sweep time change. This is a graph showing the apparent frequency characteristics of the tuning voltage in a state where is changed. A: Phase locked loop, 3: Local oscillation circuit, 5: Frequency divider, 10: Array display. Applicant/Yap Co., Ltd. Agent Patent Attorneys [(] Kazuhide

Claims (1)

[Claims] (1) Sweeping the frequency of the local oscillation signal output from the local oscillation circuit 3 by changing the frequency division ratio of the frequency divider 5 in the phase-locked loop A and changing the tuning voltage applied to the local oscillation circuit 3 In the frequency synthesizer type radio receiver, the frequency synthesizer type radio receiver is configured to display the reception frequency in an array by applying the tuning voltage from the phase-locked loop A to the array display 10. A frequency synthesizer one-type radio reception, characterized in that the frequency synthesizer is configured to change the tuning sweep time according to the frequency so that the relationship between the tuning voltage and the tuning sweep time within the frequency sweep band is approximately linear. Machine.