JPS60254786A - High density printing wiring method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a high-density printed wiring method used in a printed wiring board layout device.

[Technical background of the invention and its problems]

In recent years, there has been an increasing demand for higher density printed wiring boards. Therefore, in order to increase the density of printed wiring, the following two
Two methods have been considered: 1. Increase the maximum number of signal lines that can be arranged in one grid interval (for example, 0.1 inch) by narrowing the conductor width of the signal lines.

■ By reducing the land diameter of random through holes, the maximum number of signal lines that can be arranged between one grid is increased.

However, printed wiring boards made using this method have an extremely large number of random through holes with small land diameters and signal lines with narrow conductor widths (hereinafter referred to as wiring patterns) that require advanced manufacturing technology. However, although it is possible to increase the density of printed wiring, it has the disadvantage of lowering manufacturing yield. For this reason, D A (Des
ign Automation) In automatic wiring using 7'o-gram, the step of removing unnecessary through holes that follows the step of wiring processing minimizes the number of random through holes randomly placed during wiring by improving the route of each turn. is being considered. However, even with this method, there are many random through holes with small land diameters.

Therefore, Japanese Patent Application No. 58-201309, Japanese Patent Application No. 58-'
138842), automatic wiring processing followed by unnecessary through hole deletion processing, land diameter enlargement processing, etc., random through holes randomly placed during wiring, The grid offset shown in figure M1 is to be reduced as much as possible by improving the line pattern of the wiring pattern (when wiring, KU is processed with the width shown by the dotted line, and the offset value up to the width shown by the solid line is stored in the database.Manufacturing data ( For example, when creating a drawing tape (drawing tape), the offset value is taken into account and the wiring pattern is placed along the solid line path), and even bending as shown in Figure 2 (dotted line width is processed during wiring, and solid line width is processed in post-processing). (as in the case of rerouting), consideration is given to improving clearance.

However, even with such processing, many wiring patterns with narrow conductor widths still exist, and a substantial drop in manufacturing yield is unavoidable.

[Purpose of the invention]

The invention was made in view of the above circumstances, and its purpose is to provide a high-density printed wiring method that can increase the density of printed wiring without sacrificing manufacturing yield.

[Summary of the invention]

In the present invention, after applying a wiring pattern with a preset allowable wiring density (number of wires between bins) with a thin line width, if each wiring pattern is smaller than the allowable number of wires, the line width of the hole or turn is changed to a thick line. The wiring pattern is made thicker within the permissible range by chemical processing, and the manufacturing yield of high-density printed wiring boards is improved.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described with reference to FIG. #g3 to FIG. 9. FIG. 3 is a flow diagram showing the configuration of a computer system (automatic wiring processing device) according to an embodiment of the present invention. In the figure, 30 is a CPU that forms the center of the system, and according to an automatic wiring program 32 stored in a main memory 31, a printed wiring board is automatically manufactured using a design file (database) 34 stored in an external storage device 33. Perform wiring processing. Reference numeral 35 denotes an input/output control device that performs data input/output control between input/output devices such as the external storage device 33 and the CPU 30 (main memory 31).

FIG. 4 is a flowchart showing the procedure of automatic wiring processing according to an embodiment of the present invention realized by the apparatus shown in FIG. 3 above. In Fig. 4, SL is a stage where rough wiring is performed, and S2 is an unnecessary stage A-- due to a change in the wiring pattern layer.
A step to delete holes, Sad, a step to increase the land diameter of a random through hole by changing the wiring route with four turns, a step to 7°S4, a step to perform fine wiring in consideration of improving tight clearances as much as possible, , S6 is the step of extracting the wiring top turn for which the detailed route was determined in S4, S6 is the step of checking whether all the wiring mother turns have been processed, S7 is the step of extracting the wiring pattern surrounding the wiring pattern extracted in S5 The step of extracting wiring information (positions and sizes of forbidden bands, pins, through holes, surrounding wiring, position and thickness of 9 turns), S8 is to check whether the conductor width can be made thicker. Step 89 is step f for increasing the conductor width of the wiring pattern.

5 to 9 are for explaining the wiring processing operation of the above embodiment, respectively, and FIG. 5 shows a basic lattice and two types of quasi-lattices, which are wiring units on a printed wiring board. Figures 6, 8, and 8 respectively show the wiring t! during rough automatic wiring processing where the conductor width is subject to change. The diagrams showing the patterns, Figures 7 and 9, are the same as Figures 6 and 8 above, respectively.
5 is a diagram showing an example of a no-f turn in which the thick line pattern processing shown in FIG. 4 is applied to the arm turn shown in the figure. FIG. In the figure,
51, 62, 72, 83゜93 is a basic lattice in which pins and random through holes can be set (can be used as a wiring route), 52.63.73, 134.95 is a basic lattice in 8
It can be used as a wiring route with a quasi-grid divided into equal parts.

53.94 is a quasi-lattice obtained by dividing the basic lattice into five equal parts and can be used as a wiring route. 61, 71, 81゜91 is a random hole with the same land diameter as the bottle or pin, 82
．． 92 is a random through hole with a small land diameter that could not be made larger, 64.85.91 is a wiring pattern with a narrow conductor width used during wiring, and 74.96 is the 4th one.
70 in the figure (according to the step shown in the chart), the conductor width is increased (thickened line processing is performed) to turn the arm of the wiring.

As shown in FIG. 5, the wiring board can be represented by a basic lattice 5 and two types of quasi-lattices 52 and 53.

Among these lattices 51, 52, 53, the basic lattice 51. quasi-lattice 5
2 is used as the wiring path. In addition, there are 6 pin and random through holes.

71.81.82 and 91.92 are located on the basic lattice 5. Also, random through holes 61, 71 . with large bottle and land diameters. Ijl, 91 is the quasi-lattice 52 between the fundamental lattices
and one quasi-lattice 53 are made unusable. Furthermore, the random through holes 82, 92 with small land diameters make it impossible to use one quasi-lattice 52 between the basic lattices.

The wiring process is performed under the condition that [after performing rough wiring (step 87), fine wiring (step, f84) using the basic grid 51 and quasi-lattice 52] is performed.
At fsl, rough wiring is performed using random through holes with small land diameters and wiring patterns with narrow conductor widths.

After that, in Stella fS2, the cine-required through-hole was deleted by changing the layer of wiring with 4 turns. Further, in step S3, after a process is performed to increase the second diameter of the wire by changing the route of nine turns of the wiring, detailed wiring is performed in consideration of improving the severe clearance in Stella 7'S4. In the wiring pattern that has undergone such processing, as shown in Figures 6 and 8, the conductor width of the I-lean wiring can be increased (for example, the thickness used in the proven two-pin wiring). There may be locations. So Ste, GuS
At 5, one wiring t! Extracts turn position information.

Furthermore, the wiring information around this wiring pattern is extracted using Stetsuno S7, and based on this information, it is possible to increase the conductor width using Stetsuno S8 (conductor width set between three pins). Check whether it is possible to change the conductor width between the two pins to the set conductor width. As a result of checking in step s8, if it is possible to make the conductor thicker, the conductor width is increased in step S9. Fig. 7 is a case in which the conductor width is increased by using a quasi-lattice 52 in contrast to the 74 turns shown in Fig. 6, and Fig. 9 is a case in which the conductor width is increased by using
Cases in which the conductor width is increased by using quasi-lattices 52 and 53 for the turns are shown.

By such thickening process, it is possible to minimize the number of wiring patterns having narrow conductor widths and poor manufacturing yield.

〔Effect of the invention〕

As detailed above, according to the high-density printed wiring method of the present invention, the number of signal lines with thin conductor widths that are difficult to manufacture can be minimized without reducing the wiring density, and the manufacturing yield can be improved. You can improve further.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining the grid offset means,
FIG. 2 is a diagram for explaining the bending processing means, FIG. 3 is a block diagram showing the hardware configuration in an embodiment of the present invention, and FIG. 4 is a diagram for explaining the automatic wiring processing means in the above embodiment. FIG. 5 is a diagram for explaining the lattice in the above embodiment, and FIGS. 6 to 9 are flowcharts showing 7 and turn examples for explaining the pattern processing operation in the above embodiment, respectively. FIG. 30... CPU, 31... Main memory, 32... Automatic allocation, 1lilf program, 33... External storage device,
34...Design file (7'-tapes), :is・
...Input/output control device, 51...Basic grid, 52.53
... Quasi-lattice, 64.74, 85, 96, 97... Life wiring pattern. Applicant's representative Patent attorney Takeshi Suzu

Claims (1)

[Claims] In an automatic wiring processing device for a printed wiring board, preset number 4 including the positions of through holes with land and landless, and the number of wires between pins, in units of a certain grid. Turn Layer 9) For the 9 turns that have been routed under the conditions, extract the position information of the wires and arm turns, and after confirming that all the wire turn processing has been completed, check the surroundings of each wiring pattern. Extract information for each wiring. Is the number of inter-lattice wiring as above? When it is confirmed that the allowable number of wires indicated by the turn layout conditions is smaller, the conductor width for the wiring pattern is changed to a conductor width that is wider than the conductor width set for the above-mentioned allowable number of wires. High-density printed wiring method.