JPS60254722A - Substrate for semiconductor device - Google Patents
Substrate for semiconductor deviceInfo
- Publication number
- JPS60254722A JPS60254722A JP11133184A JP11133184A JPS60254722A JP S60254722 A JPS60254722 A JP S60254722A JP 11133184 A JP11133184 A JP 11133184A JP 11133184 A JP11133184 A JP 11133184A JP S60254722 A JPS60254722 A JP S60254722A
- Authority
- JP
- Japan
- Prior art keywords
- film
- substrate
- aluminum nitride
- single crystal
- microcracks
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 claims abstract description 11
- 239000013078 crystal Substances 0.000 claims description 9
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 238000005224 laser annealing Methods 0.000 abstract description 3
- 238000002844 melting Methods 0.000 abstract description 3
- 230000008018 melting Effects 0.000 abstract description 3
- 238000000034 method Methods 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000005350 fused silica glass Substances 0.000 description 3
- 238000001069 Raman spectroscopy Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 239000005997 Calcium carbide Substances 0.000 description 1
- 101150071661 SLC25A20 gene Proteins 0.000 description 1
- 101150102633 cact gene Proteins 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- CLZWAWBPWVRRGI-UHFFFAOYSA-N tert-butyl 2-[2-[2-[2-[bis[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]amino]-5-bromophenoxy]ethoxy]-4-methyl-n-[2-[(2-methylpropan-2-yl)oxy]-2-oxoethyl]anilino]acetate Chemical compound CC1=CC=C(N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)C(OCCOC=2C(=CC=C(Br)C=2)N(CC(=O)OC(C)(C)C)CC(=O)OC(C)(C)C)=C1 CLZWAWBPWVRRGI-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Optics & Photonics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Recrystallisation Techniques (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はＳＯＩ （５ｉｌｉｃｏｎ ｏｎ Ｉｎ５ｕｌ
ａｔｏｒ ）を容易に形成できる半導体装置用基板に関
する、（従来技術とその問題点）
非晶質絶縁体上にＳｉ単結晶を成長させるいわゆるＳＯ
Ｉ成長技術は、シリコン素子の高速化あるいは三次元構
造化にとって非常に有効であシ、また表示素子など広範
囲な応用が期待されている。[Detailed Description of the Invention] (Industrial Application Field) The present invention is directed to SOI (5ilicon on In5ul)
(Prior art and its problems) So-called SO, which grows Si single crystals on an amorphous insulator, regarding substrates for semiconductor devices that can easily form
I-growth technology is very effective for increasing the speed of silicon devices or creating three-dimensional structures, and is expected to have a wide range of applications such as display devices.
現在ＳＯＩ単結晶膜の成長には二つの方式が検討されて
いる。一つは単結晶シリコン基板上の二酸化シリコン（
Ｓｔｏｗ）膜の一部を開口し、そこを種子部として堆積
した多結晶Ｓｉ＠をレーザ元や電子ビーム等の加熱手段
を用いて単結晶化する方法である。Currently, two methods are being considered for growing SOI single crystal films. One is silicon dioxide (
In this method, a part of the Stow film is opened and the deposited polycrystalline Si@ is made into a single crystal using a heating means such as a laser source or an electron beam using the opening as a seed part.
前者の種子部を用いてＳＯＩ膜を形成する方法は、結晶
学的な配向性の制御が容易なため、魅力的な方法である
が、プロセスに複雑な要因が増えること、また開口部と
非開口部の境界に段差が生じることなど解決すべき問題
が多い。The former method of forming an SOI film using a seed part is an attractive method because it is easy to control the crystallographic orientation, but it adds complicating factors to the process, and There are many problems that need to be solved, such as the occurrence of steps at the boundaries of the openings.
一方、後者の種子部を用いない方式は余分なプロセスが
ないこと、また原理的に段差を生じないこと、種子部分
に制約されないこと等、利点を有しているが、単結晶Ｓ
ＯＩ膜の良質化や配向性の制御にまだ問題を残している
。On the other hand, the latter method that does not use a seed part has advantages such as no extra process, no steps in principle, and no restrictions on the seed part, but single crystal S
Problems still remain in improving the quality of the OI film and controlling its orientation.
本発明は後者の種子部を用いない方式に関するもので、
良好なＳＯＩ膜を有する半導体装置用基板を提供するも
のである。ＳＯＩ用の絶縁基板としては、溶融石英やＳ
ｉ基板上に形成した５ｉＯ１膜が用いられでいる。特に
溶融石英は可視光領域で透明であるため、該基板上につ
くられたトランジスタはカラーディスプレイのスイッチ
ング素子等に有望である。The present invention relates to the latter method that does not use seeds,
The present invention provides a substrate for a semiconductor device having a good SOI film. As an insulating substrate for SOI, fused silica or S
A 5iO1 film formed on an i-substrate has been used. In particular, since fused silica is transparent in the visible light range, transistors fabricated on this substrate are promising as switching elements for color displays and the like.
しかしながら、溶融石英は熱膨張率が０．５５Ｘ１０７
℃とシリコンの３．５Ｘ１０ ７℃に比べて１桁近く小
さいために、ＳＯＩ膜にマイクロクラックが入るという
問題がある。そのために、シリコン゛の熱膨張率に近い
基板材料の作索が行われてきた。However, fused silica has a coefficient of thermal expansion of 0.55X107
℃ is nearly an order of magnitude smaller than that of silicon, which is 3.5×10 7 C, which causes the problem of microcracks in the SOI film. For this reason, attempts have been made to create substrate materials with a coefficient of thermal expansion close to that of silicon.
その結果、文献（Ｒ、Ａ 、 Ｌｅｍｏｎｓ ｅｔ：
ａｌ 、 Ａｐｐｌ 。As a result, the literature (R, A., Lemons et al.
al, Appl.
Ｐｈｙｓ、Ｌｅｔｔ、４０，４６９ （１９８２））に
示されているように、コーニングガラス７７４０や７０
５９が開発された。前者の熱膨張率は３．２５Ｘ１０
７℃。Phys, Lett, 40, 469 (1982)), Corning Glass 7740 and 70
59 was developed. The thermal expansion coefficient of the former is 3.25X10
7℃.
後者のそれは４．６Ｘ１０ ７℃で比較的Ｓｉに近い値
を示すが、軟化点の低いことが問題である。すなわち、
前者の軟化点は８２１℃、後者のそれは８４４℃である
ため、現在のデバイスプロセスに投入し、トランジスタ
を作成することは不可能である。The latter exhibits a value relatively close to that of Si at 4.6×10 7°C, but its low softening point is a problem. That is,
Since the former has a softening point of 821° C. and the latter has a softening point of 844° C., it is impossible to input it into current device processes and create transistors.
（本発明の目的）
本発明はこのような従来技術の欠点を除去せしめて、Ｓ
ＯＩ形成時にマイクロクラ、りの入らない半導体装置用
基板を提供することにある。(Objective of the present invention) The present invention eliminates the drawbacks of the prior art and improves S
It is an object of the present invention to provide a substrate for a semiconductor device in which microcracks and oxides do not enter during OI formation.
（本発明の構成）
本発明によれば、完全性のより高い焼結体の窒化アルミ
ニウム基板上に単結晶Ｓｉ膜が形成されていることを特
徴とする半導体装置用基板が得られる。(Structure of the Present Invention) According to the present invention, a substrate for a semiconductor device is obtained, which is characterized in that a single crystal Si film is formed on a sintered aluminum nitride substrate with higher integrity.
（構成の詳細な説明）
本発明は上述の構成をとることによシ、従来技術の問題
点を解決した。高度に焼結された窒化アルミニウムの熱
膨張係数は３．５Ｘ１０ ７℃であることが判明し、こ
の値はＳｉの３．５Ｘ１０ ７℃と等しい値であった。(Detailed Description of Configuration) The present invention solves the problems of the prior art by adopting the above-described configuration. The coefficient of thermal expansion of highly sintered aluminum nitride was found to be 3.5X10 7 °C, which was equivalent to that of Si, 3.5X10 7 °C.
また融点も２４００℃と極めて高く、デバイス形成上全
く問題がなかった。そのため該窒化アルミニウム基板上
に堆積した多結晶Ｓｉ膜をレーザアニールして形成した
単結晶Ｓｉ膜にはマイクロクラ、りは全く発生せず、極
めて優れたＳＯＩ半導体装置用基板が容易に得られた。Moreover, the melting point was extremely high at 2400° C., and there were no problems in device formation. Therefore, the single crystal Si film formed by laser annealing the polycrystalline Si film deposited on the aluminum nitride substrate did not have any microcracks or pores, and an extremely excellent substrate for SOI semiconductor devices was easily obtained. .
（実施例）
以下、本発明の実施例について図面を参照して詳細に説
明する。第１図は本発明の実施例を示す断面図である。(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention.
まず窒化アルミニウム焼結体にカルシウムカーバイト（
ＣａＣｔ）１モル％を添加しホ、ドブレス法によシ基板
を作成した。本発明で得られた基板の熱膨張率を測定し
たところ、２０〜１０００℃で３．５Ｘ１０ ７℃であ
った。この値は従来のホットプレス法で作成された窒化
アルミニウム焼結体の埴４．８〜６．ｌＸ１０ ７１ｍ
、に比べて小さく、Ｓｉ単結晶の値３．５Ｘ１０ ７℃
に等しかった。First, calcium carbide (
A substrate was prepared by adding 1 mol % of CaCt) and using the Dobres method. When the thermal expansion coefficient of the substrate obtained in the present invention was measured, it was 3.5×10 7°C at 20 to 1000°C. This value is 4.8-6. lX10 71m
, the value of Si single crystal is 3.5X10 7℃
was equal to
この基板をメカニカルケミカル研磨によシ平坦化した。This substrate was planarized by mechanical chemical polishing.
該窒化アルミニウム基板１に化学気相成長法（ＣＶＤ）
により７００℃で多結晶Ｓｉ２に厚−さ０．６８ｍ堆積
した。この試料に約ＩＷＯＡｒレーザを照射し、単結晶
化した。得られたＳＯ，Ｉ膜を工、ツチングし、光学ｗ
Ａ徴鏡で観察したところ、マイクロクラックの全くない
極めて高品質の単結晶膜であることが分った。またラマ
ン分光によりＳＯＩ膜の結晶性を評価したところ、ラマ
ンシフトの波数は５２１ａｎ−１で、単結晶Ｓｉのそれ
と等しく、冷却時に基板からの歪を全く受けていないこ
とも判明した。Chemical vapor deposition (CVD) is applied to the aluminum nitride substrate 1.
A thickness of 0.68 m was deposited on polycrystalline Si2 at 700°C. This sample was irradiated with approximately IWOAr laser to form a single crystal. The obtained SO,I film was processed and then optically processed.
When observed with an A-shape mirror, it was found to be an extremely high quality single crystal film with no microcracks. Furthermore, when the crystallinity of the SOI film was evaluated by Raman spectroscopy, it was found that the wave number of the Raman shift was 521an-1, which was equal to that of single crystal Si, and that it was not subjected to any strain from the substrate during cooling.
また窒化アルミニウムの融点は２４００℃であり、この
値はコーニングガラス７７４０や７０５９に比較して非
常に高く、デバイス形成時には全く問題にならない。Furthermore, the melting point of aluminum nitride is 2400° C., which is much higher than Corning Glass 7740 and 7059, and poses no problem when forming devices.
更にまた窒化アルミニウム基板に厚さ０．１μｍのｓ
ｉＱ、膜をＣＶＤ法によシ形成し、該膜上に多結晶シリ
コン膜を堆積したのち、レーザアニールを行った場合に
も全くマイクロクラックは入らなかった。Furthermore, the aluminum nitride substrate has a thickness of 0.1 μm.
iQ, a film was formed by the CVD method, a polycrystalline silicon film was deposited on the film, and then laser annealing was performed, no microcracks were generated at all.
（発明の効果）
以上、詳細に述べたように、本発明による半導体装置用
基板はマイクロクラックのないＳＯＩ膜を提供し、シリ
コン素子の高速化あるいは三次元化、また表示素子用等
に広い応用が期待される。(Effects of the Invention) As described above in detail, the substrate for semiconductor devices according to the present invention provides an SOI film without microcracks, and is widely applicable to high-speed or three-dimensional silicon devices, display devices, etc. There is expected.
第１図は本発明の半導体装置用基板の断面図であシ、１
は窒化アルミニウム基板、２は多結晶Ｓｉ膜で、レーザ
照射によシ単結晶化される。
代理人弁理士内原 晋FIG. 1 is a cross-sectional view of a substrate for a semiconductor device according to the present invention.
2 is an aluminum nitride substrate, and 2 is a polycrystalline Si film, which is made into a single crystal by laser irradiation. Representative Patent Attorney Susumu Uchihara
Claims (1)
に単結晶Ｓｔ膜が形成されて−ることを特許とする半導
体装置用基板。A semiconductor device substrate patented in that a single crystal St film is formed on an aluminum nitride substrate having a coefficient of thermal expansion approximately equal to 3i.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11133184A JPS60254722A (en) | 1984-05-31 | 1984-05-31 | Substrate for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11133184A JPS60254722A (en) | 1984-05-31 | 1984-05-31 | Substrate for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60254722A true JPS60254722A (en) | 1985-12-16 |
Family
ID=14558494
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11133184A Pending JPS60254722A (en) | 1984-05-31 | 1984-05-31 | Substrate for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60254722A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9425248B2 (en) | 2011-12-22 | 2016-08-23 | Shin-Etsu Chemical Co., Ltd. | Composite substrate |
-
1984
- 1984-05-31 JP JP11133184A patent/JPS60254722A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9425248B2 (en) | 2011-12-22 | 2016-08-23 | Shin-Etsu Chemical Co., Ltd. | Composite substrate |
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