JPS60253343A - Transmission and reception circuit for data transmission - Google Patents

Abstract

PURPOSE:To obtain an inexpensive transmission/reception circuit which performs transmission of data through a short-distance transmission line at a low speed, by using just several units of transistors with no compensation needed for waveform distortions. CONSTITUTION:Transistors TrQ1 and Q2 constitute a double power supply SEPP (Single Ended Push-Pull) type transmission circuit. The codes of + or - levels are transmitted from terminals T3 and T4 of a pulse transformer PT when the TrQ1 or Q2 is turned on by a transmission signal sent from a logical circuit CC for control of transmission. Thus the transmission is possible for a double-current binary code. Then the transmission of a ternary code is also possible by turning off both TrQ1 and Q2. When a terminal T2 has a higher potential than a V0 terminal after reception of the transmitted code, a TrQ3 is turned on and the variation of the collector potential of the TrQ3 is fetched by the circuit CC. While a TrQ4 is turned on when the terminal T2 has a lower potential than the V0 terminal. Then the variation of the collector potential of the TrQ4 is fetched by the circuit CC after receiving a level shift through a TrQ5. In a reception mode of the ternary code, the TrQ3 or Q4 is turned on after reception of + or - levels and then turned off with ''0''.

Description

[Detailed Description of the Invention] [Technical Field to which the Invention Pertains] The present invention is directed to a simple method suitable for low-speed digital data transmission over a transmission line that is short enough to eliminate the need to compensate for transmission waveform distortion. The present invention relates to a transmitting/receiving circuit for data transmission.

More specifically, in response to the increasing sophistication and complexity of household devices including new media devices, disaster prevention and crime prevention devices, and the computerization of the home, these home information devices will be centrally housed and organically combined. The home information communication network HAN (jlomeArea Informat
ion Network) is being developed and standardized, and the present invention relates to a data transmission transmitter/receiver circuit suitable for use in such HAN. .

To give a specific example, in a home, if you want to control the blinking of lights in each room, entrance, etc. from the kitchen, you would use a network that runs through the home, and from the transmitting circuit in the kitchen to the receiving circuit in each room, etc. Control commands are transmitted in digital data format, and the present invention can be said to relate to a simple transmitting/receiving circuit suitable for such uses.

[Prior art and its problems]

Traditionally, when talking about data transmission, for example, LAN (local
Targeted at computer-to-computer communication systems in business offices such as area networks, high-speed data transmission over relatively long distance transmission paths was considered, so it was necessary to synchronize bits between sending and receiving. can be,
Therefore, a differential operational amplifier with high sensitivity and hysteresis characteristics.

Waveform equalizer that compensates for waveform distortion, PL that performs clock extraction
In addition, depending on the transmission code format, a scrambler or a descrambler is required to suppress consecutive "0"s in transmission data to facilitate clock extraction.

In addition, even when the transmission distance is relatively short and the transmission speed is low, if start-stop synchronization is achieved and DC superposition is applied to the data transmission line, the DC component is small and the output power is low. RZ codes with a small duty ratio are often used as transmission codes, but in order to extend the pulse width as a reception margin, monostable multi-high breaks that are triggered by the rising edge of the RZ code and Hanastable multi-high breaks are used. The configuration of the transmitter/receiver circuit is complicated, such as requiring a noise filter to prevent erroneous triggering, and to ensure reliability, it is expensive, making it difficult to install in a home information communication network.・It had the disadvantage of being too complex and expensive to be used in a transmission line such as RI, which requires extremely short distances and low speeds.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and therefore, it is an object of the present invention to apply to very short distance and low speed transmission lines such as home information communication networks. An object of the present invention is to provide a simple, low-cost data transmission transmitting/receiving circuit suitable for use in the field.

[Key points of the invention]

The transmitting/receiving circuit for data transmission according to the present invention connects the negative polarity of the first power source and the positive polarity of the second power source to lead to the ground potential, and connects the negative polarity of the first power source and the negative polarity of the second power source. A transistor pair consisting of a series connection of first and second transistors is connected between the terminals, a first communication terminal is connected to the ground, and a second communication terminal is connected to the transistor pair. By connecting to a connection point between both the first and second transistors, and turning on any of the first and second transistors by the control output from the transmission control logic circuit, or turning on neither, a transmitting circuit capable of transmitting a binary code or a ternary code via the first and second communication terminals; and the bases of the third and fourth transistors whose bases are interconnected. Connection point between bases (connection point between bases)
is connected to the second communication terminal via a resistor, and the third
The emitters of the transistors and the emitters of the fourth transistor are connected to each other, and the connection point is led to the ground potential on one side, and the bases are connected to the connection point on the other side via a resistor, and the connection point is connected to the first communication terminal. Either of the third and fourth transistors is turned on depending on which of the second communication terminals receives a signal with a higher potential, or the first i1M other terminal and the second communication terminal are set at the same potential. When the signal is received and turns on and off both the third and fourth i-transistors, a 24-bit code or a ternary code is extracted from the collector side of each of the third and fourth transistors and input to the logic It is characterized by consisting of a receiving circuit configured to input into the circuit, and one or both of the following.

[Embodiments of the invention]

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The transmitter/receiver circuit shown in the figure has a transmitter circuit format of 2 power supplies and 5EP.
P (Single Ended Pu5h-Pu11
) circuit format, and shows a transmitting/receiving circuit when balanced transmission is performed while direct current is superimposed on a metallic pair cable.

In the same figure, Ql and C2 are transmission transistors, C
3 and C4 are receiving transistors, C5 is a transistor for level shifting the output of transistor C4, P
WI and PW2 are power supplies, ■. , V, , V- are power supply terminals, PT is a pulse transformer, T1 to T4 are terminals of the pulse transformer, and input/output terminals for transmitting/receiving signals, C1
and C2 are capacitors for AC/DC isolation, CC is a logic circuit for transmission control, CA is a metallic pair cable, R1 is a resistor for setting the input impedance of the receiving circuit, and R2 is a transistor Q3. Q4 bias setting resistor, R3 is collector load resistor of transistor Q3, R4 is transistor Q4
R5 is the collector load resistance of transistor Q5 and the bias resistance of transistor Q5.

CC is a transmission control logic circuit, and when a transmission command is given to the circuit CC by means not shown, the transmission output terminal T is output. The required output is generated in utl+'rouL2,
It controls on/off of the transmitting transistors Ql and Q2.

Further, when a reception command is given to the logic circuit CC by means not shown, the logic circuit CC receives the reception input terminal R.
The received codes from the receiving transistors Q3 and C4 are taken in and decoded through the in.

Next, the circuit operation will be explained. First, the operation of the transmitting circuit will be explained.

The transmitting transistors Ql and Q2 constitute the transmitting circuit of the two-power supply 5EPP type 2, and when the transistor Q1 is on and the transistor Q2 is off due to the transmitting signal output from the transmission control logic circuit CC, V, - Q, →1゛2→T1→■. (ground) circuit causes a positive current to flow through the primary side of the pulse transformer PT. Thereby, terminal T3. on the secondary side of the transformer PT. Through T4 and further capacitors CI, C2
A "10 level" code is sent to the cable CA via the cable CA.

Similarly, when the transmitting transistor Q1 is off and C2 is on, (2). (Ground) -T1→T2-Q z→■- A current flows in the reverse direction to the primary side of the pulse transformer PT. As a result, terminal T3. on the secondary side of pulse transformer PT. A "-level" code is sent via T4.

In this way, it is possible to send out double-stream binary codes. Moreover, if transistors Q1 and C2 are all turned off, this state corresponds to high impedance "0", and eventually the output voltage becomes "1" and high impedance "1".
It is possible to send out a ternary code by θ''.The power supply voltage is ±5 (V), the turns ratio of the pulse transformer PT is l:l, and the saturation voltage of the output transistors Ql and Q2 and the transmission loss of the pulse transformer PT are If you ignore this, you can obtain a transmission level of ±5 [■].

One end of the winding on the transmitting/receiving circuit side of the pulse transformer PT] 1 is at ground potential. While connecting to the terminal, N P N
The emitters of the transistor Q3 and the PN-P transistor Q4 are connected to the V0 terminal at ground potential, and the other end '1'2 of the pulse transformer winding is connected to the transistor Q3. A simple receiving circuit can be obtained by connecting both terminals of Q4.

Next, the operation of the receiving circuit will be explained. The code (current pulse) transmitted by cable CA is connected to capacitors CI and C.
If the terminal T2 of the pulse transformer winding becomes a higher potential than the V0 terminal as a result of the input through the pulse transformer I) ), the base and emitter of transistor Q3 are biased in the forward direction, so transistor Q3
is turned on, and a change in potential is taken out from the collector of transistor Q3 and taken into the Rin terminal of the transmission control logic circuit CC.

As a result of the code transmitted by cable CA being taken in via pulse transformer PT, terminal T2 becomes ■, contrary to the above. When the potential is lower than that of the terminal (in this case, it is assumed that − level “1” is received), the transistor Q4
Since the base and emitter of the transistor are biased in the forward direction, the transistor Q4 is turned on, and a change in potential is taken out from the collector of the transistor Q4. After this change in potential is subjected to a required level shift by the transistor Q5, it is transferred to the transmission control logic circuit. It is taken into the Rin terminal of CC.

The reason why the level shift operation by the transistor Q5 is necessary is that, as is clear from the figure, the logic circuit CC
is supplied with power by the power source PWI (V, and V.), whereas transistor Q4 is connected to another power source PW2 (V- and Vo), so the collector output of transistor Q4 is This is because if the signal is input to the logic circuit CC as it is without level shifting, the level may be insufficient and the logic circuit CC may not operate.

In this way, a ten-level received signal (code) can be received after being double-wave rectified.

Regarding the reception of the ternary code AMI (bipolar code), when the signal "1" is received, the transistor Q3. Q
When either one of Q4 is turned on and 0'' is received, reception is possible each time transistors Q3 and Q4 are both turned off.

Furthermore, if the power supply voltages of power supplies PWI and PW2 are equal and the resistance values of R3 and R5 are equal, the transistor Q
4 turns on, Q5 turns on, and resistor 173 and R5
Since the potential at the connection point of is almost equal to the ground potential,
A single-current binary code can be easily obtained from the connection point of R3 and R5, that is, the collector output of Q3. Therefore, the collector output of this transistor Q3 or, if necessary, its inverted output can be directly input to the transmission control logic circuit CC as a reception signal.

Next, the transmitting/receiving circuit according to the present invention has a transmitting/receiving collision detection function that detects when a transmitting/receiving collision phenomenon occurs during a transmitting operation.
This will be explained below.

In FIG. 1, when the transmitting transistors Ql and Q2 are both off and transmitting "0", the receiving transistor Q3. Since Q4 can receive a low level "1" from another transmitting circuit (not shown), a receiving operation may occur during a transmitting operation in this way. Having determined this, the transmission control logic circuit CC knows that there has been a collision between transmission and reception, and can thereafter stop the transmission operation of the transmission circuit and continue only the reception operation.

Furthermore, in the transmitting/receiving circuit shown in FIG. 1, when the transmitting transistor Q1 is on, the terminal T2 has a higher potential than the terminal v0, turning on the transistor Q3, and when the transmitting transistor Q2 is on, the transistor Q4 is turned on. Therefore, the receiving circuit can also be provided with a function of monitoring the transmitted signal.

In this case, the lowest reception level is the transistor Q3, Q4
If the forward drop voltage between the base and emitter of Q3 is Vbe, 1Vbe or more is required, but in order to ensure stability of reception operation and adjust bias, resistor R2, which is larger than R1, is connected to transistor Q3. When connected between the base and emitter of Q4, the minimum reception level will be within the range of 1vbe to 2Vbe. If Vbe=0.7 (■), the minimum reception level is 2.
In the case of Vbe=1.4 CVD, the maximum allowable transmission loss is approximately 11 [dB] for a transmission level of 5 [V]. Therefore, the receiving circuit according to the present invention has a transmission speed of several 10
(Wb/s) or less, and when used at a transmission distance of several 100' (rn) or less, it can be sufficiently put to practical use.

In addition, in FIG. 1, when direct current is superimposed on the transmission path, it is sufficient to connect only three capacitors, either 01 or C2, as AC/DC separation capacitors. Of course, if there is no DC superimposition, use the AC/DC separation capacitor CI.

Both C2 are unnecessary.

FIG. 2 shows an embodiment in which the transmitting/receiving circuit shown in FIG. 1 and the cable CAO as a transmission line are coupled by a capacitor C1 without intervening a pulse transformer.

Further, FIG. 3 shows an embodiment in which the transmitting/receiving circuit and the cable CA are directly connected without intervening a pulse transformer or a capacitor.

The transmitting and receiving operations of each embodiment shown in FIGS. 2 and 3 are similar to those of the embodiment shown in FIG. As shown in FIG. 2, the transmitter/receiver circuit and the transmission line may be coupled by a capacitor, or if direct current superposition is not required in the transmission line, they may be directly coupled as shown in FIG. 3.

In the embodiment shown in FIG. 2, in order to perform unbalanced transmission through a transmission line in which DC is superimposed, AC/DC separation is simply performed using a capacitor C1, and the ground terminal V0 is directly connected to one side of the transmission line. In the embodiment shown in FIG. 3, the transmission path and the transmitting/receiving circuit are directly connected, resulting in unbalanced transmission.

In each of the embodiments shown in FIGS. 1 to 3, noise resistance can be further improved by adding a capacitor between the base and emitter of the receiving transistors Q3 and C4, that is, in parallel with the resistor R2. Further, if the collector outputs of the transistors Q3 and C4 are taken out individually, it is also possible to individually detect the error signal of the AM* code or double-current binary code that has been subjected to a violation.

〔Effect of the invention〕

As explained above, according to the present invention, a transmitter/receiver circuit for transmitting data at low speed over a short distance transmission path can be configured with only a few transistors without the need for compensating for waveform distortion. The transmitting/receiving circuit according to the present invention has the advantage that even when the circuit is constructed from individual parts, the cost can be reduced, and it can also be integrated into an IC together with the transmission control circuit.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing one embodiment of the present invention, Figures 2 and 3 are circuit diagrams showing one embodiment of the present invention.
The figures are circuit diagrams showing other embodiments of the present invention. Symbol explanation 01-Q5...Transistor, R1-R5...Resistor, CI and C2...Capacitor, V,,V. 5 ■-
...Power terminal, PWI and PW2...Power supply, PT・
...Pulse transformer, CA...cable, CC...
Transmission control logic circuit, T1 to T4...Pulse transformer terminals as well as input/output terminals for transmitting and receiving signals Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki

Claims (1)

[Claims] l) The negative polarity of the first power source and the positive polarity of the second power source are connected to lead to the ground potential, and the positive polarity of the first power source and the negative polarity of the second power source are connected. A transistor pair consisting of a series connection of first and second transistors is connected between them;
A first communication terminal is connected to the ground potential, a second communication terminal is connected to the connection point between the first and second transistors forming the transistor pair, and the control output from the transmission control logic circuit A binary code or a ternary code can be sent through each of the first and second communication terminals by turning on either the first and second transistors or by turning on neither of them. The transmission circuit and the connection point between the respective conductors of the third and fourth transistors whose conductors are connected to each other (connection point between conductors)
is connected to the second communication terminal via a resistor, and the third
The emitters of the transistors and the emitters of the fourth transistor are connected to each other, and the connection point is led to the ground potential on one side, and the bases are connected to the connection point on the other side via a resistor, and the connection point is connected to the first communication terminal. Either of the third and fourth transistors is turned on depending on which of the second communication terminals receives the higher potential signal, or the first communication terminal and the second communication terminal are connected to the same potential. By not turning on both the third and fourth transistors when a signal is received, a binary code or a ternary code is taken out from the collector side of each of the third and fourth transistors and inputted to the logic circuit. 1. A transmitting/receiving circuit for data transmission, comprising: a receiving circuit; and one or both of the following.