JPS60253342A - Transmission and reception circuit for data transmission - Google Patents

Abstract

PURPOSE:To obtain an inexpensive transmission/reception circuit which performs transmission of data through a short-distance transmission line at a low speed, by using just several units of transistors with no compensation needed for waveform distortions. CONSTITUTION:Transistors TrQ1 and Q2 for transmission constitute a DEPP (Double Ended Push-Pull) type transmission circuit. When the TrQ1 and Q2 are turned on and off with the transmission signal sent from a logical circuit CC for control of transmission, a forward current flows to the primary side of a pulse transformer PT. Then the ''+'' codes are transmitted via terminals T4 and T5 of the secondary side. While the ''-'' codes are transmitted if the TrQ1 is turned off and the TrQ2 is turned on. Therefore the transmission is possible for a double-current binary code. Then the transmission of a ternary code is also possible when the TrQ1 and Q2 are turned off. When the terminal T1 (T2) has a lower potential than a power supply terminal V+ owing to the reception code, a TrQ3 (Q4) is turned on. Then the variation of potential is extracted out of the collector of the TrQ3 (Q4) and fetched to an Rin terminal of the circuit CC. Thus the reception codes of + or - levels can be received through full-wave rectification. When a ternary code is received, the TrQ3 and Q4 are separated from each other together with discrimination of + or - levels. At the same time, ''0'' is discriminated as reception when both TrQ3 and Q4 are turned off.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention is directed to a method for transmitting low-speed digital data over a transmission line that is short enough to eliminate the need to compensate for distortion in the transmission waveform. This invention relates to a simple transmitting and receiving circuit for data transmission.

More specifically, in response to the increasing sophistication and complexity of household devices including new media devices, disaster prevention and crime prevention devices, and the computerization of the home, these home information devices will be centrally housed and organically combined. Home information communication network HA N (tlomeAre+i Inform
The present invention relates to a transmitter/receiver circuit for data transmission suitable for use in Gagaru HAN and the like.

To give a specific example, in a home, if you want to control the blinking of lights in each room, entrance, etc. from the kitchen, you would use a network that runs through the home, and from the transmitting circuit in the kitchen to the receiving circuit in each room, etc. Control commands are transmitted in digital data format, and the present invention can be said to relate to a simple transmitting/receiving circuit suitable for such uses.

[Prior art and its problems]

Conventionally, data transmission refers to data transmission performed at high speed over a relatively long distance transmission line, for example, for computer secret communication systems in business offices, such as LAN (+: +- Cal Area Network). was considered, so it was necessary to synchronize the focus between transmitting and receiving, and for this reason a differential operational amplifier with high sensitivity and hysteresis characteristics was developed.

Waveform equalizer to compensate for waveform distortion, perform clock extraction l)
In addition, depending on the transmission code format, “O” in the transmission data may be required to facilitate clock extraction.
``We needed a scrambler and descrambler to perform continuous suppression.

Furthermore, even when the transmission distance is relatively short and the transmission speed is low, if start-stop synchronization is achieved and DC superposition is applied to the data transmission transmission path, the DC component is small and the output power is low. (Although RZ codes with small Chete ratios are often used as transmission codes, in order to extend the pulse width, metastable multi-high breaks triggered by the rise of the RZ code, monostable Marna high The configuration of the transmitter/receiver circuit is complicated, such as requiring a noise filter to prevent erroneous tripping force on the break, and is expensive to ensure axial stability, making it difficult to use at home. It also had the disadvantage of being cumbersome and expensive to use for extremely short V1, low-speed, and low-speed transmission lines, such as those used in internal information and communications networks.

[Purpose of the invention]

The present invention has been made in order to eliminate the drawbacks of the prior art as described above, and therefore, an object of the present invention is to provide an extremely short-distance and low-speed transmission line, such as a home information communication network. An object of the present invention is to provide a simple, low-cost data transmission transmitter/receiver circuit suitable for use in the following.

[Key points of the invention]

The key point of the present invention is to convert the transmitter circuit into an electric RDEPP (Doubt
(Le Ended Pu5h-Pull) It is configured depending on the circuit type and performs balanced transmission without superimposing DC on the metallic bare cable, or the transmitting circuit is configured with one power source SE.
P P (Single Ended Pu5h-Pu
ll) The receiving circuit is configured in a circuit format, and the receiving circuit connects the center tap of the winding on the transmitting/receiving circuit side of the pulse transformer and each emitter of the two transistors to one polarity of the power supply, and connects both terminals of the winding to each input terminal. The present invention is configured such that both transistors are connected to each other through an impedance setting resistor.

[Embodiments of the invention]

The present invention will now be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

The transmitting/receiving circuit shown in the figure has a transmitting circuit format of one power supply D E
P P (Double Ended Pu5h-P
u11) Circuit type, metallic bare cable CA
Transmitting/receiving circuit when performing balanced transmission while superimposing DC on
This is what is shown. In the figure, Ql and C2 are transmitting transistors, C3 and C4 are receiving transistors, R1 and R2 are resistors for setting the input impedance of the receiving circuit, and R3 and R4 are transistors Q3. The bias setting resistor of Q4, R5 is the transistor Q3. Collector load resistance of Q4, C1 and C2 are AC/DC separation capacitors,
PW is the power supply, ■.

and V. is a power supply terminal, P'F is a pulse transformer, Tl~
'1'5 is the terminal of the pulse transformer as well as the input/output terminal for transmitting/receiving signals, CC is the logic circuit for transmission control, CA
is a metallic bare cable.

When a transmission command is given to the transmission control logic circuit C0C by means not shown, the transmission output terminal '1' is output. 1ILl
+1′. A required output is generated at uL2, and the on/off of the transmitting transistors Ql and Q2 is controlled.

Further, when a reception command is given to the transmission control logic circuit CC by means not shown, the logic circuit CC receives the transmission control logic circuit CC through the reception input terminal R4n. Q4
It is designed to capture and decode the received code from the computer.

Next, the circuit operation will be explained. First, the operation of the transmitting circuit will be explained. The transmitting transistors Q1 and C2 are DEP
I) type transmitting circuit is configured, and if transistor Q1 is on and transistor Q2 is off due to the transmitting signal output from the transmission control logic circuit CC, then (1). -T 3-'rl →Q 1-VO (ground) circuit causes a positive current to flow through the primary side of the pulse transformer PT. As a result, the end rT4. on the secondary side of the I-lance 1)'r. Through T5 and further capacitor C
A sign of ``+level'' is sent to cable CA via I and C2.

Similarly, when the transmitting transistor Q1 is off and C2 is on, (2). -'r3-T 2-Q 2-Vo (cland) current flows in the primary side of the pulse transformer I)'r' in the reverse direction. This allows the pulse transformer PT
through terminals i" 4 and 'I" 5 on the secondary side of °
A code of C "-level" is sent out.

In this way, it becomes possible to send out the double-flow number 24INQ. Also, if all transistors Ql and Q2 are turned off,
This state corresponds to high impedance "O゛°," and eventually it becomes possible to send out a ternary code with "1" of the high-impedance signal and "0" of high impedance. ■Power supply 1) E A pulse transformer with a center tap (8 ratio = 1:1:l) is essential for the P P circuit. If you ignore it, village 5
It is possible to obtain the output level of (V).

Center tap of the winding on the transmitting/receiving circuit side of the pulse string
r 3 and i+ N ll type 1-transistor Q3. Connect each emitter of Q4 to the high potential side terminal - of the power supply, and connect both terminals of the center-tapped winding T1. T''2 is connected to transistor Q3 through input impedance setting resistors R1 and R2.
A simple receiving circuit can be obtained by connecting each terminal to each terminal of Q4.

Next, the operation of the receiving circuit will be explained. The code (current pulse) transmitted by the cable CA is the condenser CI, C.
As a result, the terminal T1 becomes the power supply terminal ■.

When the potential becomes lower (in this case, it is assumed that 10 levels of "l" is received), the transistor Q3 is turned on because the base and emitter of the transistor Q3 are forward biased, and the transistor Q3 is turned on. The potential change is taken out from the collector of Q3, and the Ri of the transmission control logic circuit CC is
It is taken into the n terminal.

As a result of the code transmitted by the cable CA being taken in via the pulse transformer PT, the terminal 7'T2 becomes a lower potential than the power supply terminal V (in this case, the - level 19 is received), the transistor Q4 is biased in the forward direction between its base and emitter, so the transistor Q4 is turned on, and a potential change is taken out from the collector of the transistor Q4, and the transmission control logic circuit CC is taken into the Rin terminal of.

In this way, the received signal (code) of the signal can be rectified in both waves and received. In other words, the ± level “
When '1' is received, either transistor Q3 or Q4 is turned on, and when '0' is received, transistor Q3.Q4 is turned on.
Since transistors Q3.04 are both turned off, transistors Q3. You can easily obtain a jet binary code from the Weikert-OR output as shown in the figure, which is simply by connecting the Nirctors of Q4.Logic circuit C
CO) It is possible to take in the R1n terminal.

When receiving a ternary code AMI (bipolar code), instead of connecting the collectors of transistors Q3 and Q4, separate them and input them into the logic circuit CC independently (therefore, two Rin terminals are required). will be required)
In this way, Trebel's "1" and -level "l"
2, and both transistors Q3. When Q4 is off, "0" may be identified as reception.

Note that depending on the logic processing in the logic circuit CC, an inverter may be connected to the Rin terminal and the transistor Q3 may be connected to the Rin terminal.
．． Of course, the collector output of Q4 may be inverted by the inverter and then taken into the logic circuit CC.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. In the embodiment shown in the figure, the transmitting circuit format is one power supply S E P P
(Single Ended Pu5h-Pull
) shows the circuit format. In the figure, C3 is an output capacitor of a j-times circuit of 1 power supply 5EPP type, and other parts that are the same as in FIG. 1 are given the same symbols.

Next, the operation of the transmitting circuit will be explained. Transmission control logic circuit C
When the transmission signal output from C turns on the transistor Ql and turns off the transistor Q2, ■, →Q1→C3→
Tl→′l゛3→■. (ground) circuit causes a positive current (charging current of capacitor C3) to flow through the primary side of pulse transformer l)T. This makes it possible to transmit "10 levels" of codes.

Similarly, when the transmitting transistor Ql is off and Q2 is on, the circuit of V0→'F3-◆T1→C3→Q2→V0 causes a reverse current (capacitor C3 discharge current) flows. This allows a "-level" code to be sent.

In this way, it is possible to send out a double flow 2 (a code).

Also, if both transistors Ql and Q2 are turned off,
This state corresponds to high impedance "0'", and it becomes possible to transmit a ternary code using "1" of the threshold and "O" of high impedance. lThe output voltage of the power supply 5EPP circuit is half of the power supply voltage, so
To obtain a send level of ±5 [■], at least 10
(V) power supply voltage is required.

In addition, in order to construct a simple receiving circuit, only one half of the winding on the transmitting/receiving circuit side of the center combined pulse transformer (turn ratio 1:1:1) is used as the load of the transmitting circuit. Therefore, if the power supply voltage is 10 (V) and the saturation voltage of the output transistor and the transmission loss of the pulse transformer are ignored, a sending level of ±5 [■] can be obtained.

Center tap T of the winding on the transmitting/receiving circuit side of the pulse transformer
3 and NPN transistor Q3. The emitter of Q4 is at ground potential. A simple receiving circuit can be obtained by connecting both ends T1, 1'2 of the center-tapped winding to the input impedance setting resistors R1 and R2, and to the respective gates of transistors Q3 and Q4. be able to.

That is, the terminal TI is ■. When the potential is higher than the terminal, the transistor Q3 is turned on because the base and emitter of the transistor Q3 are biased in the forward direction, and conversely, the terminals 1 and 2 are turned on. When the potential is higher than that of the terminal, the transistor Q4 is biased in the ill'4 direction between its base and emitter, so the transistor Q4 is turned on, and the signal received by the signal is double-wave rectified and received.

When receiving a ternary code AMI, the “I''
When receiving the transistor Q3. When one of transistors Q4 turns on and receives "0", transistors Q3. Since transistors Q4 are both turned off, transistors Q3. A quasi-current binary code can be easily obtained from the wired OR output simply by connecting the collectors of Q4. Therefore, this wired-OR output or, if necessary, its inverted output can be directly input to the transmission control logic circuit CC as a reception signal.

Next, the transmitting/receiving circuit according to the present invention has a transmitting/receiving collision detection function that detects when a transmitting/receiving collision phenomenon occurs during a transmitting operation.
The dirt will be explained below.

In FIG. 1 or 2, the transmitting transistor Q1
．． When Q2 are both off and transmitting "O", receiving transistors Q3 and Q4 can receive "1" of -1 level from other transmitting circuits (not shown), so they cannot be transmitted in this way. B. Receive operation may occur during operation 3.

Having determined this, the transmission control logic circuit CC knows that there has been a collision between transmission and reception, and can thereafter stop the transmission operation of the transmission circuit and continue only the reception operation.

Furthermore, in the transmitting/receiving circuit shown in FIG. 1 or 2, when the transmitting transistor Q1 turns on, the receiving transistor Q3 turns on, and when the transmitting transistor Q2 turns on, the receiving transistor Q4 turns on. ,
It is also possible to provide the receiving circuit with a function of monitoring the transmitted signal.

The minimum reception level in the embodiments of FIGS. 1 and 2 is:
Transistor Q3. If the forward voltage drop between Q4's heath and emitter is Vbe, it will require at least IVba, but a resistor R is required to ensure the stability of the receiving operation and adjust the bias.
1, resistors R3 and R4 larger than R2 are connected to transistor Q3.
．． When connected between the Haas and emitters of Q4, the minimum reception level will be within the range of 1vbe to 2Vbe. V
If be = 0.7 (V), the minimum reception level is 2 V
When he=1.4 [■], the maximum allowable transmission loss is approximately 11 [dB] for a transmission level of 5 [■].

Therefore, the receiving circuit according to the present invention has a transmission speed of several 10 (
If the transmission distance is several 10,100 Kb8 or less, it can be put to practical use.

In the embodiments shown in FIGS. 1 and 2, noise resistance can be further improved by adding capacitors between the emitters of the receiving transistors Q3 and Q4, respectively. . Furthermore, if the collector outputs of the transistors Q3 and Q4 are taken out individually, it is possible to individually detect the t level of the AMI code or the double current 2-1 code, which has a bioresin effect. Furthermore, even when direct current is superimposed on the transmission path, it is sufficient to connect only one of c1 or c2 as an AC/DC separation capacitor. Of course, if there is no direct current superimposition, both the AC/DC separation capacitors CI and C2 are unnecessary.

〔Effect of the invention〕

As explained above, according to the present invention, a transmitter/receiver circuit for transmitting data at low speed over a short distance transmission line can be configured with only a few transistors without the need for waveform distortion compensation. Even if the circuit is composed of individual parts, the cost can be reduced, and the IC can be used together with the transmission control circuit 5.
The transmitting/receiving circuit according to the present invention has the advantage that it is suitable for the case where the transmitting/receiving circuit according to the present invention is intended to be used in various ways.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the invention, and FIG. 2 is a circuit diagram showing another embodiment of the invention. Code explanation 01-Q4...transistor, R1-R5...resistance, 01-C3...capacitor, PW...power supply, ■,
and V,...power supply terminal, CC...transmission control logic circuit, CA...cable, PT...pulse transformer,
Tl-T5: Terminal of the transformer as well as input/output terminal for transmitting and receiving signals Patent attorney Akio Namiki Patent attorney Kiyoshi Matsuzaki

Claims (1)

[Claims] 1) The primary side center tap of a center-tapped pulse transformer whose secondary side is coupled to a transmission line is connected to the first polarity of a power supply, and both primary side terminals of the transformer are connected to the first polarity of a power source. The first one
a first transistor between the terminal of the power source and a second polarity of the power source, and a second transistor between the second terminal and the second polarity of the power source, respectively. which of the first transistor and the second transistor is turned on by the control output from the transmission control logic circuit;
Alternatively, by not turning on any of them, a transmitting circuit that can send a binary code or a ternary code to the transmission line via the transformer, and a transmitting circuit that connects the first terminal of the transformer to the Similarly, the second terminal of the transformer is connected to the base of the fourth transistor via a resistor, and the third. The respective emitters of both of the fourth transistors are connected to the first polarity of the power source, and a resistor is connected between each of the emitters and the base thereof, and the third... The respective collectors of both fourth transistors are led to the signal input side of the logic circuit, and the voltage of the fourth transistor is determined depending on which of the first terminal and the second terminal of the transformer receives a signal having a potential lower than the center tap potential. Either one of the third and fourth transistors is turned on, or a signal having the same potential as the center tap potential is received at the first and second terminals, and the third and fourth transistors are turned on. a receiving circuit that allows a binary code or a ternary code to be input into the logic circuit by not turning on both of the fourth transistors; and one or both of the following. 2) Connect the primary side center tap of a center tapped pulse transformer whose secondary side is coupled to the transmission line to the second polarity of the power source, and connect the first polarity and the second polarity of the power source. A circuit consisting of a series connection of a first transistor and a second transistor is connected between the polarities of the first transistor and the second terminal of the primary side terminals of the transformer. Terminal-
A capacitor is connected between the transistors and the connection point between the transistors in the series connection, and either the first transistor or the second transistor is turned on by the control output from the transmission control logic circuit to charge and discharge the capacitor. A current is passed through the primary side of the transformer, or a current is passed through the primary side of the transformer. By not turning on both second transistors,
a transmitting circuit capable of sending a binary code or a ternary code to a transmission line via the transformer; a first terminal of the transformer to the base of a third transistor via a resistor; The second terminals are connected to the terminals of the fourth transistor through resistors, respectively, and the third terminals are connected to the terminals of the fourth transistor through resistors. The emitters of both the fourth transistors are connected to the second polarity of the power supply, and a resistor is connected between the emitters and the bases of the fourth transistors. The respective collectors of both fourth transistors are led to the signal input terminal of the logic circuit, and the voltage of the fourth transistor is determined depending on which of the first terminal and the second terminal of the transformer receives a signal having a potential lower than the center tap potential. Either the third and fourth transistors are turned on, or a signal having the same potential as the center tap potential is received at the first terminal and the second terminal, and the third. By not turning on both of the fourth transistors, a binary code or a ternary code can be taken into the logic circuit. 1. A transmitting/receiving circuit for data transmission, comprising: a receiving circuit having the following structure; and one or both of the following.