JPS581364A - Pulse output circuit - Google Patents

Abstract

PURPOSE:To reduce the collector loss of a transistor (TR) in a differential couple without generating any error signal, by inserting a current control element between the emitters of the differential TR couple and a power source. CONSTITUTION:The emitters of a differential couple of TRs 41 and 42 are connected mutually and further connected to a power source VEE through a TR43 as a current control element. The inputs of a two-input OR circuit 46 are connected to the bases of said TR couple, and the output of the circuit 46 is supplied, together with a clock signal, to an AND circuit 47, whose output is connected to the base of the TR43. Further, the neutral point of the primary winding of a transformer 49 is connected to a power source VCC. Then, input signals A and B are applied to the bases of the TRs 41 and 42 to obtain a pulse output Z4 at the secondary winding of the transformer 49.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a pulse output circuit used, for example, in digital communications.

Conventionally, the pulse output circuit used in the digital communication section is 1 as shown in Fig. 4, 2 WJ, and 3.
The circuit is used in The circuit shown in FIG. 1 is the most basic of four. That is, the collectors of transistors 11 and 12 are connected to the transformer 01 order tS and both terminals, and the emitter and the emitter are connected to each other and connected to the power supply through a resistor, and the above-mentioned transformer I! The midpoint of the primary winding is connected to another power supply, the input signal is supplied to the two transistor paces, and the output signal is the secondary of the transformer described above.
It is sharpened so that it can be taken out from both ends. The operation of the above circuit will be explained using the waveform diagram of FIG.

A signal with the waveform shown in FIG. 4 (1) is supplied to the input of the transistor 110, and a signal with the waveform shown in FIG. 114 (2) is supplied to the input of the transistor 12.
zl) has a waveform as shown in FIG. 4(3)K. 4 (1), (2) The waveform supplied to K is 1/Snow Noreen (the logic signal is "1" and rOJ is repeated), but in this case, the current flowing through the transistor 11 is the input waveform of the 4th WJ (1 ), a predetermined current flows through IK when it is at a high level, and turns off when it is at a low level. Similarly, the transistor 12 corresponds to the 411th input waveform (2), and a predetermined current flows when the waveform (2) is at a high level, and is turned off when the waveform (2) is at a low level. As can be seen from the waveform diagrams in Figures 4 (1) and (2), in the circuit in Figure 1, the transistor conduction period is long, so the transistor O collector loss is large, and a transistor that can withstand this must be used. There is a problem that it must be done.

The circuit of the second WA is proposed to solve the problem of improvement, and consists of nine circuits, with transistors 21 and 22 corresponding respectively to transistors 11 and 12 in the circuit of FIG.
Connect another transistor 23 to the emitter of the transistor 23, and apply a link signal (C) to the pace of the transistor 23 to obtain the transformer 02 output (I2).
). In this circuit, when the signal is at a low level, the transistor 23 is turned off, and no current flows through either the transistor 21 or 28, so compared to the circuit shown in FIG.
The period during which the current is applied is short, and therefore the collector loss is also low. However, in this circuit, (M), (B) When both input signals are non-signal (low level) KV) When Lanzostar 2s is on, either transistor 21 or 22 (each transistor's pace evening voltage v1. When there is no signal, O potential turns on), so Figure 4 (5)
A current as shown by the broken line flows at the point. Its ninth output CZ2)K is a new design that sends a nine-noise pulse (positive in the figure) in phase with the mother pulse, as shown by the broken line (in other words, indicates the case where transistor 22 is easily turned on). This causes many problems.

The circuit of the 3rd WJ uses the basic circuit shown in Figure 1 in parallel, and constructs a differential transistor pair by reducing the effect of the carrier accumulation time of the transistor on the output (*8) 0 waveform. A logic circuit is provided in addition to the transistors 31, 3233 and 340, and the input signals of the transistors 31 to 34 are applied as a signal (C). The operation of this circuit will be explained using the waveform diagram in FIG. Chapter S
The top row (1) K of the figure shows an input signal in decimal notation which is processed by the Δ' pulse output circuit of H, and the signal is transmitted by a well-known circuit (not shown) to 1II (2) and < 3) K
It is divided into two signals as shown.

These two messages correspond to logic 1 circuits 35 and 36 (
, ) and (b) as input signals. No. 5
The waveform of FIG. 4 is the waveform of a clock signal, which is added to the inputs of the error lock signal circuits 35 and 36. When the above-mentioned signal is supplied to this circuit, the waveform of the output (d) of the logic circuit 35 in the circuit of FIG. 3 becomes the inverted output of the logic circuit 350 as shown in FIG. 5 (5). (・
) is as shown in FIG. 5(6), and the waveform of the output (f) of the logic circuit 36 is as shown in FIG. 5(7).
The waveform of the 0-inverted output (g) is K as shown in FIG. 5 (8).

Also, the transistor 310 current (11),) Ranjis,'
Current of I32 (I2),) Current of Tunzoster 33 (I3
) and transistor 340 current (I4) have waveforms (9) and (1G) in FIG. 5, respectively.

(11) and (it)K are turned on and off as shown. Therefore, the output (I3) has a waveform as shown in FIG. S (13). If we focus on the current (I1) or I4) of each transistor in the circuit K of Figure 3, we can see that the inputs (2) and (3) of Figure S, although it is also related to the applied input signal. If the signal is given, then ql
The period in which K12.14 is turned on is long, and the collector losses of transistors 32 and 34 are large, and the above-mentioned problems have not been solved. Also, for an average input signal, the tendency of the energization period in 12.14 above to be long is due to the fact that the t
Well, it fits.

An object of the present invention is to solve the problem K in the conventional circuit described above.
Considering that, the differential transistor pair constituting the output circuit is connected to each other, and a pressure current control element is inserted between the input signal and the power supply circuit, and the input signal and the
Based on the concept of supplying and controlling a logical operation output of a signal, it is possible to reduce the collector loss of a transistor used in a differential transistor pair without generating an erroneous signal.

In the present invention, the NRZ input signal is used to differentially turn on/off the NRZ input signal.
・Driving the differential transistor pair that is turned off i5, and adding the current of each transistor that makes up the transistor pair, the
a logic circuit that calculates the AND of the input signal of the differential transistor pair and a clock controlled by the mosquito input signal, 4 pulses, in a current switching type delta pulse output circuit that outputs a value of 11 Z/ll pulses; and a current control element that is inserted between the mutually connected rays and rays of the pair of skeleton differential transistors and the electric current control element and is controlled by the output of the skeleton logic circuit. is provided.

A circuit diagram of an Ot4 pulse output circuit as an embodiment of the present invention is shown in FIG. 6, and a waveform diagram explaining the operation of the Ot4 pulse output circuit is shown in FIG. 7. In FIG. The collector of transistor 41 is connected to one end of the primary winding of transformer 49, and the collector of transistor 42 is connected to the other end of the primary winding of transformer 49. rays of transistors 41 and 42;
The terminals are connected to each other and connected to a power supply V□ via a transistor 43, which is a current control element in the present invention, and a resistor. A two-man power OR circuit 46, which is one of the logic circuits, has one input connected to the pace of the transistor 41 and the other input connected to the pace of the transistor 42, and the output of the OR circuit 46 is connected to the other one of the logic circuits. U circuit 470
It is connected to one input, and the other input of the phantom circuit 41 is given a clock signal from the outside. APJDgil-ro 47
The output of transistor 430 is connected to transistor 430.

The midpoint of transformer 490 primary winding is connected to power supply vCc.

Transistor 41+2) pace is the first input signal (mu)
However, the pace of transistor 4 is 820 input signals (Im
) is added to the secondary 11kl of the pulse output transformer 49.
This is because it is generated as the llK output (z4).

In the waveform diagram of Fig. 7, (1), (2) and (3)
show the waveforms of the first input signal (mu), the second input signal (1), and the black and red signals (c), respectively. AN
The waveform of the output (D) of the D circuit 47 is lll7m11(4)
K, output (Z4) 0 waveform is shown in Figure 117 (5)K.

The four-way signal (C) must be in a fixed phase relationship with the input signal. According to the simplified diagram in Figure 6, current no longer flows through the transistors that make up the K differential transistor during the period when the Rip and R signals are off (low level) and during the free period (when both input signals are low level). , the collector loss is in transistors 41 and 42 when the input signal is 1
/2 At the time of /f turn, in addition to the large IIK reduction to 174, the collector loss of transistor 43 is also lower than that of transistor 4.
Since it can be smaller than 1 or 42, a small signal transistor can be used instead of a high output transistor.

A Δ pulse output circuit as another embodiment of the present invention is shown in FIG. 118, and a round waveform diagram illustrating the operation of this circuit is shown in FIG. This circuit corresponds to the conventional circuit shown in FIG. 3 with nine circuits, taking into consideration the effect of reducing the influence of the carrier accumulation time of the transistor on the waveform of the output signal. In this circuit, transistors 51 and ! ! a differential transistor pair consisting of 2 and a differential transistor pair consisting of transistors s3 and s4,
The collector of the transistor s1 and the collector of the transistor 54 are connected to each other, the collector of the transistor s2 and the collector of the transistor 53 are connected to each other, and the collector of the transistor 51 is connected to one terminal of the primary winding of the transformation 1! The collector is connected to the other terminal of the primary winding of transformer sfI. transistor 51 and s
The second rays and ri are connected to each other through the transistor sS and a resistor to the power supply V□, and the transistor ss and the sth ray and ri are connected to each other and are connected to the power supply iii, , through the transistor 56 and another resistor. It is connected. The OR circuit 57 and the phantom circuit 58 are the OR circuit 4 of the circuit in FIG.
Similar to 6 and 10 circuits 47, but OR circuit 570
One input terminal is connected to the pace of transistor 51, and the other input terminal of OR circuit 57 is connected to the pace of transistor 5a.

The output of the υ mountain circuit 58 is supplied to the pace of transistors s5 and 56. The first input signal (,) is the inverted signal of the first input signal) to the pace of the transistor 51.
to the pace of transistor 62, the second input signal (b)
is connected to the pace of transistor 53, the second input signal is inverted, and the good signal (W) is connected to the pace of transistor 54.

The output signal is available across the two windings of transformer 5il.

Other aspects are the same as the circuit shown in FIG.

The operation of the embodiment shown in FIG. 8 will be explained using FIG. 9. The top row (1) K in the figure shows the binary input signal to be processed in this circuit, and the blank signal is a known circuit not shown (FIG. 9 (2)).

(3), (4) and (5), which are divided into 10 input signals, an inverted signal of the first input signal, a second input signal, and an inverted signal of the second input signal. be done. The waveform shown in FIG. 9(6) is the waveform of the single peak signal, which is applied to the single peak circuit 580 input terminal. The above-mentioned black and white signals are synchronized in phase with the input signal. O
The output signal (h) of the R circuit 51 is shown in FIG. 9 (7) K, AND
The waveforms of the output signal (J) of the circuit 58 are shown in FIG. 9(8)K, respectively. The output signal (j) from K 9/5) x
By controlling ls5 and 56, the currents of transistors 51, 52, 53 and 54 ((1), (-2
), (a3) and (a4) are respectively shown in Figure 9 (9)
, (10), (11) and -(12). An output current (jO) is obtained in the secondary winding of the transformer 59, and its current waveform is shown in FIG. 13') K
shown.

From the waveform diagrams in FIGS. 9 (9), (10), (11), and (12), the period in which the current is flowing through the transistors 51 to 54 can be determined from FIG. When compared with the energization period obtained from waveforms (9) to 12), it is 41K ((2).

It can be seen that the energization period of (I4) is shorter than the energization periods of (I2) and (14).

As mentioned above, in the nine circuits shown in the Km example, when the input signal is rOJ, no current flows through any of the transistors, and the power consumption and heat generation of the transistors are less than half that of the conventional circuit.
mrk 1nversion) code, it is approximately 174. Therefore, a great effect can be expected when trying to obtain high speed, large output/4 pulses, and it is possible to use smaller transistors than in conventional circuits for the same output.

According to the present invention, collector loss of a transistor used in a differential transistor pair in a pulse output circuit can be reduced without generating an erroneous signal.

[Brief explanation of the drawing]

Figures 1, 2, and 3 are circuit diagrams of conventional/intermediate pulse output circuits, Figure 4 is a waveform diagram explaining the operation of the circuits in Figures 1 and 2, and Figure 5 is a diagram of a conventional/intermediate pulse output circuit. 3 is a waveform diagram illustrating the operation of the circuit in FIG. 6, FIG. 6 is a circuit diagram of a pulse output circuit as an embodiment of the present invention, and FIG. 7 is a waveform diagram illustrating the operation of the circuit in FIG. 6. FIG. 8 is a circuit diagram of another embodiment of the present invention,
FIG. 9 is a waveform diagram illustrating the operation of the circuit of FIG. 8. 11.12, 21.22.23-...transistor, 3
1.32.33.34...transistor, 35°36
-Logic circuit, 41, 42.48...transistor, 4
6-・08 circuit, 47... Book A circuit, 49... transformer, 51.52, 53.54, 55.56... transistor, 57... OR circuit, 58... phantom circuit, 5
9...Transformer. Figure 1 VEE Figure 2 EE (6> Figure 4 Z2 o + Place l Place 1-Figure 5 (1) 101hO11-11,0,0,0,0,0,1
1O111'' - 1 (13) 73 calls] Figure 6 Figure 7, (5) 74U- Figure 8 Figure 9 (1), 0, 1.0, 1.1.1. O, O, O,
O, 0, 1, 0, 1, 1, 0° (13) Lo g-

Claims (1)

[Claims] 1. A current switching type that drives a differential transistor pair that is turned on and off differentially by m-input sound-IK, and outputs a three-value signal by adding the current of each transistor that makes up the skeleton transistor pair. In the analogy output circuit, the scissors l
A logic circuit that calculates the AND of the input signals of the IwIh transistor pair and the armpit input signal, and a power supply circuit that is connected to each other of the differential transistor pair. The 4I output circuit is provided with a current control element inserted between the output circuit and the output circuit, which is controlled by the output of the wrinkle logic circuit. 2. Connect two pairs of differential current control elements between the wires and the power supply that are connected to each other.
11l, and a signal obtained by inverting the polarity of the tenth human input signal and the first input signal of the two input signals is input to one of the two differential transistor pairs, respectively. and the second input signal and the second input signal.
A signal obtained by inverting the polarity of the input signal of is connected to the input Kli of the other O differential transistor pair, respectively, and the output of the skeleton logic circuit is supplied to the two current control elements in parallel.
The pulse output circuit according to item 1.