JPS60251719A - Mos transistor circuit - Google Patents

Abstract

PURPOSE:To simplify the circuit constitution by constituting a circuit deciding logic with a circuit comprising both a pMOS transistor (TR) and an nMOS TR to decrease an input signal in the logical decision circuit. CONSTITUTION:The logical decision circuit L2 consists of the pMOS TR and the nMOS TR. An input affirmative signal is used as a serial gate input signal and it is turned off when the input affirmative signal is a high level and the MOS TR is turned off when the signal is at a low level. Thus, since all the MOS TRs included in the logical decision circuit L2 are operated by the input affirmative signal only, the number of input signal lines is less.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an MO constituting a logic circuit such as a
S) Is it related to transistor circuits0 [Prior art] Conventional MOS) Fungister circuits, especially CMOS dynamic decoder circuits will be explained with reference to Fig. 1〇 The ones marked p in Fig. 1 are pMO8) The transistors are n
Items marked with ``MO8'' are for use with the transistor. A,
B, C are decoder manual signals (input affirmation No. 48), A,
B and C are the inversions of the decoder manual signals AI D and C 63
(input negation signal). 0. ,0.・・・・・・
−・・−・0. indicates the decoder output signal, and φ indicates the tarok signal. NI+ N2 r...N8 is a node, +1. +2. Is is an inverter for creating an input negation signal, s,, e2t...B8 is an inverter for shaping the output waveform, Fl+F21...F8 is a transistor that outputs a filter pMO8), C,, C, ,...
...C8 are nodes N,,N,...-N, respectively
8 and ground.

In this conventional example, the number of input signals is 3 and the number of output signals is 2328.
However, the number of input signals may be n and the number of output signals may be 2n. Further, E is a power supply, and GND is a ground.

Note that the capacitor charging circuit will be referred to as a first switching circuit, and the circuit that performs logic determination will be referred to as a second switching circuit.

Next, the operation shown in FIG. 1 will be explained.

First, set the clock signal φ to LOW (hereinafter referred to as
, turns on the 9MO8) transistor connected to the clock signal φ, turns off the 1MO8) transistor also connected to the clock signal φ, and connects the node NH+ N2 r...
...N, as the power supply magnetic pressure, capacitor CI * C2
＋・・・・・・C8 is increased. During this charging period, the decoder input signals A, B, and C are connected to the river gh (hereinafter referred to as l).
Or set it to L.

Next, the transistor 9MO8 connected to the clock signal φ by setting the pj signal φ to H is turned off, and the transistor nMO's) connected to the clock signal φ and 1'+iφ is turned on. At this time, if the decoder input signals A, B, and C are, for example, H, L, and L, respectively, all the nMOS transistors connected in series between the node N2 and the ground are turned on, and the capacitor C7 is uncentered.
Node N2 is selected, the potential becomes L,
Decoder output signal 02 becomes H. At this time, transistor F2 is turned off. The unselected mate, for example, the capacitor CI connected to N1, tries to be uncentered due to leakage current, but the 2p MOS transistor F does not feed.

is on, and in order to compensate for the leakage current, the node N is not inverted to L.

In the conventional decoder circuit shown in FIG. 1, the decoder input signals A, B, and C are all inverted, and the first
In the circuit shown in the figure, the logic decision enclosed by the L10 dotted line should be made.
O8) A logic decision circuit made of transistors requires human input affirmation signals and input negation signals, that is, twice as many signal lines as the number of input signals. At the same time, to generate an input affirmation signal, 4. It has the disadvantage that it requires the same number of inverters as the number of inverters.

[Synopsis of the invention]

This invention was made in order to eliminate such drawbacks, and consists of a 9MO8) transistor and a 1M
O8) This is a MOS) transistor circuit that realizes the same logical operation as the conventional circuit by being configured with a circuit consisting of both transistors and only an input affirmation signal.

An embodiment of the present invention will be described below with reference to FIG.

[Embodiments of the invention]

The embodiment shown in FIG. 2 is a circuit that operates logically in the same way as the circuit shown in FIG. 1, and the same parts as in FIG. 1 are designated by the same reference numerals.

In Figure 2, the logic determining circuit surrounded by the dotted line of L2 is different from the circuit in Figure 1, and is composed of a pMOS transistor and 1MO8.
) consists of transistors. In addition, the inverter 11+I2+■ in FIG. 1, and the input negation 4+J No. A,
There is no equivalent to B, U:.

In the CM OS Quinaminckna coder circuit shown in FIG. 2, for example, the decoder input signal A,
If B and C are H, L, and L, respectively, the nMOS transistor using the decoder input signal A as the gate input signal is turned on, and the pMOS transistor is turned off. Further, the pMOS transistors using the decoder input signals B and C as gate input signals are turned on, and the L1nMOS transistors are turned off. As a result, when the clock signal φ is H, as in the case of the circuit shown in FIG. , the potential of node N2 becomes L, and node N2 is selected. The node that was not lost, for example, N, is 9 before the ground.
MO8) At least one transistor or nMOS transistor is off and the potential remains at H. nM
The Os transistor turns on when the gate pressure is 1, whereas the 9MO8 transistor turns on when the gate pressure is L. Conventionally, input negative No. 16 was used as the gate input signal, and the input positive signal was 9MO8 instead of the nMOS transistor that was turned off when high and turned on when low
) By using a transistor, it is possible to realize a circuit that turns the input affirmation signal into a serial gate input signal and turns off when the input affirmation signal is I (and turns on when it is L).

In the present invention, all the MOS transistors included in the logic determining circuit surrounded by the dotted line L2 in FIG. 2 are operated by only input positive signals by utilizing the above-mentioned properties of the MO8I transistor. As a result, the logic decision circuit L2 is realized with a circuit having 1/20 the number of input signals of the conventional logic decision circuit L1. Also, an inverter for creating an input negation signal is unnecessary.

Although this invention describes a CMOS dynamic decoder circuit, it is also applicable to a MOS transistor circuit that requires an input affirmation signal and an input negation signal at the same time, such as a PMOS transistor circuit.
, L, A (Programmable Logic A
Of course, it can also be used for circuits such as rrar.

Furthermore, it is clear that the grounding in the above-mentioned "Gun WE and Soldiers Novel 7" is meant.

〔Effect of the invention〕

As described above in detail, the present invention includes a first switching circuit consisting of one or more switching transistors connected to a gate terminal signal between an output terminal and a power supply; (Place one or more boards between the first switching circuit and the ground, and connect one or more switching transistors in parallel with the Ichikawa capacitor, In a multi-input, multi-output MOS transistor circuit having a second switching circuit connected to each gate terminal and an input signal and a clock signal, the second switching circuit is connected to each capacitor with a different number of values of conduction type.
By connecting the S switching transistors in the upper row, it is possible to reduce the input signal strength in the r1tj buried redundant circuit, thereby making the circuit structure simpler.

[Brief explanation of drawings]

Figure 1 shows a CMO consisting of a conventional MOS (MOS) transistor circuit.
FIG. 2 is a diagram showing a CMOS power converter circuit, which is a central example of the present invention. In FIG. 2, p is a pH/108) transistor, and n is nM. S transistors, A, B, C are decoder input signals, φ is a clock signal, L2 is a successor determination circuit, 01 to 06 are Tecoder output signals, N1 to N8 are mates, 81 to B8 are inverters, F, -F, G'l-Fitnokkutsuk pMOS
Transistor, C+-Ca is capacitor, E is power supply, G
ND is ground. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 0, 02--1-----08I ND Figure 2 GND Procedural amendment (voluntary) 60123 Showa year/month [1 3, amendment Representative Hitoshi Katayama Department 4, Agent 5 Claims column 9 of supplementary description 4+1 detailed explanation of the invention and brief explanation of drawings 6 Contents of amendment (1) Specification! 1-. Supplement the persimmon and encirclement of the fraudulent claim as shown in the attached sheet. (2) Similarly, "capacitor" on page 3, line 17, page 4, line 8, and lines 12 to 13 are corrected as "parasitic capacitor." (3) Similarly, on page 8, lines 10 to 12, [provide one or more capacitors, and correct J in parallel with the capacitor described in Fist as "column 1 with the generated parasitic capacitor." . (4) Similarly, on page 8, line 15, “Multiple inputs, multiple outputs” should be changed to “
"Multi-input" is corrected. (5) Similarly, delete "for each capacitor phrase" on page 8, lines 16-17. (13) Similarly, "capacitor" on page 9, lines 11-12 is corrected to "parasitic capacitor." 1-2, the patent claim ζ1ij (circle (1) each output terminal r- and ijj of the compound shell: there is a game I between the whale and
A first switching circuit consisting of one or more switching I/Run transistors connected to the clock 1-1 is connected to the first switching circuit 1-1 and grounded. The 1111 is also composed of one or more switching transistors and connects each gate terminal to the input low signal and the 0 clock signal.
<'jeL>In the large MO3I-Runsistor circuit formed by connecting a second switching circuit, the second Swiss-Nunc circuit 1.1. A MO3I transistor circuit is created by connecting a plurality of MOS switch transistors of 1 to 11 times. In the second switching circuit consisting of link transistors,
Clean output and equalize human power! Princess MOS
Switzinck I. Lancista's Case 1. The upper pole is the common person Chi 1, the bow is 4'; A MOS transistor circuit according to claim No. (l l )''1.

Claims (1)

[Scope of Claims] (11) A first switching circuit consisting of one or more switching transistors each having a gate terminal connected to a clock signal is connected between each of the plurality of output terminals and the 1L source; One or more capacitors are provided between each switching circuit of No. 1 and ground, and one or more switching transistors are arranged in parallel with each of the capacitors, and each gate terminal is connected to an input signal and a clock signal. In the multi-input, multi-output MO8) transistor circuit formed by connecting a second switching circuit, the second switching circuit is configured by connecting in series a plurality of MOS switching transistors having different conductivity types for each capacitor. A MOS) transistor circuit characterized by: (2) In a second switching circuit comprising a plurality of MOS switching transistors of different conductivity types, the gate electrodes of the MOS switching transistors having different outputs and the same input are connected to a common input signal. MOS according to claim (1)
Tofunjistar circuit.