JPS6025030B2 - Drive method of semiconductor memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in the driving method of a semiconductor memory device having a nonvolatile memory in which information is written and output electrically.

Most of the semiconductor memory bags that have been widely used in the past are of the volatile type, and the stored information disappears when the power is turned off.

Therefore, non-volatile devices exclusively used for sending out messages have been provided as devices to deal with such drawbacks, but many of these devices are not rewritable, and there are very few types of rewritable devices. And what can be rewritten is
Although writing can be done electrically, erasing, which is a prerequisite for rewriting, must rely on ultraviolet irradiation, which is inconvenient in handling. In addition, devices that can be electrically written and erased have the disadvantage of poor retention of stored information, and in addition, such devices and those that can be erased by ultraviolet light,
They require voltages that are much higher than those of the power supplies typically used in integrated circuit devices. FIG. 1 is a cross-sectional side view of a conventional ultraviolet erasable nonvolatile semiconductor memory device.

In the figure, 1 is a p-type silicon semiconductor substrate, 2 is a field oxide film, 3 is an n+ type source region, 4 is an n+ type drain region, 5 is a gate oxide film, 6 is a polycrystalline silicon floating gate, 7 is a polycrystalline silicon control gate, 8 is a phosphosilicate glass film, 9 is a source electrode, and 10 is a drain electrode.

In this device, in order to write information, charges in the channel region are injected into the floating gate 6 to change the function voltage Vth of the transistor.

At this time, in order to facilitate charge injection into the floating gate 6, the substrate 1 and the control gate 7 are
A voltage is applied between the two to form an accelerating electric field. In order to increase the speed of writing information and to enable writing at a low voltage, it is necessary to reduce the thickness of the gate oxide film 5. However, if it is made too thin, the electric field applied to the gate oxide film 5 at the time of deposition will cause charge injection, even if only slightly, and the characteristics will become unstable. Usually, in the conventional example,
About 125 [V] for information writing, about 15 [V] for reading
] is applied to the control gate to detect changes in the function voltage y.

Note that in the structure of the conventional example, the floating gate 7
When electrons are injected into and accumulated, the threshold voltage Vth increases. Further, in order to erase written information, ultraviolet rays are irradiated to emit electrons. According to the present invention, information can be written and erased electrically, and all writing, reading, and erasing can be performed with a single low-voltage power source, for example, a single 85 [V] power source. Further, it is possible to hold written information in a non-volatile manner, and this will be explained in detail below.

FIG. 2 is a sectional side view of a main part of an example of a semiconductor memory device used in carrying out the present invention, and FIG. 3 is a plan view of the main part.

Note that although FIG. 2 is a cut along the line x-Y in FIG. 3, when comparing FIG. 2 and FIG. 3, there are omissions in FIG. In each figure, 11 is a p-type silicon semiconductor substrate, 12 is a field oxide film, and 13 is an n1
14 is an n+ type drain region, 15 is a gate oxide film, 16 is a silicon floating gate,
17, a silicon first control gate, 172 a silicon second control gate, and 18 a phosphoric acid glass film, respectively.

Note that the gates 16, 17, and 172 are of course made of polycrystalline silicon. Further, in particular, the gates 17, 172 may be made of metal. In the device having the above configuration, a capacitance C is provided between the substrate 11 and the gate oxide film 15, a capacitance C2 is provided between the floating gate 16 and the first control gate 17, and a capacitance C2 is provided between the floating gate 16 and the first control gate 17. A capacitor C3 is formed between the two control gates 172 and the second control gate 172.

These capacitors C, ~C3 form a connection relationship as shown in Figure 4 (during writing) and Figure 5 (during reading), and charge is injected and accumulated, and the required amount as a storage device is achieved. It is designed to take action.

In FIGS. 4 and 5, Vo is the potential of the floating gate 16 when the substrate 11 is grounded;
Vr represents a read voltage, and VW represents a write voltage. Now, when writing and erasing information, it is necessary to increase the electric field applied to the gate oxide film 15.

Since this electric field is proportional to the potential Vo, it is sufficient to evaluate the potential Vo in order to analyze the operation. V.

= Kisho 2 Chapter 3 Kiki ------ (11 Now,
Since Vr=Vw, V.

=C≦2 words Chapter 2 is also 3Vr...[2'. Also, ``When extracting memory information, in formula {1}, Vw=
Since C2Vr.
．． ．． ...{3'V.

=C, 10C20C3.

FIG. 6 shows the dependence of the potential Vo on the capacitor C3.

In the figure, the value of Vo/VW when the capacitance C3 is zero is
In the device having the normal structure shown in FIG. 1, this corresponds to the magnitude of the potential Vo when the output voltage Vr is applied. The greatest feature of the present invention is that C3>0, and in the case of the value of capacitance C3 as shown in FIG. 6, even though a constant setting voltage Vr is used, The Vo/Vr at the time of issuing a meeting is small, and the Vo/Vr at the time of writing or erasing information can be increased several times or more. That is, by switching the connection of the second control gate between writing or erasing and reading, it is possible to perform these operations using a single power supply and at a low voltage. In the embodiment described above, the injection of charge for writing or erasing information causes a breakdown in the junction in the substrate 11, and the resulting hot carriers are injected or a tunnel current is generated. It is optional to perform injection depending on the situation, but in any case,
Information can be written and erased at high speed with low voltage, and stored information can be retained semi-permanently.

Of course, the structure is not limited to that shown in FIGS. 2 and 3. For example, in FIG. 2, it is possible to extend the floating gate 16 to the left side of the figure and, therefore, to make the second control gate 172 also exist on the left side.In short, the capacitance C,... It is sufficient if the capacitors corresponding to C2 and C3 can be connected as shown in FIGS. 4 and 5. As can be seen from the above description, according to the present invention, in a non-volatile memory IJ' consisting of an MIS field effect transistor having a floating gate and a control gate, the floating gate is not only located on the channel region but also The first and second control gates extend over the field insulating film, and the first and second control gates are opposed to the floating gate, so when writing information, the first and second control gates are A predetermined voltage for writing is applied to the gate, and depending on the polarity, a positive or negative charge is injected into the floating gate from the semiconductor substrate side to store it. When erasing the stored information, a negative or positive charge is similarly applied. This can be done by injecting into the floating gate to change its charging state, and when writing information, the same voltage as the predetermined voltage for writing is applied to either the first or second control gate. A voltage, which is a voltage, is applied to the semiconductor substrate, and the other voltage is applied to the semiconductor substrate. - The threshold voltage Vth can be detected at this point.

In this manner, the present invention allows electrical writing, programming, and erasing to be performed at high speed, low voltage, and with a single power supply, and the stored information remains non-volatile. Furthermore, manufacturing the device used in the present invention requires no additional steps compared to manufacturing the conventional device, and only changes the patterns of the floating gate, control gate, and patterning mask. .

[Brief explanation of the drawing]

Fig. 1 is a side sectional view of the main part of the subordinate sluice device, Fig. 2 is a side sectional view of the main part showing an example of the device used to carry out the present invention, Fig. 3 is a plan view of the main part, and Fig. 4 is a side sectional view of the main part. 5 is an explanatory diagram showing the connection relationship of the capacitors generated in the device, and FIG. 6 is a diagram showing the dependence of the capacitor C3 on the potential Vo. In the figure, 11 is a substrate, 12 is an oxide film, 13 is a source region, 14 is a drain region, 15 is a gate oxide film, and 16 is a
is a floating gate, 17, 172 are first and second control gates, and 18 is a borosilicate glass frame. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6

Claims (1)

[Claims] 1 A field insulating film selectively formed on a semiconductor substrate of one conductivity type, a source and drain region of the opposite conductivity type formed on the substrate surface exposed between the field insulating films, the source and a floating gate extending from a gate insulating film on a channel region between drain regions to the field insulating film;
In a semiconductor device comprising first and second control gates facing each other with an insulating film on the gate, when writing information, a predetermined voltage for writing is applied to the first and second control gates. is applied, and when reading information, a read voltage that is the same voltage as the predetermined voltage for writing is applied to one of the first and second control gates, and the other is at the same potential as the semiconductor substrate. A driving method for a semiconductor memory device, characterized in that: