JPS60249450A - クロツク位相誤差検出器 - Google Patents

クロツク位相誤差検出器

Info

Publication number
JPS60249450A
JPS60249450A JP59105748A JP10574884A JPS60249450A JP S60249450 A JPS60249450 A JP S60249450A JP 59105748 A JP59105748 A JP 59105748A JP 10574884 A JP10574884 A JP 10574884A JP S60249450 A JPS60249450 A JP S60249450A
Authority
JP
Japan
Prior art keywords
signal
clock
clock phase
value
detector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59105748A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0535616B2 (enExample
Inventor
Junji Namiki
並木　淳治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59105748A priority Critical patent/JPS60249450A/ja
Publication of JPS60249450A publication Critical patent/JPS60249450A/ja
Publication of JPH0535616B2 publication Critical patent/JPH0535616B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP59105748A 1984-05-25 1984-05-25 クロツク位相誤差検出器 Granted JPS60249450A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59105748A JPS60249450A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59105748A JPS60249450A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Publications (2)

Publication Number Publication Date
JPS60249450A true JPS60249450A (ja) 1985-12-10
JPH0535616B2 JPH0535616B2 (enExample) 1993-05-27

Family

ID=14415870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59105748A Granted JPS60249450A (ja) 1984-05-25 1984-05-25 クロツク位相誤差検出器

Country Status (1)

Country Link
JP (1) JPS60249450A (enExample)

Also Published As

Publication number Publication date
JPH0535616B2 (enExample) 1993-05-27

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