JPS60248048A - Ring type information transmission equipment - Google Patents

Ring type information transmission equipment

Info

Publication number
JPS60248048A
JPS60248048A JP10372484A JP10372484A JPS60248048A JP S60248048 A JPS60248048 A JP S60248048A JP 10372484 A JP10372484 A JP 10372484A JP 10372484 A JP10372484 A JP 10372484A JP S60248048 A JPS60248048 A JP S60248048A
Authority
JP
Japan
Prior art keywords
speed
transmission
low
signal
unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10372484A
Other languages
Japanese (ja)
Inventor
Takashi Yamashiro
山城　貴志
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP10372484A priority Critical patent/JPS60248048A/en
Publication of JPS60248048A publication Critical patent/JPS60248048A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00—Data switching networks
    • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/46—Interconnection of networks
    • H04L12/4637—Interconnected ring systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Small-Scale Networks (AREA)

Abstract

PURPOSE:To obtain a ring type information transmission equipment in which no speed matching memory is required by adopting the multiplex speed of a high speed transmission frame as a natural number multiple of a multiplex speed of a low speed transmission frame and applying phase locking to heads of mutual frames. CONSTITUTION:A signal of a high speed transmission frame from a high speed signal transmission line 2 is inputted to a high speed signal multiplex unit 20. The unit 20 applies S/P conversion or P/S conversion to a high speed signal and transmit the result to a high speed bus 4 and stores it in an information exchange memory 40. A synchronizing unit 60 generates a low speed transmission frame in synchronizing with a head frame of a multiplex speed of a 1/n (n is a natural number) of the multiplex speed of the high speed transmission frame by using a clock synchronizing with the timing signal extracted from the high speed transmission frame by the unit 20 and inputs the frame to a low speed signal multiplex unit 30. A memory 40 takes phase synchronization with the bus 4, the data is transferred to the low speed bus 5 where the multiplex speed is 1/2 and inputs the result to the unit 30. The unit 30 applies P/S conversion or S/P conversion to the low speed signal from the bus 5 and transmits the result to the low speed signal transmission line 3.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は伝送速度の異なる２つの伝送フレーム間で相
互に情報を交換するリング形情報伝送装置に関するもの
である。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a ring-type information transmission device that mutually exchanges information between two transmission frames having different transmission speeds.

〔従来技術〕[Prior art]

従来この種のリング形情報伝送用伝送路として、第１図
に示すものがあった。図において、１は下記伝送ユニッ
ト等を収容する筐体であり、２は高速信号伝送用伝送路
、３は低速信号伝送用伝送路、４は高速バス、５は端末
との信号のやりとシを行なうための低速バスである。ま
た２０はシリアルの高速信号をパラレルにまたパラレル
の高速信号をシリアルに変換する高速信号多重ユニット
であシ、そのうちパラレルに変換された信号を扱うもの
が上記高速バス４である。更に３０はシリアルの低速信
号をパラレルに変換し、パラレルの信号をシリアルに変
換する低速信号多重ユニットであり、５０は上記低速バ
ス５の信号と、上記低速信号多重ユニツ）３Ｇとの間で
速度の整合を取るメモリ、また６０は低速伝送フレーム
を生成フレームを生成する同期ユニットである。2. Description of the Related Art Conventionally, there has been a ring type transmission line for transmitting information of this type as shown in FIG. In the figure, 1 is a housing that accommodates the following transmission units, 2 is a transmission path for high-speed signal transmission, 3 is a transmission path for low-speed signal transmission, 4 is a high-speed bus, and 5 is a system for exchanging signals with terminals. This is a low-speed bus for carrying out. Further, 20 is a high-speed signal multiplexing unit that converts a serial high-speed signal into parallel and a parallel high-speed signal into serial, and among these, the high-speed bus 4 handles the signal converted into parallel. Furthermore, 30 is a low-speed signal multiplexing unit that converts a serial low-speed signal into parallel and converts a parallel signal into serial, and 50 is a low-speed signal multiplexing unit that converts a serial low-speed signal into parallel and converts a parallel signal into serial. 60 is a synchronization unit that generates low-speed transmission frames.

次に動作について説明する。高速信号伝送用伝送路２上
を情報は第２図に示した高速伝送７レームにスロット単
位で多重されて伝送されておシ、高速信号多重ユニット
４では第２図に見られる高速伝送フレーム上の第１スロ
ツト１＆の情報を高速バス４上の２８に、また２ａの情
報はメモリ４０の３８に格納される。３ａの情報は高速
バスと位相同期がとれた多重速度が自然数倍の低速バス
５上の４８に出力され、４ａの情報は速度整合メモリ５
０上の５ａに格納される。この５ａの情報は高速伝送フ
レームを生成するクロックとは全く独立なりロックで生
成され、フレーム先頭同志で位相同期のとれていない低
速伝送フレーム上の第１スロツ）６８に多重される。こ
の様に高速伝送フレーム上の第１スロツ）１ａの情報が
低速伝送フレーム上の第１スロツ）６ｍに移される。同
様にして１ｂ、１ｃの情報も６ｂ、（ｉｅに移される。Next, the operation will be explained. Information is transmitted on the transmission path 2 for high-speed signal transmission by being multiplexed in slot units into the 7 high-speed transmission frames shown in FIG. The information on the first slot 1& of the slot 2a is stored in 28 on the high-speed bus 4, and the information on slot 2a is stored in 38 of the memory 40. The information 3a is output to 48 on the low-speed bus 5 whose multiple speed is a natural number times the speed synchronized with the high-speed bus, and the information 4a is output to the speed matching memory 5.
It is stored in 5a above 0. This information 5a is generated in a locked manner, completely independent of the clock that generates the high-speed transmission frame, and is multiplexed into the first slot 68 on the low-speed transmission frame, which is not phase-synchronized at the beginning of the frame. In this way, the information in the first slot 1a on the high-speed transmission frame is transferred to the first slot 6m on the low-speed transmission frame. Similarly, the information of 1b and 1c is also transferred to 6b and (ie).

また低速伝送フレーム上の情報も上記の逆ルートをたど
り同様に高速伝送フレームに移す事ができる。Information on the low-speed transmission frame can also be transferred to the high-speed transmission frame in the same way by following the above-mentioned reverse route.

従来のリング形情報伝送装置は以上のように構成されて
いるので、２つの伝送フレームの伝送速度が互いに独立
しており高速伝送フレームへの多重速度と低速伝送フレ
ームへの多重速度も異々つでいたために、高速伝送フレ
ーム上の情報と低速伝送フレーム上の情報を交換する速
度整合用のメモリが必要であるという欠点があった。Since the conventional ring type information transmission device is configured as described above, the transmission speeds of the two transmission frames are independent of each other, and the multiplexing speed for high-speed transmission frames and the multiplexing speed for low-speed transmission frames are also different. Therefore, there was a drawback in that a memory for speed matching was required to exchange information on high-speed transmission frames and information on low-speed transmission frames.

〔発明の概要〕[Summary of the invention]

この発明は、上記の様な従来のものの欠点を除去するた
めＫなされたもので、高速伝送フレームの多重速度を低
速伝送フレームの多重速度の自然数倍にし、かつ相互の
フレームの先頭同志で位相同期をとる事により、速度整
合メモリを不要としたリング形情報伝送装置を提供する
事を目的としている。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it increases the multiplexing rate of high-speed transmission frames to a natural number multiple of the multiplexing rate of low-speed transmission frames, and also sets the top of each frame to The purpose of this invention is to provide a ring-type information transmission device that eliminates the need for speed matching memory by achieving synchronization.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例を第３図に基づいて説明する
。第３図において１は上記ユニット等を収容する筐体、
２は高速信号伝送用伝送路、３は低速信号伝送用伝送路
、４は高速バス、５は端末との信号のやりとりを行なう
ための低速バスである。更に、２０はシリアルの高速信
号をパラレルにパラレルの信号をシリアルに変換する高
速信号多重ユニットでアシ、このうちパラレルに変換さ
れた信号を扱うのが上記高速バス４である。また、３０
はシリアルの低速信号をパラレルに変換し、またパラレ
ルの信号をシリアルに変換する低速信号多重ユニットで
あり、４Ｇは高速バス４と低速バス５の情報の交換を行
なうメモリである。An embodiment of the present invention will be described below with reference to FIG. In FIG. 3, 1 is a casing that houses the above unit, etc.;
2 is a transmission line for high-speed signal transmission, 3 is a transmission line for low-speed signal transmission, 4 is a high-speed bus, and 5 is a low-speed bus for exchanging signals with a terminal. Furthermore, 20 is a high-speed signal multiplexing unit that converts serial high-speed signals into parallel signals and converts parallel signals into serial signals. Of these, the high-speed bus 4 handles the signals converted into parallel signals. Also, 30
4G is a low-speed signal multiplexing unit that converts serial low-speed signals into parallel signals and converts parallel signals into serial signals, and 4G is a memory that exchanges information between the high-speed bus 4 and the low-speed bus 5.

同期ユニット６０は高速信号多重ユ、ニット２０が高速
伝送フレームから抽出したタイミング信号と同期のとれ
たクロックにより、高速伝送フレームの多重速度の’／
ｎ　（ｎは自然数）の多重速度を持つ低速伝送フレーム
を生成する同期ユニットである。The synchronization unit 60 is a high-speed signal multiplexing unit, which uses a clock synchronized with the timing signal extracted from the high-speed transmission frame by the unit 20 to adjust the multiplexing speed of the high-speed transmission frame.
It is a synchronization unit that generates low-speed transmission frames with multiple speeds of n (n is a natural number).

次に１高速伝送フレームの多重速度が低速伝送フレーム
の多重速度の１／２の場合について動作の説明を行なう
。Next, the operation will be explained in the case where the multiplexing rate of one high-speed transmission frame is 1/2 of the multiplexing rate of one low-speed transmission frame.

高速信号伝送用伝送路２上を情報は第４図に示した高速
伝送フレームにスロット単位で多重されており、高速信
号多重ユニット４では高速伝送フレーム上の第１スロツ
）１ａの情報を高速ハス４上の２ａｌＣ，この２ａの情
報はメモリ４０の３１に格納される。３ａの情報は高速
バス４と位相同期がとれ、多重速度が１７２の低速バス
５上の４１に出力される。高速伝送フレームの先頭を示
す高速フレームタイミングに低速伝送フレームの先頭を
示す低速フレームタイミングの位相を従属同期させ、高
速スロットタイミング１を２分周した高速スロットタイ
ミングに低速スロットタイミングをＰＬＬによシ従属同
期させる事により、低速バス５上の情報４ａは低速伝送
フレームの第１スロツ）６ａＫ多重可能となる。同様に
して１ｂ、１ｅの情報も６ｂ、６ｅＫ移される。また低
速の伝送フレーム上の情報も上記のルートの逆を辿り、
同様に高速伝送フレームに多重する事ができる。Information on the transmission line 2 for high-speed signal transmission is multiplexed in slot units into the high-speed transmission frame shown in FIG. 2alC on 4, the information of this 2a is stored in 31 of the memory 40. The information on 3a is phase synchronized with the high speed bus 4 and is output to 41 on the low speed bus 5 with a multiple speed of 172. The phase of the low-speed frame timing indicating the beginning of the low-speed transmission frame is subordinately synchronized to the high-speed frame timing indicating the beginning of the high-speed transmission frame, and the low-speed slot timing is subordinated to the high-speed slot timing obtained by dividing the frequency of high-speed slot timing 1 by 2 using the PLL. By synchronizing, the information 4a on the low-speed bus 5 can be multiplexed in the first slot 6aK of the low-speed transmission frame. Similarly, the information of 1b and 1e is also transferred to 6b and 6eK. Information on low-speed transmission frames also follows the reverse of the above route,
Similarly, it can be multiplexed into high-speed transmission frames.

なお、上記実施例では多重′速度の異なる２つのリング
伝速路間での情報の交換について示したが、情報がサイ
クリングに出力されるバス等においても、同様の方式を
とる事ができる。In the above embodiment, information is exchanged between two ring transmission lines having different speeds, but a similar method can be used in a bus or the like where information is output for cycling.

〔発明の効果〕〔Effect of the invention〕

以上の様にこの発明によれば、低速の伝送フレームを高
速の伝送フレームに位相同期させ、多重速度を高速は低
速の自然数の倍率にする事により、速度整合用のメモリ
が不要となり、安価で等時性の高い非常に優れたリング
形情報伝送装置が得られる効果がある。As described above, according to the present invention, a low-speed transmission frame is phase-synchronized with a high-speed transmission frame, and the multiplex speed is set to a natural number multiplier of the high speed and low speed, thereby eliminating the need for speed matching memory and reducing the cost. This has the effect of providing an excellent ring-type information transmission device with high isochronism.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のリング形情報伝送装置の構成を示すブロ
ック図、第２図は第１図の各部の信号の流れを示す動作
図、第３図はこの発明の一実施例によるリング形情報伝
送装置を示すブロック図、第４図は第３図の各部の信号
の流れを示す動作図である。 １・・・筐体、２・・・高速信号伝送用伝送路、３・・
・低速信号伝送用伝送路、４・・・高速バス、５・・・
低速バス、２０・・・高速信号多重ユニット、３０・・
・低速信号多重ユニット、４０・・・メモリ、５０・・
・速度整合用メモリ、６０・・・同期ユニット。 尚、各図中同一符号は同−又は相当部分を示す。 第１図 第３図FIG. 1 is a block diagram showing the configuration of a conventional ring-type information transmission device, FIG. 2 is an operation diagram showing the signal flow of each part in FIG. 1, and FIG. 3 is a ring-type information transmission device according to an embodiment of the present invention. FIG. 4 is a block diagram showing the transmission device. FIG. 4 is an operation diagram showing the flow of signals in each part of FIG. 1... Housing, 2... Transmission path for high-speed signal transmission, 3...
・Transmission line for low-speed signal transmission, 4...high-speed bus, 5...
Low-speed bus, 20...High-speed signal multiplexing unit, 30...
・Low-speed signal multiplexing unit, 40...Memory, 50...
- Speed matching memory, 60... synchronization unit. Note that the same reference numerals in each figure indicate the same or corresponding parts. Figure 1 Figure 3

Claims (1)

【特許請求の範囲】[Claims] 伝送速度の異なる複数の伝送フレームが扱われる複数の
信号伝送用伝送路でシリアル−パラレルまたはパラレル
−シリアル変換を行なう複数の信号多重ユニットと、上
記複数の伝送フレームの中で高速伝送フレーム上の情報
と低速伝送フレーム上の情報を変換及び上記複数の信号
多重ユニット間の速度の整合を取る複数のメモリとを有
するリング形情報伝送装置において、上記高速伝送フレ
ームへの多重速度を低速伝送フレームの多重速度の自然
数の倍率とし、相互のフレームの先頭同志で位相を同期
させたことを特徴とするリング形情報伝送装置。A plurality of signal multiplexing units that perform serial-to-parallel or parallel-to-serial conversion on a plurality of signal transmission transmission lines that handle a plurality of transmission frames with different transmission speeds, and information on a high-speed transmission frame among the plurality of transmission frames. and a plurality of memories that convert information on the low-speed transmission frame and match speeds between the plurality of signal multiplexing units, the multiplexing speed of the low-speed transmission frame to the high-speed transmission frame is multiplexed. A ring type information transmission device characterized in that the speed is multiplied by a natural number and the phases are synchronized at the beginning of each frame.
JP10372484A 1984-05-24 1984-05-24 Ring type information transmission equipment Pending JPS60248048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10372484A JPS60248048A (en) 1984-05-24 1984-05-24 Ring type information transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10372484A JPS60248048A (en) 1984-05-24 1984-05-24 Ring type information transmission equipment

Publications (1)

Publication Number Publication Date
JPS60248048A true JPS60248048A (en) 1985-12-07

Family

ID=14361616

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10372484A Pending JPS60248048A (en) 1984-05-24 1984-05-24 Ring type information transmission equipment

Country Status (1)

Country Link
JP (1) JPS60248048A (en)

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