JPS60246668A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To improve the efficiency of an MOS integrated circuit, and to reduce ship size by forming an input/output protective circuit in a region just under an external connecting-lead leading-out buffer for the MOS integrated circuit. CONSTITUTION:An input protective circuit 9 is constituted by a pad 1 and diodes 3, 4. The diode 3 as an N<+>-P<-> junction section and the diode 4 as a P<+>-N<-> junction section are shaped just under the pad 1, and one ends of the diodes 3, 4 are connected to the pad 1 through an aluminum electrode and wirings (b). A spatial region just junder the pad can be used as a practical region, and the efficiency of the circuit can be improved and chip size reduced, thus obtaining circuit consitution generating no waste.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field of Qtl] The present invention relates to a semiconductor integrated circuit equipped with an input/output protection circuit.

[Prior art]

A conventional semiconductor integrated circuit will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of input buffer 7 of a conventional general CMO8 configuration, where S is an input protection circuit, which is composed of a pad 1°, a resistor 2 made of polysilicon, and a diode 3°4. 5.7'i'iP channel MO8) Lanozista,
6.8 is an N-channel MOS transistor, 12 is a power supply terminal, and 13 is a ground terminal.

FIG. 2 schematically shows the pattern of the input protection circuit 90 part in FIG.
O8) Run raster 5. An inverter consisting of an N-channel MOS transistor 6, an impark consisting of a P-channel MOS transistor 7, an N channel transistor 8), and the like are omitted. Figure 3 is an enlarged cross-sectional view of Figure 2, taken from ■-■. In Figure 3, a is a crow coat, b is an aluminum electrode, and C is an insulating oxide film. Pad 1 is connected to one end of diode 3, which is an N''P-junction, and one end of diode 4, which is one junction to P+, through two crosslinkers.

Generally, in the case of MO3 integrated circuits, damage wk (including electrostatic damage) is likely to occur due to surge voltage during operation and handling. The main cause of this breakdown is dielectric breakdown between the gate and source. In the past, the human power output section (main human power section) 9 of the MO8 assembly d was equipped with a human power protection circuit 9 to prevent destruction. This human power protection circuit 9 is composed of a resistor 2 and diodes 3 and 4, and the input power protection circuit 9 is built into the outside of the pad 1 as part of the input/output circuit. Note that the output protection circuit is also formed in the same manner.

In this way, by inserting it as part of the human power protection circuit 9, the output protection circuit (not shown), or the input/output circuit, the surface shape becomes thicker (and the circuit itself becomes more complicated). .

[Summary of the invention]

In order to solve the above-mentioned drawbacks, this invention has been made to improve the efficiency of the circuit and reduce the chip size by installing an inlet/output power protection circuit in the trap area directly under the pad, which has not been done before. be.

An example of this invention will be explained below with reference to the drawings.

[Embodiments of the invention]

FIG. 4 is a schematic diagram of one embodiment of the present invention, in which the long sword protection circuit 9 is replaced directly below the pad.

FIG. 5 is a sectional view taken along the m-thin line in FIG.
, the resistor 2 shown in Fig. 3 is not mentioned.

! In Fig. 5, a, b+c are the same as in Fig. 3, and instead of providing a resistor as shown in Fig. 3, tie-out 3, which is an N''P- junction, and P4N- are placed directly under pad 1. Four diodes, which are junctions, are provided, and one end of each diode 3, 4 is connected to the pad 1 through a full mini-RAM 4-pole.

Further, FIG. 6 shows another embodiment of the present invention, and is a circuit diagram showing an output rough 710 which is an output side boosting circuit, and FIG. 7 is a sectional view of FIG. 6. . In Figure 6, the diode 30.40 and each MO8) Rungis 250.6
A resistor 20 made of a diffused resistance is inserted between 0 and 0.

In FIG. 7, a, b, and c immediately below the pad 1 are the same as in FIG. 3. Directly below the pad 1 are a diode 30, which is an N+P- junction with 20 resistors made of diffused resistance, and a diode 4, which is a P+N- junction.
0, and these diodes 40 and a resistor 20 made of a diffused resistor. The diode 30 is connected to the pad 1 through an aluminum wire.

Further, FIG. 8 shows still another embodiment of the present invention, in which a pad 1 and diodes 3 (3G) and 4 for a human blade are shown.
(40) is a front view of the input/output band section 11 when a polysilicon resistor 20' is inserted between the sections (40).

In the CMOS inverter circuit of the present invention, in addition to the pad 1, an input protection circuit 9, which has been conventionally incorporated as a part of the input/output circuit, and an output cover sofa 10, which is a protection circuit.
Furthermore, since the button is replaced in the space area under the pad 11IL, the four paths become more efficient and the chip size is significantly reduced. In addition, the surface of the diode itself as a protective diode is larger than that of the conventional one, and the withstand voltage is higher than that of the conventional one, so there is no need to insert a protective resistor such as the resistor 2 installed in the +1II stage ( Become.

As shown in FIG. 5, two relatively small contacts are provided outside the pad 1 so that the pad 1 does not come into contact with the diode 3.4.

In addition, this invention has been explained by taking as an example the fact that by placing the output protection circuit directly under the pad in the MO8 collection, the input/output protection circuit is Needless to say, the present invention is applicable not only to other semiconductor circuits but also to other semiconductor circuits that can utilize the space area directly under the pad.

〔Effect of the invention〕

As explained in detail above, this method has not been used in the past because it increases the number of external connection leads of the MO8 integrated circuit and forms an input/output voltage insulating circuit consisting of a diode or a diode and a resistor in the lower layer area of the pad. The pad can be used as a storage area for the lower space area, which can improve circuit efficiency and reduce chip size, and has the effect of achieving a lean circuit configuration.

[Brief explanation of drawings]

Figure 1 Mini conventional cMos Nobunari human power circuit diagram,
Figure 2 is a diagram showing the pattern of the protection circuit part in Figure 1, #
Figure g3 is an enlarged view of the defense by It-ft mK in Figure 2,
FIG. 4 is a diagram showing a pattern of an embodiment of the present invention, and FIG.
The figures are an enlarged view of the 1θI plane taken at 1-1 m in Fig. 3, Fig. 6 is an input huff 7 circuit diagram according to the present invention, Fig. 7 is an enlarged cross-sectional view of the narrow part of Fig. 6, and Fig. 8 is an enlarged view of this light beam. Other fruit between 211
It is a figure showing the pattern of example i1. In the figure, 1 is a pad, 2 is a resistor, 3 and 4 are diodes,
5 and 7 are P-channel A10S transistors, 6 and 8 are N-channel MO3) transistors, 9 is an input protection circuit,
10 is an output hack 7. 11 is an input/output pad section, 12 is a power supply terminal, and 13 is a ground terminal. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others) Figure 1 Figure 4 Old Figure 3 Figure 6 L j Figure 7 Figure 8 Figure 11 Hands, supplementary old (1,1 shot) 1. Indication of the incident 14 Application No. 59-104934 2, Name of the invention 'l'j' Number 3 shi) name
(601) Mitsubishi Electric Co., Ltd. Representative Hitoshi Katayama 4 Agent 5, XT details, i9 light column and drawing 6 of the invention in the subject specification of Yushi,
Contents of amendment (1) In line 2010 of the specification, "b stands for aluminum electrode J, [b stands for aluminum electrode and wiring"]. (2) Similarly, the "output protection circuit that does not discharge water" in section 1 of page 3, sections 5-6, was changed to "output protection circuit (10 in Figure 6)".
l: Yes. (3) Similarly, on page 3, line 17, the word ``r bat-like do'' is supplemented with ``directly below putt 1''. (4) Similarly, on page 4, line 13, next to ``...is inserted.'', r70.80 is a MOS transistor. ” to join. (5) Similarly, "aluminum electrode b" in lines 5 and 20 of page 4 are supplemented with "aluminum electrode and wiring b," respectively. (6) Correct the figures 3 and 7 as shown in the attached sheet. Above Figure 3 Figure 7

Claims (1)

[Claims] A semiconductor Vat circuit characterized in that an input/output protection circuit consisting of a diode or a diode and a resistor is formed in the lower region of the external connection lead extraction pad of the MO3 integrated circuit.