JPS5944872A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5944872A JPS5944872A JP57155501A JP15550182A JPS5944872A JP S5944872 A JPS5944872 A JP S5944872A JP 57155501 A JP57155501 A JP 57155501A JP 15550182 A JP15550182 A JP 15550182A JP S5944872 A JPS5944872 A JP S5944872A
- Authority
- JP
- Japan
- Prior art keywords
- drain
- diode
- fet
- protection
- mos
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000002457 bidirectional effect Effects 0.000 claims description 5
- 230000005669 field effect Effects 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 3
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- NFLLKCVHYJRNRH-UHFFFAOYSA-N 8-chloro-1,3-dimethyl-7H-purine-2,6-dione 2-(diphenylmethyl)oxy-N,N-dimethylethanamine Chemical compound O=C1N(C)C(=O)N(C)C2=C1NC(Cl)=N2.C=1C=CC=CC=1C(OCCN(C)C)C1=CC=CC=C1 NFLLKCVHYJRNRH-UHFFFAOYSA-N 0.000 description 1
- 101100366935 Caenorhabditis elegans sto-2 gene Proteins 0.000 description 1
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 241000270666 Testudines Species 0.000 description 1
- 239000011324 bead Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
- H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
- H01L27/0255—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using diodes as protective elements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Amplifiers (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Protection Of Static Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置、特に絶蒜ケ゛−１・形亀界効果ト
ランジスタ（以下、ＭＯＳ − ＦＥＴと称する）の保
護ダイオードに関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly to a protection diode for a silica-1 type turtle field effect transistor (hereinafter referred to as MOS-FET).
一般にＭＯＳ− ＦＥＴは、入カグ〜ト端子にサー−）
電圧が印加されたときにダート絶縁膜がｎ電破壊される
ことを防止するだめの保護ダイオードが接続きれている
。すなわち、第１図（ａ） ｔ！）るいは（ｂ）に示す
ように、ＭＯＳ − ＦＥＴ １のダート電極（ニ）・
ソース電極（Ｓ）間に並列に、図示の向きで１個のダー
ト保護帯ダイオード２あるいｅまブート保護用の双方向
形のＰＮＰダイオード３が接続されている。なお、上記
ダート保護ダイオード２あるいは３は、殆んどの場合に
ＭＯＳ − ＦＥＴ１と同一の半導体基板上に形成され
ている。In general, MOS-FETs are connected to input terminals.
A protective diode is disconnected to prevent the dart insulating film from being damaged by n-voltage when a voltage is applied. That is, FIG. 1(a) t! ) or as shown in (b), the dart electrode (d) of MOS-FET 1.
A dart protection band diode 2 or a bidirectional PNP diode 3 for boot protection is connected in parallel between the source electrodes (S) in the direction shown. Note that the dirt protection diode 2 or 3 is formed on the same semiconductor substrate as the MOS-FET 1 in most cases.
一方、サージ電流はソース端子４，ドレイン端子５を介
して流れるため、ドレイン端子５については人カグ〜ト
端子６ほどはｆＩｐ竜破壊には注目されていなｂｏしが
し、近年のＭＯＳ − ＦＥＴ１の高性能化に伴ない、
ダート長は非常に短かく（１〜２μ程度）なっておシ、
このためにドレインのＰＮジャンクションは電界が集中
し、静電破壊が生じ易くなシ、またドレイン端のダート
絶縁膜の破壊も起し易くなっておシ、ドレイン端子５に
ついても静電破壊防止策が必要になっている。On the other hand, since the surge current flows through the source terminal 4 and the drain terminal 5, it seems that the drain terminal 5 has not received as much attention as the input terminal 6 for fIp damage, and in recent years MOS-FET1 As the performance of
The dirt length is very short (about 1 to 2μ),
For this reason, the electric field concentrates at the PN junction of the drain, making it easy to cause electrostatic damage, and also making it easy to break down the dirt insulating film at the end of the drain.The drain terminal 5 also has measures to prevent electrostatic damage. is now needed.
このようにドレイン端子５の静電破壊防止策を必要とす
る場合、従来は第２図に示すように、ＭＯＳ −ＦＥＴ
７のドレイン端子５とソース端子４との間にドレイン
保護帯ダイオード７が図示の向きに外付は接続されるこ
とがあった。In this way, when it is necessary to take measures to prevent electrostatic damage to the drain terminal 5, as shown in FIG.
In some cases, a drain protection band diode 7 is externally connected between the drain terminal 5 and the source terminal 4 of the device 7 in the direction shown in the figure.
しかし、上記したようにドレイン保１１ダイオード７を
外付けすることは、ＭＯＳ −ＦＥＴ １およびケ゛−
ト保護帯ダイオード３（あるいは２）を有する半導体装
置とは別個の素子（ドレイン保護用ダイオード７）を特
別に必要とし、′まだ外付けのための組立工数が増加す
るので、ドレインの静電破壊防止のだめの費用が高くつ
く欠点があった。However, as mentioned above, externally attaching the drain protection 11 diode 7
A separate element (drain protection diode 7) is specially required from the semiconductor device having the protection band diode 3 (or 2), and the number of assembly steps required for external attachment is still increased, so that electrostatic damage to the drain is prevented. The drawback was that the cost of prevention was high.
〔発明の目的〕
本発明は上記の事情に鑑みてなされたもので、ＭＯＳ
−ＦＥＴに対して別個に形成されたドレイン保護用ダイ
オードを例付けすることなくΔ’ＩＯ８−ＦＥＴのドレ
イン端子の静電破壊を防止でき、し。[Object of the invention] The present invention has been made in view of the above circumstances, and it
Electrostatic damage to the drain terminal of the Δ'IO8-FET can be prevented without providing a separate drain protection diode for the FET.
かも安価に実現可能な半導体装置を提供するものである
。Moreover, the present invention provides a semiconductor device that can be realized at low cost.
すなわち、本発明の半導体装置は、ＭＯＳ −ＦＥ’Ｉ
’が形成された半導体基板上で上記トラン・ゾスタの動
作領域以外の近傍に保Ｗａｆｔダイオードを形成し、こ
の保護附ダイオードの両端を各対応して前記トランジス
タのソース電極およびドレイン電極に接続してなること
を特徴とするものである。That is, the semiconductor device of the present invention has a MOS-FE'I
A protection Waft diode is formed in the vicinity of the transistor except the operating area on the semiconductor substrate on which the transistor is formed, and both ends of the protection diode are connected to the source electrode and the drain electrode of the transistor, respectively. It is characterized by:
したがって、上記保護ダイオードの耐圧をＭＯＳ −Ｆ
ＥＴのドレイン耐圧よシも低く設削しておくことによっ
て、ＭＯＳ −ＦＥＴのドレイン端子へのサージ印加時
に上記ダイオードによる保許がなされ、ドレイン端子の
静電破壊が防止されるようになる。Therefore, the withstand voltage of the protection diode is MOS -F
By setting the drain breakdown voltage of the ET to be low, the diode provides protection when a surge is applied to the drain terminal of the MOS-FET, and electrostatic damage to the drain terminal is prevented.
以下、図面を参照して本発明の一実施例を詳細に説明す
る。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings.
第３図１において、１０は八ｉ０ｓ −Ｆ’ＥＴ 、
Ｉ Ｊは入力ダート端子、１２はソース端子、１３は
ドレイン端子、１４は上記ＭＯ８−ＦＥＴ １０のダー
ト電極Ｇ・ソース電極Ｓ間に並列に設けられたケ゛−ト
保護用の双方向形のＰＮＰダイオード、１５は前記ＭＱ
Ｓ −ＦＥＴ １０のドレイン電極Ｄ・ソース電極Ｓ間
に並列に設けられたドレイン保護用の双方向形のＰＮＰ
ダイオードである。上記ダート保護ダイオード１４およ
びドレイン保Ｐ件ダイメート１５−一、第１４図に示す
ようにＭＯＳ−ＦＥＴ １０と同一の半導体基板（たと
えばＰ形シリコン基板）１６上においてＭＯＳ −ＦＥ
Ｔ ７ 。In FIG. 3 1, 10 is 8 i0s −F'ET,
IJ is an input dart terminal, 12 is a source terminal, 13 is a drain terminal, and 14 is a bidirectional PNP for gate protection provided in parallel between the dirt electrode G and source electrode S of the MO8-FET 10. Diode, 15 is the MQ
Bidirectional PNP for drain protection provided in parallel between drain electrode D and source electrode S of S-FET 10
It is a diode. As shown in FIG.
T7.
の動作領域以外に設けられ、ドレイン保護帯ダイオード
１５はＭＯＳ −ＦＥＴ １０のドレイン領域近傍に形
成されている。The drain protection band diode 15 is formed near the drain region of the MOS-FET 10.
第４図において、１７は前記ｍｏｓ −ＦＥＴ Ｊ 。In FIG. 4, 17 is the mos-FET J.
のソース領域（Ｎｌ）、１８はソース電極、ノ９はドレ
イン領域（Ｎｌ）、２０はドレイン電極、２ノはダート
絶縁膜（ｓｔｏ２）、２２はダート電極であり、上記Ｌ
ＩＯ８−ＦＥ’ｒ １０ ｔ、ｉ Ｎ ｆ、ｙ ンネル
のシングルケ“−ト形式として＋１・７成されている。18 is a source electrode, 9 is a drain region (Nl), 20 is a drain electrode, 2 is a dirt insulating film (sto2), 22 is a dirt electrode,
It is configured as a single-gate format of the IO8-FE'r 10 t, i N f, y channel.
一方、２３は前記ダート保ｉ乃用のＰＮＰダイ」−Ｐｌ
（における第１のアノードであってＰ＋領域よシなり、
２４は同じく上記ＰＮＰダイ刊−ビードにおけるカソー
ド２４であってＮ ＪＰｑよりなｐ、前記Ｐ形基板１６
は上記ＰＮＩ）ダイメート１４の第２のアノードとなっ
ている。上記アノード２３上にはアノード電極２５が形
成され、このアノード電極２５は前記ケ゛−１・電極２
２と共に入力ダート端子１１に接続されている。オだ、
２６は前記ドレイン保護用のＰＮＰダイオード１５にお
ける第１のアノ−ド２６であってＰ＋領域よシなシ、２
７は同じく−１：記１１”Ｎｌ）ダイオード１５におけ
るカソードであってＮ層よりなり、前記Ｐ形基板１６は
上記ＰＮＰダイオード１５の第２のアノードとなってい
る。上１；［シアノード２６上にはアノード電極２８が
形成され、このアノード電極２８は前記ドレイン電極２
ｏと共に１゛レイン端子１３に接続されている。On the other hand, 23 is the PNP die for the dirt protection
(the first anode in the P+ region,
24 is the cathode 24 in the PNP die publication-bead, which is also from NJPq, and the P-type substrate 16.
is the second anode of the PNI) dimate 14 described above. An anode electrode 25 is formed on the anode 23, and this anode electrode 25 is connected to the case-1 electrode 2.
2 and is connected to the input dart terminal 11. Oh yeah
26 is the first anode 26 of the PNP diode 15 for drain protection, which is similar to the P+ region;
7 is the cathode in the diode 15 (-1: 11"Nl) made of an N layer, and the P-type substrate 16 serves as the second anode of the PNP diode 15. Top 1; [on the cyanode 26] An anode electrode 28 is formed in the drain electrode 2.
It is connected to the 1'' rain terminal 13 together with 0.
なお、前記ソース端子１２は半導体基板１６と同電位に
設定されておシ、換言すればり８−ト保穫僻ダイオード
１４の第２のアノードおよびドレイン保護帯ダイオード
１５の第２のアノードはＨｏ８− ＦＥＴ １０のソー
ス電極Ｓに接続されている。Note that the source terminal 12 is set to the same potential as the semiconductor substrate 16. In other words, the second anode of the 8-band protection band diode 14 and the second anode of the drain protection band diode 15 are set to the same potential as the semiconductor substrate 16. It is connected to the source electrode S of the FET 10.
上記構成の半導体装置は、第１図（ｂ） を参照して前
述した従来例の半導体装置に比べてドレイン保護帯ダイ
オード１５が同一半導体基板上に追加されたものであシ
、ダート保護帯ダイオード１４によるＨｏ８− ＦＥ’
ｒ １０のダート保護動作は従来通り行なわれる１、そ
ｌノＣ、ドレイン保護帯ダイオード１５の耐圧をＨｏ８
− ＦＥｉ” １０のドレイン耐圧よシも低く設計して
おくことによシ、ドレイン端子１３へのサージ印加時に
ドレイン保護帯ダイオード１５がＨｏ８− ＦＥＴ ｉ
Ｏのドレインの静電破壊を防止するようになる。たと
えば、ドレイン保護形ダイオード１５のカソード２７と
なるＮ層の濃度を１０１７〜１８ ／ＣＣに選ぶことに
より、このダイオード１５の耐圧を約２０Ｖにすること
ができ、これｖ；Ｌ近年の低電圧動作用の八・ＩＯ８−
ＦＥＴのドし／イン保洒用として充分な耐圧である。The semiconductor device having the above structure has a drain guard diode 15 added on the same semiconductor substrate as compared to the conventional semiconductor device described above with reference to FIG. 1(b). Ho8-FE' by 14
The dirt protection operation of r10 is performed as before.
- By designing the drain withstand voltage of the FEi" 10 to be low, the drain protection band diode 15 is connected to the Ho8-FET i when a surge is applied to the drain terminal 13.
This prevents electrostatic damage to the O drain. For example, by selecting the concentration of the N layer that becomes the cathode 27 of the drain protection diode 15 to be 1017 to 18 /CC, the withstand voltage of this diode 15 can be made approximately 20V, which is v; 8・IO8-
It has sufficient pressure resistance for FET do/in protection.
上）ホしたようなＨｏ５− ＦｇＴ’−ｉコンデンザチ
ャージ法によシ静電破壊試験を行なった結果、コンデン
゛す容量が２００ ＰＦの場合にドしイン端子１３の平
均耐騎は５００ｖであり、ドレイン保護甜ダイオード１
５を鳴さ万い従来例のＨｏ８− ＦＥＴのそれが２００
ｖであるのに比べて非常に有効であった。As a result of conducting an electrostatic discharge test using the Ho5-FgT'-i capacitor charging method as shown above, when the capacitance is 200 PF, the average resistance of the input terminal 13 is 500 V. Yes, drain protection diode 1
The conventional Ho8-FET that sounds 5 is 200.
It was very effective compared to v.
なお、前記ドレイン保Ｈφ俗ダイオード１５は、ダート
保にφ坩ダイオード１４の形成時に同時に同一工程で形
成可能である。The drain holding Hφ general diode 15 can be formed in the same process at the same time as forming the drain holding Hφ converting diode 14.
また、上記実施例はＮチャンネルＨｏ８− ＦＥＴを示
したが、ＰチャンネルＭＯ３−ＦＥＴの場合にも上記実
施例に準じて本発明を適用可能である。Further, although the above embodiment shows an N-channel Ho8-FET, the present invention can also be applied to a P-channel MO3-FET according to the above embodiment.
才だ、」二記ツＪ施例ではドレイン保護用ダイメート１
５として双方向形ダイオードをｔＦ、 成したので、ド
レインの静電容量の」す−７加を押えることができるが
、これに限らずド１／イン・ノース間に並列に１個のＰ
Ｎ接合ダイオードを設けるようにしてもよい。In the second example, dyemate 1 for drain protection is used.
Since a bidirectional diode is formed as tF as 5, it is possible to suppress the drain capacitance.
An N-junction diode may also be provided.
上述したように本発明の半導体装置によれば、Ｈｏ８−
ＦＥＴのドレイン保護帯ダイオードをＨｏ８−Ｆｆ２
Ｔと同じ半導体基板上に形成したので、Ｈｏ８−ＦＥＴ
に対して別個に形成されたドレイン保護形ダイオードを
外付けすることな（Ｈｏ８− ＦＥＴのドレイン端子の
静電破壊を防止でき、またドレイン保護帯ダイオードの
外付けのだめの組立が不要になるので安価に実現できる
。As described above, according to the semiconductor device of the present invention, Ho8-
FET drain protection band diode Ho8-Ff2
Since it was formed on the same semiconductor substrate as T, Ho8-FET
It is possible to prevent electrostatic damage to the drain terminal of the Ho8-FET by externally attaching a separately formed drain protection diode to the drain protection diode. can be realized.
第１図（ａ） （ｂ）はそれぞれ従来のケ゛−ト保護坩
ダイオード付きＨｏ８− ＦＥＴを示す回路図、第２図
はドレイン保護帯ダイオードを外付けしたＨｏ８− Ｆ
ＥＴを示す回路図、第３図は本発明に係る半導体装置の
一実施例に係るドレイン保護坩ダイオード付きＨｏ３−
ＦＥＴを示す回路図、第４図は第３図の装置の断面構
造を示す図である。
１０・・・Ｈｏ８− ＦＥＴ、 １２・・・ソース端
子、１３・・・ドレイン端子、１５・・・ドレイン保護
帯ダイオード、１８・・・ソース電律、２０・・・ドレ
イン電極。Figures 1 (a) and (b) are circuit diagrams showing a conventional Ho8-FET with a gate protection crucible diode, and Figure 2 is a circuit diagram of a Ho8-FET with an external drain protection diode.
FIG. 3 is a circuit diagram showing the ET, and FIG.
FIG. 4 is a circuit diagram showing an FET, and FIG. 4 is a diagram showing a cross-sectional structure of the device shown in FIG. 3. DESCRIPTION OF SYMBOLS 10...Ho8-FET, 12... Source terminal, 13... Drain terminal, 15... Drain protection band diode, 18... Source electric current, 20... Drain electrode.
Claims (2)
半導体基板上で上記トランジスタの動作領域以外の近傍
に保設ダイオードが形成され、この保護ダイオードの両
端が前記トランジスタのソース電極およびドレイン電極
にそれぞれ対応して接続てれてなることを特徴とする半
導体装置。(1) On the semiconductor substrate on which the insulating dart type field effect transistor is formed, a protection diode is formed in the vicinity of the transistor other than the operating area, and both ends of this protection diode correspond to the source electrode and drain electrode of the transistor, respectively. A semiconductor device characterized in that it can be connected and connected.
ードであることを特徴とする特許 の範囲第１項記載の半導体装置。(2) The semiconductor device according to item 1 of the patent, wherein the protection diode is a bidirectional PN)) diode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57155501A JPS5944872A (en) | 1982-09-07 | 1982-09-07 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57155501A JPS5944872A (en) | 1982-09-07 | 1982-09-07 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5944872A true JPS5944872A (en) | 1984-03-13 |
Family
ID=15607422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57155501A Pending JPS5944872A (en) | 1982-09-07 | 1982-09-07 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5944872A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63110958A (en) * | 1986-10-28 | 1988-05-16 | Fuji Elelctrochem Co Ltd | Bridge type switching power source |
| EP0645817A1 (en) * | 1993-08-24 | 1995-03-29 | Motorola, Inc. | Diode protected semiconductor device |
| US5777367A (en) * | 1993-09-30 | 1998-07-07 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated structure active clamp for the protection of power devices against overvoltages |
| JP2013219246A (en) * | 2012-04-10 | 2013-10-24 | Mitsubishi Electric Corp | Protection diode |
-
1982
- 1982-09-07 JP JP57155501A patent/JPS5944872A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63110958A (en) * | 1986-10-28 | 1988-05-16 | Fuji Elelctrochem Co Ltd | Bridge type switching power source |
| JPH0357707B2 (en) * | 1986-10-28 | 1991-09-03 | Fuji Electrochemical Co Ltd | |
| EP0645817A1 (en) * | 1993-08-24 | 1995-03-29 | Motorola, Inc. | Diode protected semiconductor device |
| US5777367A (en) * | 1993-09-30 | 1998-07-07 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno | Integrated structure active clamp for the protection of power devices against overvoltages |
| JP2013219246A (en) * | 2012-04-10 | 2013-10-24 | Mitsubishi Electric Corp | Protection diode |
| US8907424B2 (en) | 2012-04-10 | 2014-12-09 | Mitsubishi Electric Corporation | Protection diode |
| US9202907B2 (en) | 2012-04-10 | 2015-12-01 | Mitsubishi Electric Corporation | Protection diode |
| US9202908B2 (en) | 2012-04-10 | 2015-12-01 | Mitsubishi Electric Corporation | Protection diode |
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